1 //==== SPUInstrFormats.td - Cell SPU Instruction Formats ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // Cell SPU instruction formats. Note that these are notationally similar to
13 // PowerPC, like "A-Form". But the sizes of operands and fields differ.
15 // This was kiped from the PPC instruction formats (seemed like a good idea...)
17 class SPUInstr<dag OOL, dag IOL, string asmstr, InstrItinClass itin>
21 let Namespace = "SPU";
22 let OutOperandList = OOL;
23 let InOperandList = IOL;
24 let AsmString = asmstr;
29 class RRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr,
30 InstrItinClass itin, list<dag> pattern>
31 : SPUInstr<OOL, IOL, asmstr, itin> {
36 let Pattern = pattern;
38 let Inst{0-10} = opcode;
45 // RR Format, where RB is zeroed (dont care):
46 class RRForm_1<bits<11> opcode, dag OOL, dag IOL, string asmstr,
47 InstrItinClass itin, list<dag> pattern>
48 : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
52 // RR Format, where RA and RB are zeroed (dont care):
53 // Used for reads from status control registers (see FPSCRRr32)
54 class RRForm_2<bits<11> opcode, dag OOL, dag IOL, string asmstr,
55 InstrItinClass itin, list<dag> pattern>
56 : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
62 // RR Format, where RT is zeroed (don't care), or as the instruction handbook
63 // says, "RT is a false target." Used in "Halt if" instructions
64 class RRForm_3<bits<11> opcode, dag OOL, dag IOL, string asmstr,
65 InstrItinClass itin, list<dag> pattern>
66 : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
71 class RRRForm<bits<4> opcode, dag OOL, dag IOL, string asmstr,
72 InstrItinClass itin, list<dag> pattern>
73 : SPUInstr<OOL, IOL, asmstr, itin>
80 let Pattern = pattern;
82 let Inst{0-3} = opcode;
90 class RI7Form<bits<11> opcode, dag OOL, dag IOL, string asmstr,
91 InstrItinClass itin, list<dag> pattern>
92 : SPUInstr<OOL, IOL, asmstr, itin>
98 let Pattern = pattern;
100 let Inst{0-10} = opcode;
101 let Inst{11-17} = i7;
102 let Inst{18-24} = RA;
103 let Inst{25-31} = RT;
107 class CVTIntFPForm<bits<10> opcode, dag OOL, dag IOL, string asmstr,
108 InstrItinClass itin, list<dag> pattern>
109 : SPUInstr<OOL, IOL, asmstr, itin>
114 let Pattern = pattern;
116 let Inst{0-9} = opcode;
118 let Inst{18-24} = RA;
119 let Inst{25-31} = RT;
123 class BICondForm<bits<11> opcode, string asmstr, list<dag> pattern>
124 : RRForm<opcode, (outs), (ins R32C:$rA, R32C:$func), asmstr,
125 BranchResolv, pattern>
129 // Branch instruction format (without D/E flag settings)
130 class BRForm<bits<11> opcode, dag OOL, dag IOL, string asmstr,
131 InstrItinClass itin, list<dag> pattern>
132 : RRForm<opcode, OOL, IOL, asmstr, itin, pattern>
135 class BIForm<bits<11> opcode, string asmstr, list<dag> pattern>
136 : RRForm<opcode, (outs), (ins R32C:$func), asmstr, BranchResolv,
141 // Return instruction (bi, branch indirect), RA is zero (LR):
142 class RETForm<string asmstr, list<dag> pattern>
143 : BRForm<0b00010101100, (outs), (ins), asmstr, BranchResolv,
150 // Branch indirect external data forms:
151 class BISLEDForm<bits<2> DE_flag, string asmstr, list<dag> pattern>
152 : SPUInstr<(outs), (ins indcalltarget:$func), asmstr, BranchResolv>
156 let Pattern = pattern;
158 let Inst{0-10} = 0b11010101100;
160 let Inst{12-13} = DE_flag;
161 let Inst{14-17} = 0b0000;
162 let Inst{18-24} = Rcalldest;
163 let Inst{25-31} = 0b0000000;
167 class RI10Form<bits<8> opcode, dag OOL, dag IOL, string asmstr,
168 InstrItinClass itin, list<dag> pattern>
169 : SPUInstr<OOL, IOL, asmstr, itin>
175 let Pattern = pattern;
177 let Inst{0-7} = opcode;
178 let Inst{8-17} = i10;
179 let Inst{18-24} = RA;
180 let Inst{25-31} = RT;
183 // RI10 Format, where the constant is zero (or effectively ignored by the
186 class RI10Form_1<bits<8> opcode, dag OOL, dag IOL, string asmstr,
187 InstrItinClass itin, list<dag> pattern>
188 : RI10Form<opcode, OOL, IOL, asmstr, itin, pattern>
192 // RI10 Format, where RT is ignored.
193 // This format is used primarily by the Halt If ... Immediate set of
196 class RI10Form_2<bits<8> opcode, dag OOL, dag IOL, string asmstr,
197 InstrItinClass itin, list<dag> pattern>
198 : RI10Form<opcode, OOL, IOL, asmstr, itin, pattern>
203 class RI16Form<bits<9> opcode, dag OOL, dag IOL, string asmstr,
204 InstrItinClass itin, list<dag> pattern>
205 : SPUInstr<OOL, IOL, asmstr, itin>
210 let Pattern = pattern;
212 let Inst{0-8} = opcode;
213 let Inst{9-24} = i16;
214 let Inst{25-31} = RT;
217 // Specialized version of the RI16 Format for unconditional branch relative and
218 // branch absolute, branch and set link. Note that for branch and set link, the
219 // link register doesn't have to be $lr, but this is actually hard coded into
220 // the instruction pattern.
223 class UncondBranch<bits<9> opcode, dag OOL, dag IOL, string asmstr,
225 : RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
228 class BranchSetLink<bits<9> opcode, dag OOL, dag IOL, string asmstr,
230 : RI16Form<opcode, OOL, IOL, asmstr, BranchResolv, pattern>
234 //===----------------------------------------------------------------------===//
235 // Specialized versions of RI16:
236 //===----------------------------------------------------------------------===//
239 class RI18Form<bits<7> opcode, dag OOL, dag IOL, string asmstr,
240 InstrItinClass itin, list<dag> pattern>
241 : SPUInstr<OOL, IOL, asmstr, itin>
246 let Pattern = pattern;
248 let Inst{0-6} = opcode;
249 let Inst{7-24} = i18;
250 let Inst{25-31} = RT;
253 //===----------------------------------------------------------------------===//
254 // Instruction formats for intrinsics:
255 //===----------------------------------------------------------------------===//
257 // RI10 Format for v8i16 intrinsics
258 class RI10_Int_v8i16<bits<8> opcode, string opc, InstrItinClass itin,
260 RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
261 !strconcat(opc, " $rT, $rA, $val"), itin,
262 [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
263 i16ImmSExt10:$val))] >;
265 class RI10_Int_v4i32<bits<8> opcode, string opc, InstrItinClass itin,
267 RI10Form<opcode, (outs VECREG:$rT), (ins s10imm:$val, VECREG:$rA),
268 !strconcat(opc, " $rT, $rA, $val"), itin,
269 [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
270 i32ImmSExt10:$val))] >;
272 // RR Format for v8i16 intrinsics
273 class RR_Int_v8i16<bits<11> opcode, string opc, InstrItinClass itin,
275 RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
276 !strconcat(opc, " $rT, $rA, $rB"), itin,
277 [(set (v8i16 VECREG:$rT), (IntID (v8i16 VECREG:$rA),
278 (v8i16 VECREG:$rB)))] >;
280 // RR Format for v4i32 intrinsics
281 class RR_Int_v4i32<bits<11> opcode, string opc, InstrItinClass itin,
283 RRForm<opcode, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
284 !strconcat(opc, " $rT, $rA, $rB"), itin,
285 [(set (v4i32 VECREG:$rT), (IntID (v4i32 VECREG:$rA),
286 (v4i32 VECREG:$rB)))] >;
288 //===----------------------------------------------------------------------===//
289 // Pseudo instructions, like call frames:
290 //===----------------------------------------------------------------------===//
292 class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern>
293 : SPUInstr<OOL, IOL, asmstr, NoItinerary> {
294 let Pattern = pattern;