1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/Streams.h"
24 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
25 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
27 RI(*TM.getSubtargetImpl(), *this)
32 /// getPointerRegClass - Return the register class to use to hold pointers.
33 /// This is used for addressing modes.
34 const TargetRegisterClass *
35 SPUInstrInfo::getPointerRegClass() const
37 return &SPU::R32CRegClass;
41 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
43 unsigned& destReg) const {
44 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
45 // cases where we can safely say that what's being done is really a move
46 // (see how PowerPC does this -- it's the model for this code too.)
47 switch (MI.getOpcode()) {
62 assert(MI.getNumOperands() == 3 &&
63 MI.getOperand(0).isRegister() &&
64 MI.getOperand(1).isRegister() &&
65 MI.getOperand(2).isImmediate() &&
66 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
67 if (MI.getOperand(2).getImm() == 0) {
68 sourceReg = MI.getOperand(1).getReg();
69 destReg = MI.getOperand(0).getReg();
74 assert(MI.getNumOperands() == 3 &&
75 "wrong number of operands to AIr32");
76 if (MI.getOperand(0).isRegister() &&
77 (MI.getOperand(1).isRegister() ||
78 MI.getOperand(1).isFrameIndex()) &&
79 (MI.getOperand(2).isImmediate() &&
80 MI.getOperand(2).getImm() == 0)) {
81 sourceReg = MI.getOperand(1).getReg();
82 destReg = MI.getOperand(0).getReg();
87 case SPU::ORv8i16_i16:
88 case SPU::ORv4i32_i32:
89 case SPU::ORv2i64_i64:
90 case SPU::ORv4f32_f32:
91 case SPU::ORv2f64_f64:
93 case SPU::ORi16_v8i16:
94 case SPU::ORi32_v4i32:
95 case SPU::ORi64_v2i64:
96 case SPU::ORf32_v4f32:
97 case SPU::ORf64_v2f64:
105 assert(MI.getNumOperands() == 3 &&
106 MI.getOperand(0).isRegister() &&
107 MI.getOperand(1).isRegister() &&
108 MI.getOperand(2).isRegister() &&
109 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
110 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
111 sourceReg = MI.getOperand(1).getReg();
112 destReg = MI.getOperand(0).getReg();
122 SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
123 switch (MI->getOpcode()) {
139 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
140 MI->getOperand(2).isFrameIndex()) {
141 FrameIndex = MI->getOperand(2).getIndex();
142 return MI->getOperand(0).getReg();
150 SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
151 switch (MI->getOpcode()) {
173 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
174 MI->getOperand(2).isFrameIndex()) {
175 FrameIndex = MI->getOperand(2).getIndex();
176 return MI->getOperand(0).getReg();
183 bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator MI,
185 unsigned DestReg, unsigned SrcReg,
186 const TargetRegisterClass *DestRC,
187 const TargetRegisterClass *SrcRC) const
189 // We support cross register class moves for our aliases, such as R3 in any
190 // reg class to any other reg class containing R3. This is required because
191 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
192 // types have no specific meaning.
194 //if (DestRC != SrcRC) {
195 // cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
199 if (DestRC == SPU::R8CRegisterClass) {
200 BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
201 } else if (DestRC == SPU::R16CRegisterClass) {
202 BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
203 } else if (DestRC == SPU::R32CRegisterClass) {
204 BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
205 } else if (DestRC == SPU::R32FPRegisterClass) {
206 BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
208 } else if (DestRC == SPU::R64CRegisterClass) {
209 BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
211 } else if (DestRC == SPU::R64FPRegisterClass) {
212 BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
214 } /* else if (DestRC == SPU::GPRCRegisterClass) {
215 BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
217 } */ else if (DestRC == SPU::VECREGRegisterClass) {
218 BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
221 // Attempt to copy unknown/unsupported register class!
229 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
230 MachineBasicBlock::iterator MI,
231 unsigned SrcReg, bool isKill, int FrameIdx,
232 const TargetRegisterClass *RC) const
235 if (RC == SPU::GPRCRegisterClass) {
236 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
239 } else if (RC == SPU::R64CRegisterClass) {
240 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
243 } else if (RC == SPU::R64FPRegisterClass) {
244 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
247 } else if (RC == SPU::R32CRegisterClass) {
248 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
251 } else if (RC == SPU::R32FPRegisterClass) {
252 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
255 } else if (RC == SPU::R16CRegisterClass) {
256 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
260 assert(0 && "Unknown regclass!");
264 addFrameReference(BuildMI(MBB, MI, get(opc))
265 .addReg(SrcReg, false, false, isKill), FrameIdx);
268 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
270 SmallVectorImpl<MachineOperand> &Addr,
271 const TargetRegisterClass *RC,
272 SmallVectorImpl<MachineInstr*> &NewMIs) const {
273 cerr << "storeRegToAddr() invoked!\n";
276 if (Addr[0].isFrameIndex()) {
277 /* do what storeRegToStackSlot does here */
280 if (RC == SPU::GPRCRegisterClass) {
281 /* Opc = PPC::STW; */
282 } else if (RC == SPU::R16CRegisterClass) {
283 /* Opc = PPC::STD; */
284 } else if (RC == SPU::R32CRegisterClass) {
285 /* Opc = PPC::STFD; */
286 } else if (RC == SPU::R32FPRegisterClass) {
287 /* Opc = PPC::STFD; */
288 } else if (RC == SPU::R64FPRegisterClass) {
289 /* Opc = PPC::STFS; */
290 } else if (RC == SPU::VECREGRegisterClass) {
291 /* Opc = PPC::STVX; */
293 assert(0 && "Unknown regclass!");
296 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
297 .addReg(SrcReg, false, false, isKill);
298 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
299 MachineOperand &MO = Addr[i];
301 MIB.addReg(MO.getReg());
302 else if (MO.isImmediate())
303 MIB.addImm(MO.getImm());
305 MIB.addFrameIndex(MO.getIndex());
307 NewMIs.push_back(MIB);
312 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
313 MachineBasicBlock::iterator MI,
314 unsigned DestReg, int FrameIdx,
315 const TargetRegisterClass *RC) const
318 if (RC == SPU::GPRCRegisterClass) {
319 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
322 } else if (RC == SPU::R64CRegisterClass) {
323 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
326 } else if (RC == SPU::R64FPRegisterClass) {
327 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
330 } else if (RC == SPU::R32CRegisterClass) {
331 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
334 } else if (RC == SPU::R32FPRegisterClass) {
335 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
338 } else if (RC == SPU::R16CRegisterClass) {
339 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
343 assert(0 && "Unknown regclass in loadRegFromStackSlot!");
347 addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
351 \note We are really pessimistic here about what kind of a load we're doing.
353 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
354 SmallVectorImpl<MachineOperand> &Addr,
355 const TargetRegisterClass *RC,
356 SmallVectorImpl<MachineInstr*> &NewMIs)
358 cerr << "loadRegToAddr() invoked!\n";
361 if (Addr[0].isFrameIndex()) {
362 /* do what loadRegFromStackSlot does here... */
365 if (RC == SPU::R8CRegisterClass) {
366 /* do brilliance here */
367 } else if (RC == SPU::R16CRegisterClass) {
368 /* Opc = PPC::LWZ; */
369 } else if (RC == SPU::R32CRegisterClass) {
371 } else if (RC == SPU::R32FPRegisterClass) {
372 /* Opc = PPC::LFD; */
373 } else if (RC == SPU::R64FPRegisterClass) {
374 /* Opc = PPC::LFS; */
375 } else if (RC == SPU::VECREGRegisterClass) {
376 /* Opc = PPC::LVX; */
377 } else if (RC == SPU::GPRCRegisterClass) {
378 /* Opc = something else! */
380 assert(0 && "Unknown regclass!");
383 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
384 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
385 MachineOperand &MO = Addr[i];
387 MIB.addReg(MO.getReg());
388 else if (MO.isImmediate())
389 MIB.addImm(MO.getImm());
391 MIB.addFrameIndex(MO.getIndex());
393 NewMIs.push_back(MIB);
397 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
398 /// copy instructions, turning them into load/store instructions.
400 SPUInstrInfo::foldMemoryOperand(MachineFunction &MF,
402 SmallVectorImpl<unsigned> &Ops,
403 int FrameIndex) const
405 #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
406 if (Ops.size() != 1) return NULL;
408 unsigned OpNum = Ops[0];
409 unsigned Opc = MI->getOpcode();
410 MachineInstr *NewMI = 0;
412 if ((Opc == SPU::ORr32
413 || Opc == SPU::ORv4i32)
414 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
415 if (OpNum == 0) { // move -> store
416 unsigned InReg = MI->getOperand(1).getReg();
417 bool isKill = MI->getOperand(1).isKill();
418 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
419 NewMI = addFrameReference(BuildMI(MF, TII.get(SPU::STQDr32))
420 .addReg(InReg, false, false, isKill),
423 } else { // move -> load
424 unsigned OutReg = MI->getOperand(0).getReg();
425 bool isDead = MI->getOperand(0).isDead();
426 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
427 ? SPU::STQDr32 : SPU::STQXr32;
428 NewMI = addFrameReference(BuildMI(MF, TII.get(Opc))
429 .addReg(OutReg, true, false, false, isDead), FrameIndex);