1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/Streams.h"
24 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
25 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
27 RI(*TM.getSubtargetImpl(), *this)
32 /// getPointerRegClass - Return the register class to use to hold pointers.
33 /// This is used for addressing modes.
34 const TargetRegisterClass *
35 SPUInstrInfo::getPointerRegClass() const
37 return &SPU::R32CRegClass;
41 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
43 unsigned& destReg) const {
44 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
45 // cases where we can safely say that what's being done is really a move
46 // (see how PowerPC does this -- it's the model for this code too.)
47 switch (MI.getOpcode()) {
62 assert(MI.getNumOperands() == 3 &&
63 MI.getOperand(0).isRegister() &&
64 MI.getOperand(1).isRegister() &&
65 MI.getOperand(2).isImmediate() &&
66 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
67 if (MI.getOperand(2).getImm() == 0) {
68 sourceReg = MI.getOperand(1).getReg();
69 destReg = MI.getOperand(0).getReg();
74 assert(MI.getNumOperands() == 3 &&
75 "wrong number of operands to AIr32");
76 if (MI.getOperand(0).isRegister() &&
77 (MI.getOperand(1).isRegister() ||
78 MI.getOperand(1).isFrameIndex()) &&
79 (MI.getOperand(2).isImmediate() &&
80 MI.getOperand(2).getImm() == 0)) {
81 sourceReg = MI.getOperand(1).getReg();
82 destReg = MI.getOperand(0).getReg();
87 case SPU::ORv8i16_i16:
88 case SPU::ORv4i32_i32:
89 case SPU::ORv2i64_i64:
90 case SPU::ORv4f32_f32:
91 case SPU::ORv2f64_f64:
93 case SPU::ORi16_v8i16:
94 case SPU::ORi32_v4i32:
95 case SPU::ORi64_v2i64:
96 case SPU::ORf32_v4f32:
97 case SPU::ORf64_v2f64:
105 assert(MI.getNumOperands() == 3 &&
106 MI.getOperand(0).isRegister() &&
107 MI.getOperand(1).isRegister() &&
108 MI.getOperand(2).isRegister() &&
109 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
110 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
111 sourceReg = MI.getOperand(1).getReg();
112 destReg = MI.getOperand(0).getReg();
122 SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
123 switch (MI->getOpcode()) {
139 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
140 MI->getOperand(2).isFrameIndex()) {
141 FrameIndex = MI->getOperand(2).getIndex();
142 return MI->getOperand(0).getReg();
150 SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
151 switch (MI->getOpcode()) {
173 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
174 MI->getOperand(2).isFrameIndex()) {
175 FrameIndex = MI->getOperand(2).getIndex();
176 return MI->getOperand(0).getReg();
183 void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
184 MachineBasicBlock::iterator MI,
185 unsigned DestReg, unsigned SrcReg,
186 const TargetRegisterClass *DestRC,
187 const TargetRegisterClass *SrcRC) const
189 // We support cross register class moves for our aliases, such as R3 in any
190 // reg class to any other reg class containing R3. This is required because
191 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
192 // types have no specific meaning.
194 //if (DestRC != SrcRC) {
195 // cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
199 if (DestRC == SPU::R8CRegisterClass) {
200 BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
201 } else if (DestRC == SPU::R16CRegisterClass) {
202 BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
203 } else if (DestRC == SPU::R32CRegisterClass) {
204 BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
205 } else if (DestRC == SPU::R32FPRegisterClass) {
206 BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
208 } else if (DestRC == SPU::R64CRegisterClass) {
209 BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
211 } else if (DestRC == SPU::R64FPRegisterClass) {
212 BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
214 } /* else if (DestRC == SPU::GPRCRegisterClass) {
215 BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
217 } */ else if (DestRC == SPU::VECREGRegisterClass) {
218 BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
221 cerr << "Attempt to copy unknown/unsupported register class!\n";
227 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
228 MachineBasicBlock::iterator MI,
229 unsigned SrcReg, bool isKill, int FrameIdx,
230 const TargetRegisterClass *RC) const
233 if (RC == SPU::GPRCRegisterClass) {
234 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
237 } else if (RC == SPU::R64CRegisterClass) {
238 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
241 } else if (RC == SPU::R64FPRegisterClass) {
242 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
245 } else if (RC == SPU::R32CRegisterClass) {
246 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
249 } else if (RC == SPU::R32FPRegisterClass) {
250 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
253 } else if (RC == SPU::R16CRegisterClass) {
254 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
258 assert(0 && "Unknown regclass!");
262 addFrameReference(BuildMI(MBB, MI, get(opc))
263 .addReg(SrcReg, false, false, isKill), FrameIdx);
266 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
268 SmallVectorImpl<MachineOperand> &Addr,
269 const TargetRegisterClass *RC,
270 SmallVectorImpl<MachineInstr*> &NewMIs) const {
271 cerr << "storeRegToAddr() invoked!\n";
274 if (Addr[0].isFrameIndex()) {
275 /* do what storeRegToStackSlot does here */
278 if (RC == SPU::GPRCRegisterClass) {
279 /* Opc = PPC::STW; */
280 } else if (RC == SPU::R16CRegisterClass) {
281 /* Opc = PPC::STD; */
282 } else if (RC == SPU::R32CRegisterClass) {
283 /* Opc = PPC::STFD; */
284 } else if (RC == SPU::R32FPRegisterClass) {
285 /* Opc = PPC::STFD; */
286 } else if (RC == SPU::R64FPRegisterClass) {
287 /* Opc = PPC::STFS; */
288 } else if (RC == SPU::VECREGRegisterClass) {
289 /* Opc = PPC::STVX; */
291 assert(0 && "Unknown regclass!");
294 MachineInstrBuilder MIB = BuildMI(get(Opc))
295 .addReg(SrcReg, false, false, isKill);
296 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
297 MachineOperand &MO = Addr[i];
299 MIB.addReg(MO.getReg());
300 else if (MO.isImmediate())
301 MIB.addImm(MO.getImm());
303 MIB.addFrameIndex(MO.getIndex());
305 NewMIs.push_back(MIB);
310 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
311 MachineBasicBlock::iterator MI,
312 unsigned DestReg, int FrameIdx,
313 const TargetRegisterClass *RC) const
316 if (RC == SPU::GPRCRegisterClass) {
317 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
320 } else if (RC == SPU::R64CRegisterClass) {
321 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
324 } else if (RC == SPU::R64FPRegisterClass) {
325 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
328 } else if (RC == SPU::R32CRegisterClass) {
329 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
332 } else if (RC == SPU::R32FPRegisterClass) {
333 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
336 } else if (RC == SPU::R16CRegisterClass) {
337 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
341 assert(0 && "Unknown regclass in loadRegFromStackSlot!");
345 addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
349 \note We are really pessimistic here about what kind of a load we're doing.
351 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
352 SmallVectorImpl<MachineOperand> &Addr,
353 const TargetRegisterClass *RC,
354 SmallVectorImpl<MachineInstr*> &NewMIs)
356 cerr << "loadRegToAddr() invoked!\n";
359 if (Addr[0].isFrameIndex()) {
360 /* do what loadRegFromStackSlot does here... */
363 if (RC == SPU::R8CRegisterClass) {
364 /* do brilliance here */
365 } else if (RC == SPU::R16CRegisterClass) {
366 /* Opc = PPC::LWZ; */
367 } else if (RC == SPU::R32CRegisterClass) {
369 } else if (RC == SPU::R32FPRegisterClass) {
370 /* Opc = PPC::LFD; */
371 } else if (RC == SPU::R64FPRegisterClass) {
372 /* Opc = PPC::LFS; */
373 } else if (RC == SPU::VECREGRegisterClass) {
374 /* Opc = PPC::LVX; */
375 } else if (RC == SPU::GPRCRegisterClass) {
376 /* Opc = something else! */
378 assert(0 && "Unknown regclass!");
381 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
382 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
383 MachineOperand &MO = Addr[i];
385 MIB.addReg(MO.getReg());
386 else if (MO.isImmediate())
387 MIB.addImm(MO.getImm());
389 MIB.addFrameIndex(MO.getIndex());
391 NewMIs.push_back(MIB);
395 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
396 /// copy instructions, turning them into load/store instructions.
398 SPUInstrInfo::foldMemoryOperand(MachineFunction &MF,
400 SmallVectorImpl<unsigned> &Ops,
401 int FrameIndex) const
403 #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
404 if (Ops.size() != 1) return NULL;
406 unsigned OpNum = Ops[0];
407 unsigned Opc = MI->getOpcode();
408 MachineInstr *NewMI = 0;
410 if ((Opc == SPU::ORr32
411 || Opc == SPU::ORv4i32)
412 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
413 if (OpNum == 0) { // move -> store
414 unsigned InReg = MI->getOperand(1).getReg();
415 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
416 NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
419 } else { // move -> load
420 unsigned OutReg = MI->getOperand(0).getReg();
421 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
422 NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
427 NewMI->copyKillDeadInfo(MI);