1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/Streams.h"
21 #include "llvm/Support/Debug.h"
26 //! Predicate for an unconditional branch instruction
27 inline bool isUncondBranch(const MachineInstr *I) {
28 unsigned opc = I->getOpcode();
30 return (opc == SPU::BR
35 //! Predicate for a conditional branch instruction
36 inline bool isCondBranch(const MachineInstr *I) {
37 unsigned opc = I->getOpcode();
39 return (opc == SPU::BRNZr32
40 || opc == SPU::BRNZv4i32
42 || opc == SPU::BRZv4i32
43 || opc == SPU::BRHNZr16
44 || opc == SPU::BRHNZv8i16
45 || opc == SPU::BRHZr16
46 || opc == SPU::BRHZv8i16);
50 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
51 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
53 RI(*TM.getSubtargetImpl(), *this)
56 /// getPointerRegClass - Return the register class to use to hold pointers.
57 /// This is used for addressing modes.
58 const TargetRegisterClass *
59 SPUInstrInfo::getPointerRegClass() const
61 return &SPU::R32CRegClass;
65 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
68 unsigned& SrcSR, unsigned& DstSR) const {
69 SrcSR = DstSR = 0; // No sub-registers.
71 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
72 // cases where we can safely say that what's being done is really a move
73 // (see how PowerPC does this -- it's the model for this code too.)
74 switch (MI.getOpcode()) {
89 assert(MI.getNumOperands() == 3 &&
90 MI.getOperand(0).isReg() &&
91 MI.getOperand(1).isReg() &&
92 MI.getOperand(2).isImm() &&
93 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
94 if (MI.getOperand(2).getImm() == 0) {
95 sourceReg = MI.getOperand(1).getReg();
96 destReg = MI.getOperand(0).getReg();
101 assert(MI.getNumOperands() == 3 &&
102 "wrong number of operands to AIr32");
103 if (MI.getOperand(0).isReg() &&
104 MI.getOperand(1).isReg() &&
105 (MI.getOperand(2).isImm() &&
106 MI.getOperand(2).getImm() == 0)) {
107 sourceReg = MI.getOperand(1).getReg();
108 destReg = MI.getOperand(0).getReg();
125 case SPU::ORv16i8_i8:
126 case SPU::ORv8i16_i16:
127 case SPU::ORv4i32_i32:
128 case SPU::ORv2i64_i64:
129 case SPU::ORv4f32_f32:
130 case SPU::ORv2f64_f64:
131 case SPU::ORi8_v16i8:
132 case SPU::ORi16_v8i16:
133 case SPU::ORi32_v4i32:
134 case SPU::ORi64_v2i64:
135 case SPU::ORf32_v4f32:
136 case SPU::ORf64_v2f64:
137 case SPU::ORi128_r64:
138 case SPU::ORi128_f64:
139 case SPU::ORi128_r32:
140 case SPU::ORi128_f32:
141 case SPU::ORi128_r16:
143 case SPU::ORi128_vec:
144 case SPU::ORr64_i128:
145 case SPU::ORf64_i128:
146 case SPU::ORr32_i128:
147 case SPU::ORf32_i128:
148 case SPU::ORr16_i128:
150 case SPU::ORvec_i128:
162 assert(MI.getNumOperands() == 2 &&
163 MI.getOperand(0).isReg() &&
164 MI.getOperand(1).isReg() &&
165 "invalid SPU OR<type>_<vec> or LR instruction!");
166 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
167 sourceReg = MI.getOperand(0).getReg();
168 destReg = MI.getOperand(0).getReg();
183 assert(MI.getNumOperands() == 3 &&
184 MI.getOperand(0).isReg() &&
185 MI.getOperand(1).isReg() &&
186 MI.getOperand(2).isReg() &&
187 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
188 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
189 sourceReg = MI.getOperand(1).getReg();
190 destReg = MI.getOperand(0).getReg();
200 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
201 int &FrameIndex) const {
202 switch (MI->getOpcode()) {
213 const MachineOperand MOp1 = MI->getOperand(1);
214 const MachineOperand MOp2 = MI->getOperand(2);
215 if (MOp1.isImm() && MOp2.isFI()) {
216 FrameIndex = MOp2.getIndex();
217 return MI->getOperand(0).getReg();
226 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
227 int &FrameIndex) const {
228 switch (MI->getOpcode()) {
240 const MachineOperand MOp1 = MI->getOperand(1);
241 const MachineOperand MOp2 = MI->getOperand(2);
242 if (MOp1.isImm() && MOp2.isFI()) {
243 FrameIndex = MOp2.getIndex();
244 return MI->getOperand(0).getReg();
252 bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator MI,
254 unsigned DestReg, unsigned SrcReg,
255 const TargetRegisterClass *DestRC,
256 const TargetRegisterClass *SrcRC) const
258 // We support cross register class moves for our aliases, such as R3 in any
259 // reg class to any other reg class containing R3. This is required because
260 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
261 // types have no specific meaning.
263 if (DestRC == SPU::R8CRegisterClass) {
264 BuildMI(MBB, MI, get(SPU::LRr8), DestReg).addReg(SrcReg);
265 } else if (DestRC == SPU::R16CRegisterClass) {
266 BuildMI(MBB, MI, get(SPU::LRr16), DestReg).addReg(SrcReg);
267 } else if (DestRC == SPU::R32CRegisterClass) {
268 BuildMI(MBB, MI, get(SPU::LRr32), DestReg).addReg(SrcReg);
269 } else if (DestRC == SPU::R32FPRegisterClass) {
270 BuildMI(MBB, MI, get(SPU::LRf32), DestReg).addReg(SrcReg);
271 } else if (DestRC == SPU::R64CRegisterClass) {
272 BuildMI(MBB, MI, get(SPU::LRr64), DestReg).addReg(SrcReg);
273 } else if (DestRC == SPU::R64FPRegisterClass) {
274 BuildMI(MBB, MI, get(SPU::LRf64), DestReg).addReg(SrcReg);
275 } else if (DestRC == SPU::GPRCRegisterClass) {
276 BuildMI(MBB, MI, get(SPU::LRr128), DestReg).addReg(SrcReg);
277 } else if (DestRC == SPU::VECREGRegisterClass) {
278 BuildMI(MBB, MI, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
280 // Attempt to copy unknown/unsupported register class!
288 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
289 MachineBasicBlock::iterator MI,
290 unsigned SrcReg, bool isKill, int FrameIdx,
291 const TargetRegisterClass *RC) const
294 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
295 if (RC == SPU::GPRCRegisterClass) {
296 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
297 } else if (RC == SPU::R64CRegisterClass) {
298 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
299 } else if (RC == SPU::R64FPRegisterClass) {
300 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
301 } else if (RC == SPU::R32CRegisterClass) {
302 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
303 } else if (RC == SPU::R32FPRegisterClass) {
304 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
305 } else if (RC == SPU::R16CRegisterClass) {
306 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
307 } else if (RC == SPU::R8CRegisterClass) {
308 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
309 } else if (RC == SPU::VECREGRegisterClass) {
310 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
312 assert(0 && "Unknown regclass!");
316 addFrameReference(BuildMI(MBB, MI, get(opc))
317 .addReg(SrcReg, false, false, isKill), FrameIdx);
320 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
322 SmallVectorImpl<MachineOperand> &Addr,
323 const TargetRegisterClass *RC,
324 SmallVectorImpl<MachineInstr*> &NewMIs) const {
325 cerr << "storeRegToAddr() invoked!\n";
328 if (Addr[0].isFI()) {
329 /* do what storeRegToStackSlot does here */
332 if (RC == SPU::GPRCRegisterClass) {
333 /* Opc = PPC::STW; */
334 } else if (RC == SPU::R16CRegisterClass) {
335 /* Opc = PPC::STD; */
336 } else if (RC == SPU::R32CRegisterClass) {
337 /* Opc = PPC::STFD; */
338 } else if (RC == SPU::R32FPRegisterClass) {
339 /* Opc = PPC::STFD; */
340 } else if (RC == SPU::R64FPRegisterClass) {
341 /* Opc = PPC::STFS; */
342 } else if (RC == SPU::VECREGRegisterClass) {
343 /* Opc = PPC::STVX; */
345 assert(0 && "Unknown regclass!");
348 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
349 .addReg(SrcReg, false, false, isKill);
350 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
351 MachineOperand &MO = Addr[i];
353 MIB.addReg(MO.getReg());
355 MIB.addImm(MO.getImm());
357 MIB.addFrameIndex(MO.getIndex());
359 NewMIs.push_back(MIB);
364 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
365 MachineBasicBlock::iterator MI,
366 unsigned DestReg, int FrameIdx,
367 const TargetRegisterClass *RC) const
370 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
371 if (RC == SPU::GPRCRegisterClass) {
372 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
373 } else if (RC == SPU::R64CRegisterClass) {
374 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
375 } else if (RC == SPU::R64FPRegisterClass) {
376 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
377 } else if (RC == SPU::R32CRegisterClass) {
378 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
379 } else if (RC == SPU::R32FPRegisterClass) {
380 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
381 } else if (RC == SPU::R16CRegisterClass) {
382 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
383 } else if (RC == SPU::R8CRegisterClass) {
384 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
385 } else if (RC == SPU::VECREGRegisterClass) {
386 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
388 assert(0 && "Unknown regclass in loadRegFromStackSlot!");
392 addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
396 \note We are really pessimistic here about what kind of a load we're doing.
398 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
399 SmallVectorImpl<MachineOperand> &Addr,
400 const TargetRegisterClass *RC,
401 SmallVectorImpl<MachineInstr*> &NewMIs)
403 cerr << "loadRegToAddr() invoked!\n";
406 if (Addr[0].isFI()) {
407 /* do what loadRegFromStackSlot does here... */
410 if (RC == SPU::R8CRegisterClass) {
411 /* do brilliance here */
412 } else if (RC == SPU::R16CRegisterClass) {
413 /* Opc = PPC::LWZ; */
414 } else if (RC == SPU::R32CRegisterClass) {
416 } else if (RC == SPU::R32FPRegisterClass) {
417 /* Opc = PPC::LFD; */
418 } else if (RC == SPU::R64FPRegisterClass) {
419 /* Opc = PPC::LFS; */
420 } else if (RC == SPU::VECREGRegisterClass) {
421 /* Opc = PPC::LVX; */
422 } else if (RC == SPU::GPRCRegisterClass) {
423 /* Opc = something else! */
425 assert(0 && "Unknown regclass!");
428 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
429 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
430 MachineOperand &MO = Addr[i];
432 MIB.addReg(MO.getReg());
434 MIB.addImm(MO.getImm());
436 MIB.addFrameIndex(MO.getIndex());
438 NewMIs.push_back(MIB);
442 //! Return true if the specified load or store can be folded
444 SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
445 const SmallVectorImpl<unsigned> &Ops) const {
446 if (Ops.size() != 1) return false;
448 // Make sure this is a reg-reg copy.
449 unsigned Opc = MI->getOpcode();
462 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
470 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
471 /// copy instructions, turning them into load/store instructions.
473 SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
475 const SmallVectorImpl<unsigned> &Ops,
476 int FrameIndex) const
478 if (Ops.size() != 1) return 0;
480 unsigned OpNum = Ops[0];
481 unsigned Opc = MI->getOpcode();
482 MachineInstr *NewMI = 0;
495 if (OpNum == 0) { // move -> store
496 unsigned InReg = MI->getOperand(1).getReg();
497 bool isKill = MI->getOperand(1).isKill();
498 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
499 MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32));
501 MIB.addReg(InReg, false, false, isKill);
502 NewMI = addFrameReference(MIB, FrameIndex);
504 } else { // move -> load
505 unsigned OutReg = MI->getOperand(0).getReg();
506 bool isDead = MI->getOperand(0).isDead();
507 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
509 MIB.addReg(OutReg, true, false, false, isDead);
510 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
511 ? SPU::STQDr32 : SPU::STQXr32;
512 NewMI = addFrameReference(MIB, FrameIndex);
522 \note This code was kiped from PPC. There may be more branch analysis for
523 CellSPU than what's currently done here.
526 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
527 MachineBasicBlock *&FBB,
528 SmallVectorImpl<MachineOperand> &Cond) const {
529 // If the block has no terminators, it just falls into the block after it.
530 MachineBasicBlock::iterator I = MBB.end();
531 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
534 // Get the last instruction in the block.
535 MachineInstr *LastInst = I;
537 // If there is only one terminator instruction, process it.
538 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
539 if (isUncondBranch(LastInst)) {
540 TBB = LastInst->getOperand(0).getMBB();
542 } else if (isCondBranch(LastInst)) {
543 // Block ends with fall-through condbranch.
544 TBB = LastInst->getOperand(1).getMBB();
545 DEBUG(cerr << "Pushing LastInst: ");
546 DEBUG(LastInst->dump());
547 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
548 Cond.push_back(LastInst->getOperand(0));
551 // Otherwise, don't know what this is.
555 // Get the instruction before it if it's a terminator.
556 MachineInstr *SecondLastInst = I;
558 // If there are three terminators, we don't know what sort of block this is.
559 if (SecondLastInst && I != MBB.begin() &&
560 isUnpredicatedTerminator(--I))
563 // If the block ends with a conditional and unconditional branch, handle it.
564 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
565 TBB = SecondLastInst->getOperand(1).getMBB();
566 DEBUG(cerr << "Pushing SecondLastInst: ");
567 DEBUG(SecondLastInst->dump());
568 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
569 Cond.push_back(SecondLastInst->getOperand(0));
570 FBB = LastInst->getOperand(0).getMBB();
574 // If the block ends with two unconditional branches, handle it. The second
575 // one is not executed, so remove it.
576 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
577 TBB = SecondLastInst->getOperand(0).getMBB();
579 I->eraseFromParent();
583 // Otherwise, can't handle this.
588 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
589 MachineBasicBlock::iterator I = MBB.end();
590 if (I == MBB.begin())
593 if (!isCondBranch(I) && !isUncondBranch(I))
596 // Remove the first branch.
597 DEBUG(cerr << "Removing branch: ");
599 I->eraseFromParent();
601 if (I == MBB.begin())
605 if (!(isCondBranch(I) || isUncondBranch(I)))
608 // Remove the second branch.
609 DEBUG(cerr << "Removing second branch: ");
611 I->eraseFromParent();
616 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
617 MachineBasicBlock *FBB,
618 const SmallVectorImpl<MachineOperand> &Cond) const {
619 // Shouldn't be a fall through.
620 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
621 assert((Cond.size() == 2 || Cond.size() == 0) &&
622 "SPU branch conditions have two components!");
627 // Unconditional branch
628 MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR));
631 DEBUG(cerr << "Inserted one-way uncond branch: ");
632 DEBUG((*MIB).dump());
634 // Conditional branch
635 MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
636 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
638 DEBUG(cerr << "Inserted one-way cond branch: ");
639 DEBUG((*MIB).dump());
643 MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
644 MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR));
646 // Two-way Conditional Branch.
647 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
650 DEBUG(cerr << "Inserted conditional branch: ");
651 DEBUG((*MIB).dump());
652 DEBUG(cerr << "part 2: ");
653 DEBUG((*MIB2).dump());
659 SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
660 return (!MBB.empty() && isUncondBranch(&MBB.back()));
662 //! Reverses a branch's condition, returning false on success.
664 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
666 // Pretty brainless way of inverting the condition, but it works, considering
667 // there are only two conditions...
669 unsigned Opc; //! The incoming opcode
670 unsigned RevCondOpc; //! The reversed condition opcode
672 { SPU::BRNZr32, SPU::BRZr32 },
673 { SPU::BRNZv4i32, SPU::BRZv4i32 },
674 { SPU::BRZr32, SPU::BRNZr32 },
675 { SPU::BRZv4i32, SPU::BRNZv4i32 },
676 { SPU::BRHNZr16, SPU::BRHZr16 },
677 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
678 { SPU::BRHZr16, SPU::BRHNZr16 },
679 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
682 unsigned Opc = unsigned(Cond[0].getImm());
683 // Pretty dull mapping between the two conditions that SPU can generate:
684 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
685 if (revconds[i].Opc == Opc) {
686 Cond[0].setImm(revconds[i].RevCondOpc);