1 //===-- SPUInstrInfo.cpp - Cell SPU Instruction Information ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPUInstrInfo.h"
15 #include "SPUInstrBuilder.h"
16 #include "SPUTargetMachine.h"
17 #include "SPUHazardRecognizers.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRINFO_CTOR
26 #include "SPUGenInstrInfo.inc"
31 //! Predicate for an unconditional branch instruction
32 inline bool isUncondBranch(const MachineInstr *I) {
33 unsigned opc = I->getOpcode();
35 return (opc == SPU::BR
40 //! Predicate for a conditional branch instruction
41 inline bool isCondBranch(const MachineInstr *I) {
42 unsigned opc = I->getOpcode();
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr16
49 || opc == SPU::BRHNZv8i16
50 || opc == SPU::BRHZr16
51 || opc == SPU::BRHZv8i16);
55 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
56 : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
58 RI(*TM.getSubtargetImpl(), *this)
61 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
62 /// this target when scheduling the DAG.
63 ScheduleHazardRecognizer *SPUInstrInfo::CreateTargetHazardRecognizer(
64 const TargetMachine *TM,
65 const ScheduleDAG *DAG) const {
66 const TargetInstrInfo *TII = TM->getInstrInfo();
67 assert(TII && "No InstrInfo?");
68 return new SPUHazardRecognizer(*TII);
72 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
73 int &FrameIndex) const {
74 switch (MI->getOpcode()) {
85 const MachineOperand MOp1 = MI->getOperand(1);
86 const MachineOperand MOp2 = MI->getOperand(2);
87 if (MOp1.isImm() && MOp2.isFI()) {
88 FrameIndex = MOp2.getIndex();
89 return MI->getOperand(0).getReg();
98 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
99 int &FrameIndex) const {
100 switch (MI->getOpcode()) {
112 const MachineOperand MOp1 = MI->getOperand(1);
113 const MachineOperand MOp2 = MI->getOperand(2);
114 if (MOp1.isImm() && MOp2.isFI()) {
115 FrameIndex = MOp2.getIndex();
116 return MI->getOperand(0).getReg();
124 void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I, DebugLoc DL,
126 unsigned DestReg, unsigned SrcReg,
129 // We support cross register class moves for our aliases, such as R3 in any
130 // reg class to any other reg class containing R3. This is required because
131 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
132 // types have no specific meaning.
134 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
135 .addReg(SrcReg, getKillRegState(KillSrc));
139 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
140 MachineBasicBlock::iterator MI,
141 unsigned SrcReg, bool isKill, int FrameIdx,
142 const TargetRegisterClass *RC,
143 const TargetRegisterInfo *TRI) const {
145 bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
146 if (RC == &SPU::GPRCRegClass)
147 opc = isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128;
148 else if (RC == &SPU::R64CRegClass)
149 opc = isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64;
150 else if (RC == &SPU::R64FPRegClass)
151 opc = isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64;
152 else if (RC == &SPU::R32CRegClass)
153 opc = isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32;
154 else if (RC == &SPU::R32FPRegClass)
155 opc = isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32;
156 else if (RC == &SPU::R16CRegClass)
157 opc = isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16;
158 else if (RC == &SPU::R8CRegClass)
159 opc = isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8;
160 else if (RC == &SPU::VECREGRegClass)
161 opc = isValidFrameIdx ? SPU::STQDv16i8 : SPU::STQXv16i8;
163 llvm_unreachable("Unknown regclass!");
166 if (MI != MBB.end()) DL = MI->getDebugLoc();
167 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
168 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
172 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
173 MachineBasicBlock::iterator MI,
174 unsigned DestReg, int FrameIdx,
175 const TargetRegisterClass *RC,
176 const TargetRegisterInfo *TRI) const {
178 bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
179 if (RC == &SPU::GPRCRegClass)
180 opc = isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128;
181 else if (RC == &SPU::R64CRegClass)
182 opc = isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64;
183 else if (RC == &SPU::R64FPRegClass)
184 opc = isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64;
185 else if (RC == &SPU::R32CRegClass)
186 opc = isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32;
187 else if (RC == &SPU::R32FPRegClass)
188 opc = isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32;
189 else if (RC == &SPU::R16CRegClass)
190 opc = isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16;
191 else if (RC == &SPU::R8CRegClass)
192 opc = isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8;
193 else if (RC == &SPU::VECREGRegClass)
194 opc = isValidFrameIdx ? SPU::LQDv16i8 : SPU::LQXv16i8;
196 llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
199 if (MI != MBB.end()) DL = MI->getDebugLoc();
200 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
205 \note This code was kiped from PPC. There may be more branch analysis for
206 CellSPU than what's currently done here.
209 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
210 MachineBasicBlock *&FBB,
211 SmallVectorImpl<MachineOperand> &Cond,
212 bool AllowModify) const {
213 // If the block has no terminators, it just falls into the block after it.
214 MachineBasicBlock::iterator I = MBB.end();
215 if (I == MBB.begin())
218 while (I->isDebugValue()) {
219 if (I == MBB.begin())
223 if (!isUnpredicatedTerminator(I))
226 // Get the last instruction in the block.
227 MachineInstr *LastInst = I;
229 // If there is only one terminator instruction, process it.
230 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
231 if (isUncondBranch(LastInst)) {
232 // Check for jump tables
233 if (!LastInst->getOperand(0).isMBB())
235 TBB = LastInst->getOperand(0).getMBB();
237 } else if (isCondBranch(LastInst)) {
238 // Block ends with fall-through condbranch.
239 TBB = LastInst->getOperand(1).getMBB();
240 DEBUG(errs() << "Pushing LastInst: ");
241 DEBUG(LastInst->dump());
242 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
243 Cond.push_back(LastInst->getOperand(0));
246 // Otherwise, don't know what this is.
250 // Get the instruction before it if it's a terminator.
251 MachineInstr *SecondLastInst = I;
253 // If there are three terminators, we don't know what sort of block this is.
254 if (SecondLastInst && I != MBB.begin() &&
255 isUnpredicatedTerminator(--I))
258 // If the block ends with a conditional and unconditional branch, handle it.
259 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
260 TBB = SecondLastInst->getOperand(1).getMBB();
261 DEBUG(errs() << "Pushing SecondLastInst: ");
262 DEBUG(SecondLastInst->dump());
263 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
264 Cond.push_back(SecondLastInst->getOperand(0));
265 FBB = LastInst->getOperand(0).getMBB();
269 // If the block ends with two unconditional branches, handle it. The second
270 // one is not executed, so remove it.
271 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
272 TBB = SecondLastInst->getOperand(0).getMBB();
275 I->eraseFromParent();
279 // Otherwise, can't handle this.
283 // search MBB for branch hint labels and branch hit ops
284 static void removeHBR( MachineBasicBlock &MBB) {
285 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I){
286 if (I->getOpcode() == SPU::HBRA ||
287 I->getOpcode() == SPU::HBR_LABEL){
296 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
297 MachineBasicBlock::iterator I = MBB.end();
299 if (I == MBB.begin())
302 while (I->isDebugValue()) {
303 if (I == MBB.begin())
307 if (!isCondBranch(I) && !isUncondBranch(I))
310 // Remove the first branch.
311 DEBUG(errs() << "Removing branch: ");
313 I->eraseFromParent();
315 if (I == MBB.begin())
319 if (!(isCondBranch(I) || isUncondBranch(I)))
322 // Remove the second branch.
323 DEBUG(errs() << "Removing second branch: ");
325 I->eraseFromParent();
329 /** Find the optimal position for a hint branch instruction in a basic block.
330 * This should take into account:
331 * -the branch hint delays
332 * -congestion of the memory bus
333 * -dual-issue scheduling (i.e. avoid insertion of nops)
334 * Current implementation is rather simplistic.
336 static MachineBasicBlock::iterator findHBRPosition(MachineBasicBlock &MBB)
338 MachineBasicBlock::iterator J = MBB.end();
339 for( int i=0; i<8; i++) {
340 if( J == MBB.begin() ) return J;
347 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
348 MachineBasicBlock *FBB,
349 const SmallVectorImpl<MachineOperand> &Cond,
351 // Shouldn't be a fall through.
352 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
353 assert((Cond.size() == 2 || Cond.size() == 0) &&
354 "SPU branch conditions have two components!");
356 MachineInstrBuilder MIB;
357 //TODO: make a more accurate algorithm.
358 bool haveHBR = MBB.size()>8;
361 MCSymbol *branchLabel = MBB.getParent()->getContext().CreateTempSymbol();
362 // Add a label just before the branch
364 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
369 // Unconditional branch
370 MIB = BuildMI(&MBB, DL, get(SPU::BR));
373 DEBUG(errs() << "Inserted one-way uncond branch: ");
374 DEBUG((*MIB).dump());
376 // basic blocks have just one branch so it is safe to add the hint a its
378 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
379 MIB.addSym(branchLabel);
383 // Conditional branch
384 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
385 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
388 MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
389 MIB.addSym(branchLabel);
393 DEBUG(errs() << "Inserted one-way cond branch: ");
394 DEBUG((*MIB).dump());
398 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
399 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
401 // Two-way Conditional Branch.
402 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
406 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
407 MIB.addSym(branchLabel);
411 DEBUG(errs() << "Inserted conditional branch: ");
412 DEBUG((*MIB).dump());
413 DEBUG(errs() << "part 2: ");
414 DEBUG((*MIB2).dump());
419 //! Reverses a branch's condition, returning false on success.
421 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
423 // Pretty brainless way of inverting the condition, but it works, considering
424 // there are only two conditions...
426 unsigned Opc; //! The incoming opcode
427 unsigned RevCondOpc; //! The reversed condition opcode
429 { SPU::BRNZr32, SPU::BRZr32 },
430 { SPU::BRNZv4i32, SPU::BRZv4i32 },
431 { SPU::BRZr32, SPU::BRNZr32 },
432 { SPU::BRZv4i32, SPU::BRNZv4i32 },
433 { SPU::BRHNZr16, SPU::BRHZr16 },
434 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
435 { SPU::BRHZr16, SPU::BRHNZr16 },
436 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
439 unsigned Opc = unsigned(Cond[0].getImm());
440 // Pretty dull mapping between the two conditions that SPU can generate:
441 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
442 if (revconds[i].Opc == Opc) {
443 Cond[0].setImm(revconds[i].RevCondOpc);