1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation.
8 // See README.txt for details.
10 //===----------------------------------------------------------------------===//
12 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
14 //===----------------------------------------------------------------------===//
16 #include "SPURegisterNames.h"
17 #include "SPUInstrInfo.h"
18 #include "SPUTargetMachine.h"
19 #include "SPUGenInstrInfo.inc"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
26 : TargetInstrInfo(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
28 RI(*TM.getSubtargetImpl(), *this)
33 /// getPointerRegClass - Return the register class to use to hold pointers.
34 /// This is used for addressing modes.
35 const TargetRegisterClass *
36 SPUInstrInfo::getPointerRegClass() const
38 return &SPU::R32CRegClass;
42 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
44 unsigned& destReg) const {
45 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
46 // cases where we can safely say that what's being done is really a move
47 // (see how PowerPC does this -- it's the model for this code too.)
48 switch (MI.getOpcode()) {
58 // case SPU::ORHI1To2:
67 assert(MI.getNumOperands() == 3 &&
68 MI.getOperand(0).isRegister() &&
69 MI.getOperand(1).isRegister() &&
70 MI.getOperand(2).isImmediate() &&
71 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
72 if (MI.getOperand(2).getImmedValue() == 0) {
73 sourceReg = MI.getOperand(1).getReg();
74 destReg = MI.getOperand(0).getReg();
81 // Special case because there's no third immediate operand to the
82 // instruction (the constant is embedded in the instruction)
83 assert(MI.getOperand(0).isRegister() &&
84 MI.getOperand(1).isRegister() &&
85 "ORIf32/f64: operands not registers");
86 sourceReg = MI.getOperand(1).getReg();
87 destReg = MI.getOperand(0).getReg();
90 // case SPU::ORv16i8_i8:
91 case SPU::ORv8i16_i16:
92 case SPU::ORv4i32_i32:
93 case SPU::ORv2i64_i64:
94 case SPU::ORv4f32_f32:
95 case SPU::ORv2f64_f64:
96 // case SPU::ORi8_v16i8:
97 case SPU::ORi16_v8i16:
98 case SPU::ORi32_v4i32:
99 case SPU::ORi64_v2i64:
100 case SPU::ORf32_v4f32:
101 case SPU::ORf64_v2f64:
108 assert(MI.getNumOperands() == 3 &&
109 MI.getOperand(0).isRegister() &&
110 MI.getOperand(1).isRegister() &&
111 MI.getOperand(2).isRegister() &&
112 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
113 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
114 sourceReg = MI.getOperand(1).getReg();
115 destReg = MI.getOperand(0).getReg();
125 SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
126 switch (MI->getOpcode()) {
142 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
143 MI->getOperand(2).isFrameIndex()) {
144 FrameIndex = MI->getOperand(2).getFrameIndex();
145 return MI->getOperand(0).getReg();
153 SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
154 switch (MI->getOpcode()) {
176 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
177 MI->getOperand(2).isFrameIndex()) {
178 FrameIndex = MI->getOperand(2).getFrameIndex();
179 return MI->getOperand(0).getReg();