1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPUInstrInfo.h"
15 #include "SPUInstrBuilder.h"
16 #include "SPUTargetMachine.h"
17 #include "SPUHazardRecognizers.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/Target/TargetRegistry.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRINFO_CTOR
26 #include "SPUGenInstrInfo.inc"
31 //! Predicate for an unconditional branch instruction
32 inline bool isUncondBranch(const MachineInstr *I) {
33 unsigned opc = I->getOpcode();
35 return (opc == SPU::BR
40 //! Predicate for a conditional branch instruction
41 inline bool isCondBranch(const MachineInstr *I) {
42 unsigned opc = I->getOpcode();
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr16
49 || opc == SPU::BRHNZv8i16
50 || opc == SPU::BRHZr16
51 || opc == SPU::BRHZv8i16);
55 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
56 : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
58 RI(*TM.getSubtargetImpl(), *this)
61 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
62 /// this target when scheduling the DAG.
63 ScheduleHazardRecognizer *SPUInstrInfo::CreateTargetHazardRecognizer(
64 const TargetMachine *TM,
65 const ScheduleDAG *DAG) const {
66 const TargetInstrInfo *TII = TM->getInstrInfo();
67 assert(TII && "No InstrInfo?");
68 return new SPUHazardRecognizer(*TII);
72 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
73 int &FrameIndex) const {
74 switch (MI->getOpcode()) {
85 const MachineOperand MOp1 = MI->getOperand(1);
86 const MachineOperand MOp2 = MI->getOperand(2);
87 if (MOp1.isImm() && MOp2.isFI()) {
88 FrameIndex = MOp2.getIndex();
89 return MI->getOperand(0).getReg();
98 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
99 int &FrameIndex) const {
100 switch (MI->getOpcode()) {
112 const MachineOperand MOp1 = MI->getOperand(1);
113 const MachineOperand MOp2 = MI->getOperand(2);
114 if (MOp1.isImm() && MOp2.isFI()) {
115 FrameIndex = MOp2.getIndex();
116 return MI->getOperand(0).getReg();
124 void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I, DebugLoc DL,
126 unsigned DestReg, unsigned SrcReg,
129 // We support cross register class moves for our aliases, such as R3 in any
130 // reg class to any other reg class containing R3. This is required because
131 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
132 // types have no specific meaning.
134 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
135 .addReg(SrcReg, getKillRegState(KillSrc));
139 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
140 MachineBasicBlock::iterator MI,
141 unsigned SrcReg, bool isKill, int FrameIdx,
142 const TargetRegisterClass *RC,
143 const TargetRegisterInfo *TRI) const
146 bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
147 if (RC == SPU::GPRCRegisterClass) {
148 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
149 } else if (RC == SPU::R64CRegisterClass) {
150 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
151 } else if (RC == SPU::R64FPRegisterClass) {
152 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
153 } else if (RC == SPU::R32CRegisterClass) {
154 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
155 } else if (RC == SPU::R32FPRegisterClass) {
156 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
157 } else if (RC == SPU::R16CRegisterClass) {
158 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
159 } else if (RC == SPU::R8CRegisterClass) {
160 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
161 } else if (RC == SPU::VECREGRegisterClass) {
162 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
164 llvm_unreachable("Unknown regclass!");
168 if (MI != MBB.end()) DL = MI->getDebugLoc();
169 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
170 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
174 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
175 MachineBasicBlock::iterator MI,
176 unsigned DestReg, int FrameIdx,
177 const TargetRegisterClass *RC,
178 const TargetRegisterInfo *TRI) const
181 bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
182 if (RC == SPU::GPRCRegisterClass) {
183 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
184 } else if (RC == SPU::R64CRegisterClass) {
185 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
186 } else if (RC == SPU::R64FPRegisterClass) {
187 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
188 } else if (RC == SPU::R32CRegisterClass) {
189 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
190 } else if (RC == SPU::R32FPRegisterClass) {
191 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
192 } else if (RC == SPU::R16CRegisterClass) {
193 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
194 } else if (RC == SPU::R8CRegisterClass) {
195 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
196 } else if (RC == SPU::VECREGRegisterClass) {
197 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
199 llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
203 if (MI != MBB.end()) DL = MI->getDebugLoc();
204 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
209 \note This code was kiped from PPC. There may be more branch analysis for
210 CellSPU than what's currently done here.
213 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
214 MachineBasicBlock *&FBB,
215 SmallVectorImpl<MachineOperand> &Cond,
216 bool AllowModify) const {
217 // If the block has no terminators, it just falls into the block after it.
218 MachineBasicBlock::iterator I = MBB.end();
219 if (I == MBB.begin())
222 while (I->isDebugValue()) {
223 if (I == MBB.begin())
227 if (!isUnpredicatedTerminator(I))
230 // Get the last instruction in the block.
231 MachineInstr *LastInst = I;
233 // If there is only one terminator instruction, process it.
234 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
235 if (isUncondBranch(LastInst)) {
236 // Check for jump tables
237 if (!LastInst->getOperand(0).isMBB())
239 TBB = LastInst->getOperand(0).getMBB();
241 } else if (isCondBranch(LastInst)) {
242 // Block ends with fall-through condbranch.
243 TBB = LastInst->getOperand(1).getMBB();
244 DEBUG(errs() << "Pushing LastInst: ");
245 DEBUG(LastInst->dump());
246 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
247 Cond.push_back(LastInst->getOperand(0));
250 // Otherwise, don't know what this is.
254 // Get the instruction before it if it's a terminator.
255 MachineInstr *SecondLastInst = I;
257 // If there are three terminators, we don't know what sort of block this is.
258 if (SecondLastInst && I != MBB.begin() &&
259 isUnpredicatedTerminator(--I))
262 // If the block ends with a conditional and unconditional branch, handle it.
263 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
264 TBB = SecondLastInst->getOperand(1).getMBB();
265 DEBUG(errs() << "Pushing SecondLastInst: ");
266 DEBUG(SecondLastInst->dump());
267 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
268 Cond.push_back(SecondLastInst->getOperand(0));
269 FBB = LastInst->getOperand(0).getMBB();
273 // If the block ends with two unconditional branches, handle it. The second
274 // one is not executed, so remove it.
275 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
276 TBB = SecondLastInst->getOperand(0).getMBB();
279 I->eraseFromParent();
283 // Otherwise, can't handle this.
287 // search MBB for branch hint labels and branch hit ops
288 static void removeHBR( MachineBasicBlock &MBB) {
289 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I){
290 if (I->getOpcode() == SPU::HBRA ||
291 I->getOpcode() == SPU::HBR_LABEL){
298 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
299 MachineBasicBlock::iterator I = MBB.end();
301 if (I == MBB.begin())
304 while (I->isDebugValue()) {
305 if (I == MBB.begin())
309 if (!isCondBranch(I) && !isUncondBranch(I))
312 // Remove the first branch.
313 DEBUG(errs() << "Removing branch: ");
315 I->eraseFromParent();
317 if (I == MBB.begin())
321 if (!(isCondBranch(I) || isUncondBranch(I)))
324 // Remove the second branch.
325 DEBUG(errs() << "Removing second branch: ");
327 I->eraseFromParent();
331 /** Find the optimal position for a hint branch instruction in a basic block.
332 * This should take into account:
333 * -the branch hint delays
334 * -congestion of the memory bus
335 * -dual-issue scheduling (i.e. avoid insertion of nops)
336 * Current implementation is rather simplistic.
338 static MachineBasicBlock::iterator findHBRPosition(MachineBasicBlock &MBB)
340 MachineBasicBlock::iterator J = MBB.end();
341 for( int i=0; i<8; i++) {
342 if( J == MBB.begin() ) return J;
349 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
350 MachineBasicBlock *FBB,
351 const SmallVectorImpl<MachineOperand> &Cond,
353 // Shouldn't be a fall through.
354 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
355 assert((Cond.size() == 2 || Cond.size() == 0) &&
356 "SPU branch conditions have two components!");
358 MachineInstrBuilder MIB;
359 //TODO: make a more accurate algorithm.
360 bool haveHBR = MBB.size()>8;
363 MCSymbol *branchLabel = MBB.getParent()->getContext().CreateTempSymbol();
364 // Add a label just before the branch
366 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
371 // Unconditional branch
372 MIB = BuildMI(&MBB, DL, get(SPU::BR));
375 DEBUG(errs() << "Inserted one-way uncond branch: ");
376 DEBUG((*MIB).dump());
378 // basic blocks have just one branch so it is safe to add the hint a its
380 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
381 MIB.addSym(branchLabel);
385 // Conditional branch
386 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
387 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
390 MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
391 MIB.addSym(branchLabel);
395 DEBUG(errs() << "Inserted one-way cond branch: ");
396 DEBUG((*MIB).dump());
400 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
401 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
403 // Two-way Conditional Branch.
404 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
408 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
409 MIB.addSym(branchLabel);
413 DEBUG(errs() << "Inserted conditional branch: ");
414 DEBUG((*MIB).dump());
415 DEBUG(errs() << "part 2: ");
416 DEBUG((*MIB2).dump());
421 //! Reverses a branch's condition, returning false on success.
423 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
425 // Pretty brainless way of inverting the condition, but it works, considering
426 // there are only two conditions...
428 unsigned Opc; //! The incoming opcode
429 unsigned RevCondOpc; //! The reversed condition opcode
431 { SPU::BRNZr32, SPU::BRZr32 },
432 { SPU::BRNZv4i32, SPU::BRZv4i32 },
433 { SPU::BRZr32, SPU::BRNZr32 },
434 { SPU::BRZv4i32, SPU::BRNZv4i32 },
435 { SPU::BRHNZr16, SPU::BRHZr16 },
436 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
437 { SPU::BRHZr16, SPU::BRHNZr16 },
438 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
441 unsigned Opc = unsigned(Cond[0].getImm());
442 // Pretty dull mapping between the two conditions that SPU can generate:
443 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
444 if (revconds[i].Opc == Opc) {
445 Cond[0].setImm(revconds[i].RevCondOpc);