1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
25 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
27 RI(*TM.getSubtargetImpl(), *this)
32 /// getPointerRegClass - Return the register class to use to hold pointers.
33 /// This is used for addressing modes.
34 const TargetRegisterClass *
35 SPUInstrInfo::getPointerRegClass() const
37 return &SPU::R32CRegClass;
41 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
43 unsigned& destReg) const {
44 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
45 // cases where we can safely say that what's being done is really a move
46 // (see how PowerPC does this -- it's the model for this code too.)
47 switch (MI.getOpcode()) {
63 assert(MI.getNumOperands() == 3 &&
64 MI.getOperand(0).isRegister() &&
65 MI.getOperand(1).isRegister() &&
66 MI.getOperand(2).isImmediate() &&
67 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
68 if (MI.getOperand(2).getImm() == 0) {
69 sourceReg = MI.getOperand(1).getReg();
70 destReg = MI.getOperand(0).getReg();
75 assert(MI.getNumOperands() == 3 &&
76 "wrong number of operands to AIr32");
77 if (MI.getOperand(0).isRegister() &&
78 (MI.getOperand(1).isRegister() ||
79 MI.getOperand(1).isFrameIndex()) &&
80 (MI.getOperand(2).isImmediate() &&
81 MI.getOperand(2).getImm() == 0)) {
82 sourceReg = MI.getOperand(1).getReg();
83 destReg = MI.getOperand(0).getReg();
88 case SPU::ORv8i16_i16:
89 case SPU::ORv4i32_i32:
90 case SPU::ORv2i64_i64:
91 case SPU::ORv4f32_f32:
92 case SPU::ORv2f64_f64:
94 case SPU::ORi16_v8i16:
95 case SPU::ORi32_v4i32:
96 case SPU::ORi64_v2i64:
97 case SPU::ORf32_v4f32:
98 case SPU::ORf64_v2f64:
107 assert(MI.getNumOperands() == 3 &&
108 MI.getOperand(0).isRegister() &&
109 MI.getOperand(1).isRegister() &&
110 MI.getOperand(2).isRegister() &&
111 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
112 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
113 sourceReg = MI.getOperand(1).getReg();
114 destReg = MI.getOperand(0).getReg();
124 SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
125 switch (MI->getOpcode()) {
141 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
142 MI->getOperand(2).isFrameIndex()) {
143 FrameIndex = MI->getOperand(2).getIndex();
144 return MI->getOperand(0).getReg();
152 SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
153 switch (MI->getOpcode()) {
175 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
176 MI->getOperand(2).isFrameIndex()) {
177 FrameIndex = MI->getOperand(2).getIndex();
178 return MI->getOperand(0).getReg();
185 void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator MI,
187 unsigned DestReg, unsigned SrcReg,
188 const TargetRegisterClass *DestRC,
189 const TargetRegisterClass *SrcRC) const
191 if (DestRC != SrcRC) {
192 cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
196 if (DestRC == SPU::R8CRegisterClass) {
197 BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
198 } else if (DestRC == SPU::R16CRegisterClass) {
199 BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
200 } else if (DestRC == SPU::R32CRegisterClass) {
201 BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
202 } else if (DestRC == SPU::R32FPRegisterClass) {
203 BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
205 } else if (DestRC == SPU::R64CRegisterClass) {
206 BuildMI(MBB, MI, get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
207 } else if (DestRC == SPU::R64FPRegisterClass) {
208 BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
210 } else if (DestRC == SPU::GPRCRegisterClass) {
211 BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
213 } else if (DestRC == SPU::VECREGRegisterClass) {
214 BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
217 std::cerr << "Attempt to copy unknown/unsupported register class!\n";
223 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
224 MachineBasicBlock::iterator MI,
225 unsigned SrcReg, bool isKill, int FrameIdx,
226 const TargetRegisterClass *RC) const
229 if (RC == SPU::GPRCRegisterClass) {
230 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
233 } else if (RC == SPU::R64CRegisterClass) {
234 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
237 } else if (RC == SPU::R64FPRegisterClass) {
238 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
241 } else if (RC == SPU::R32CRegisterClass) {
242 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
245 } else if (RC == SPU::R32FPRegisterClass) {
246 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
249 } else if (RC == SPU::R16CRegisterClass) {
250 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
254 assert(0 && "Unknown regclass!");
258 addFrameReference(BuildMI(MBB, MI, get(opc))
259 .addReg(SrcReg, false, false, isKill), FrameIdx);
262 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
264 SmallVectorImpl<MachineOperand> &Addr,
265 const TargetRegisterClass *RC,
266 SmallVectorImpl<MachineInstr*> &NewMIs) const {
267 cerr << "storeRegToAddr() invoked!\n";
270 if (Addr[0].isFrameIndex()) {
271 /* do what storeRegToStackSlot does here */
274 if (RC == SPU::GPRCRegisterClass) {
275 /* Opc = PPC::STW; */
276 } else if (RC == SPU::R16CRegisterClass) {
277 /* Opc = PPC::STD; */
278 } else if (RC == SPU::R32CRegisterClass) {
279 /* Opc = PPC::STFD; */
280 } else if (RC == SPU::R32FPRegisterClass) {
281 /* Opc = PPC::STFD; */
282 } else if (RC == SPU::R64FPRegisterClass) {
283 /* Opc = PPC::STFS; */
284 } else if (RC == SPU::VECREGRegisterClass) {
285 /* Opc = PPC::STVX; */
287 assert(0 && "Unknown regclass!");
290 MachineInstrBuilder MIB = BuildMI(get(Opc))
291 .addReg(SrcReg, false, false, isKill);
292 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
293 MachineOperand &MO = Addr[i];
295 MIB.addReg(MO.getReg());
296 else if (MO.isImmediate())
297 MIB.addImm(MO.getImm());
299 MIB.addFrameIndex(MO.getIndex());
301 NewMIs.push_back(MIB);
306 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
307 MachineBasicBlock::iterator MI,
308 unsigned DestReg, int FrameIdx,
309 const TargetRegisterClass *RC) const
312 if (RC == SPU::GPRCRegisterClass) {
313 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
316 } else if (RC == SPU::R64CRegisterClass) {
317 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
320 } else if (RC == SPU::R64FPRegisterClass) {
321 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
324 } else if (RC == SPU::R32CRegisterClass) {
325 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
328 } else if (RC == SPU::R32FPRegisterClass) {
329 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
332 } else if (RC == SPU::R16CRegisterClass) {
333 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
337 assert(0 && "Unknown regclass in loadRegFromStackSlot!");
341 addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
345 \note We are really pessimistic here about what kind of a load we're doing.
347 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
348 SmallVectorImpl<MachineOperand> &Addr,
349 const TargetRegisterClass *RC,
350 SmallVectorImpl<MachineInstr*> &NewMIs)
352 cerr << "loadRegToAddr() invoked!\n";
355 if (Addr[0].isFrameIndex()) {
356 /* do what loadRegFromStackSlot does here... */
359 if (RC == SPU::R8CRegisterClass) {
360 /* do brilliance here */
361 } else if (RC == SPU::R16CRegisterClass) {
362 /* Opc = PPC::LWZ; */
363 } else if (RC == SPU::R32CRegisterClass) {
365 } else if (RC == SPU::R32FPRegisterClass) {
366 /* Opc = PPC::LFD; */
367 } else if (RC == SPU::R64FPRegisterClass) {
368 /* Opc = PPC::LFS; */
369 } else if (RC == SPU::VECREGRegisterClass) {
370 /* Opc = PPC::LVX; */
371 } else if (RC == SPU::GPRCRegisterClass) {
372 /* Opc = something else! */
374 assert(0 && "Unknown regclass!");
377 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
378 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
379 MachineOperand &MO = Addr[i];
381 MIB.addReg(MO.getReg());
382 else if (MO.isImmediate())
383 MIB.addImm(MO.getImm());
385 MIB.addFrameIndex(MO.getIndex());
387 NewMIs.push_back(MIB);
391 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
392 /// copy instructions, turning them into load/store instructions.
394 SPUInstrInfo::foldMemoryOperand(MachineInstr *MI,
395 SmallVectorImpl<unsigned> &Ops,
396 int FrameIndex) const
398 #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
399 if (Ops.size() != 1) return NULL;
401 unsigned OpNum = Ops[0];
402 unsigned Opc = MI->getOpcode();
403 MachineInstr *NewMI = 0;
405 if ((Opc == SPU::ORr32
406 || Opc == SPU::ORv4i32)
407 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
408 if (OpNum == 0) { // move -> store
409 unsigned InReg = MI->getOperand(1).getReg();
410 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
411 NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
414 } else { // move -> load
415 unsigned OutReg = MI->getOperand(0).getReg();
416 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
417 NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
422 NewMI->copyKillDeadInfo(MI);