1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/Streams.h"
21 #include "llvm/Support/Debug.h"
26 //! Predicate for an unconditional branch instruction
27 inline bool isUncondBranch(const MachineInstr *I) {
28 unsigned opc = I->getOpcode();
30 return (opc == SPU::BR
35 //! Predicate for a conditional branch instruction
36 inline bool isCondBranch(const MachineInstr *I) {
37 unsigned opc = I->getOpcode();
39 return (opc == SPU::BRNZr32
40 || opc == SPU::BRNZv4i32
42 || opc == SPU::BRZv4i32
43 || opc == SPU::BRHNZr16
44 || opc == SPU::BRHNZv8i16
45 || opc == SPU::BRHZr16
46 || opc == SPU::BRHZv8i16);
50 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
51 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
53 RI(*TM.getSubtargetImpl(), *this)
56 /// getPointerRegClass - Return the register class to use to hold pointers.
57 /// This is used for addressing modes.
58 const TargetRegisterClass *
59 SPUInstrInfo::getPointerRegClass() const
61 return &SPU::R32CRegClass;
65 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
67 unsigned& destReg) const {
68 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
69 // cases where we can safely say that what's being done is really a move
70 // (see how PowerPC does this -- it's the model for this code too.)
71 switch (MI.getOpcode()) {
86 assert(MI.getNumOperands() == 3 &&
87 MI.getOperand(0).isReg() &&
88 MI.getOperand(1).isReg() &&
89 MI.getOperand(2).isImm() &&
90 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
91 if (MI.getOperand(2).getImm() == 0) {
92 sourceReg = MI.getOperand(1).getReg();
93 destReg = MI.getOperand(0).getReg();
98 assert(MI.getNumOperands() == 3 &&
99 "wrong number of operands to AIr32");
100 if (MI.getOperand(0).isReg() &&
101 MI.getOperand(1).isReg() &&
102 (MI.getOperand(2).isImm() &&
103 MI.getOperand(2).getImm() == 0)) {
104 sourceReg = MI.getOperand(1).getReg();
105 destReg = MI.getOperand(0).getReg();
122 case SPU::ORv16i8_i8:
123 case SPU::ORv8i16_i16:
124 case SPU::ORv4i32_i32:
125 case SPU::ORv2i64_i64:
126 case SPU::ORv4f32_f32:
127 case SPU::ORv2f64_f64:
128 case SPU::ORi8_v16i8:
129 case SPU::ORi16_v8i16:
130 case SPU::ORi32_v4i32:
131 case SPU::ORi64_v2i64:
132 case SPU::ORf32_v4f32:
133 case SPU::ORf64_v2f64:
134 case SPU::ORi128_r64:
135 case SPU::ORi128_f64:
136 case SPU::ORi128_r32:
137 case SPU::ORi128_f32:
138 case SPU::ORi128_r16:
140 case SPU::ORi128_vec:
141 case SPU::ORr64_i128:
142 case SPU::ORf64_i128:
143 case SPU::ORr32_i128:
144 case SPU::ORf32_i128:
145 case SPU::ORr16_i128:
147 case SPU::ORvec_i128:
159 assert(MI.getNumOperands() == 2 &&
160 MI.getOperand(0).isReg() &&
161 MI.getOperand(1).isReg() &&
162 "invalid SPU OR<type>_<vec> or LR instruction!");
163 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
164 sourceReg = MI.getOperand(0).getReg();
165 destReg = MI.getOperand(0).getReg();
180 assert(MI.getNumOperands() == 3 &&
181 MI.getOperand(0).isReg() &&
182 MI.getOperand(1).isReg() &&
183 MI.getOperand(2).isReg() &&
184 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
185 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
186 sourceReg = MI.getOperand(1).getReg();
187 destReg = MI.getOperand(0).getReg();
197 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
198 int &FrameIndex) const {
199 switch (MI->getOpcode()) {
210 const MachineOperand MOp1 = MI->getOperand(1);
211 const MachineOperand MOp2 = MI->getOperand(2);
212 if (MOp1.isImm() && MOp2.isFI()) {
213 FrameIndex = MOp2.getIndex();
214 return MI->getOperand(0).getReg();
223 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
224 int &FrameIndex) const {
225 switch (MI->getOpcode()) {
237 const MachineOperand MOp1 = MI->getOperand(1);
238 const MachineOperand MOp2 = MI->getOperand(2);
239 if (MOp1.isImm() && MOp2.isFI()) {
240 FrameIndex = MOp2.getIndex();
241 return MI->getOperand(0).getReg();
249 bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
250 MachineBasicBlock::iterator MI,
251 unsigned DestReg, unsigned SrcReg,
252 const TargetRegisterClass *DestRC,
253 const TargetRegisterClass *SrcRC) const
255 // We support cross register class moves for our aliases, such as R3 in any
256 // reg class to any other reg class containing R3. This is required because
257 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
258 // types have no specific meaning.
260 if (DestRC == SPU::R8CRegisterClass) {
261 BuildMI(MBB, MI, get(SPU::LRr8), DestReg).addReg(SrcReg);
262 } else if (DestRC == SPU::R16CRegisterClass) {
263 BuildMI(MBB, MI, get(SPU::LRr16), DestReg).addReg(SrcReg);
264 } else if (DestRC == SPU::R32CRegisterClass) {
265 BuildMI(MBB, MI, get(SPU::LRr32), DestReg).addReg(SrcReg);
266 } else if (DestRC == SPU::R32FPRegisterClass) {
267 BuildMI(MBB, MI, get(SPU::LRf32), DestReg).addReg(SrcReg);
268 } else if (DestRC == SPU::R64CRegisterClass) {
269 BuildMI(MBB, MI, get(SPU::LRr64), DestReg).addReg(SrcReg);
270 } else if (DestRC == SPU::R64FPRegisterClass) {
271 BuildMI(MBB, MI, get(SPU::LRf64), DestReg).addReg(SrcReg);
272 } else if (DestRC == SPU::GPRCRegisterClass) {
273 BuildMI(MBB, MI, get(SPU::LRr128), DestReg).addReg(SrcReg);
274 } else if (DestRC == SPU::VECREGRegisterClass) {
275 BuildMI(MBB, MI, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
277 // Attempt to copy unknown/unsupported register class!
285 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
286 MachineBasicBlock::iterator MI,
287 unsigned SrcReg, bool isKill, int FrameIdx,
288 const TargetRegisterClass *RC) const
291 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
292 if (RC == SPU::GPRCRegisterClass) {
293 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
294 } else if (RC == SPU::R64CRegisterClass) {
295 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
296 } else if (RC == SPU::R64FPRegisterClass) {
297 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
298 } else if (RC == SPU::R32CRegisterClass) {
299 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
300 } else if (RC == SPU::R32FPRegisterClass) {
301 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
302 } else if (RC == SPU::R16CRegisterClass) {
303 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
304 } else if (RC == SPU::R8CRegisterClass) {
305 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
306 } else if (RC == SPU::VECREGRegisterClass) {
307 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
309 assert(0 && "Unknown regclass!");
313 addFrameReference(BuildMI(MBB, MI, get(opc))
314 .addReg(SrcReg, false, false, isKill), FrameIdx);
317 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
319 SmallVectorImpl<MachineOperand> &Addr,
320 const TargetRegisterClass *RC,
321 SmallVectorImpl<MachineInstr*> &NewMIs) const {
322 cerr << "storeRegToAddr() invoked!\n";
325 if (Addr[0].isFI()) {
326 /* do what storeRegToStackSlot does here */
329 if (RC == SPU::GPRCRegisterClass) {
330 /* Opc = PPC::STW; */
331 } else if (RC == SPU::R16CRegisterClass) {
332 /* Opc = PPC::STD; */
333 } else if (RC == SPU::R32CRegisterClass) {
334 /* Opc = PPC::STFD; */
335 } else if (RC == SPU::R32FPRegisterClass) {
336 /* Opc = PPC::STFD; */
337 } else if (RC == SPU::R64FPRegisterClass) {
338 /* Opc = PPC::STFS; */
339 } else if (RC == SPU::VECREGRegisterClass) {
340 /* Opc = PPC::STVX; */
342 assert(0 && "Unknown regclass!");
345 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
346 .addReg(SrcReg, false, false, isKill);
347 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
348 MachineOperand &MO = Addr[i];
350 MIB.addReg(MO.getReg());
352 MIB.addImm(MO.getImm());
354 MIB.addFrameIndex(MO.getIndex());
356 NewMIs.push_back(MIB);
361 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
362 MachineBasicBlock::iterator MI,
363 unsigned DestReg, int FrameIdx,
364 const TargetRegisterClass *RC) const
367 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
368 if (RC == SPU::GPRCRegisterClass) {
369 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
370 } else if (RC == SPU::R64CRegisterClass) {
371 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
372 } else if (RC == SPU::R64FPRegisterClass) {
373 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
374 } else if (RC == SPU::R32CRegisterClass) {
375 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
376 } else if (RC == SPU::R32FPRegisterClass) {
377 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
378 } else if (RC == SPU::R16CRegisterClass) {
379 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
380 } else if (RC == SPU::R8CRegisterClass) {
381 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
382 } else if (RC == SPU::VECREGRegisterClass) {
383 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
385 assert(0 && "Unknown regclass in loadRegFromStackSlot!");
389 addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
393 \note We are really pessimistic here about what kind of a load we're doing.
395 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
396 SmallVectorImpl<MachineOperand> &Addr,
397 const TargetRegisterClass *RC,
398 SmallVectorImpl<MachineInstr*> &NewMIs)
400 cerr << "loadRegToAddr() invoked!\n";
403 if (Addr[0].isFI()) {
404 /* do what loadRegFromStackSlot does here... */
407 if (RC == SPU::R8CRegisterClass) {
408 /* do brilliance here */
409 } else if (RC == SPU::R16CRegisterClass) {
410 /* Opc = PPC::LWZ; */
411 } else if (RC == SPU::R32CRegisterClass) {
413 } else if (RC == SPU::R32FPRegisterClass) {
414 /* Opc = PPC::LFD; */
415 } else if (RC == SPU::R64FPRegisterClass) {
416 /* Opc = PPC::LFS; */
417 } else if (RC == SPU::VECREGRegisterClass) {
418 /* Opc = PPC::LVX; */
419 } else if (RC == SPU::GPRCRegisterClass) {
420 /* Opc = something else! */
422 assert(0 && "Unknown regclass!");
425 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
426 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
427 MachineOperand &MO = Addr[i];
429 MIB.addReg(MO.getReg());
431 MIB.addImm(MO.getImm());
433 MIB.addFrameIndex(MO.getIndex());
435 NewMIs.push_back(MIB);
439 //! Return true if the specified load or store can be folded
441 SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
442 const SmallVectorImpl<unsigned> &Ops) const {
443 if (Ops.size() != 1) return false;
445 // Make sure this is a reg-reg copy.
446 unsigned Opc = MI->getOpcode();
459 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
467 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
468 /// copy instructions, turning them into load/store instructions.
470 SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
472 const SmallVectorImpl<unsigned> &Ops,
473 int FrameIndex) const
475 if (Ops.size() != 1) return 0;
477 unsigned OpNum = Ops[0];
478 unsigned Opc = MI->getOpcode();
479 MachineInstr *NewMI = 0;
492 if (OpNum == 0) { // move -> store
493 unsigned InReg = MI->getOperand(1).getReg();
494 bool isKill = MI->getOperand(1).isKill();
495 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
496 MachineInstrBuilder MIB = BuildMI(MF, get(SPU::STQDr32));
498 MIB.addReg(InReg, false, false, isKill);
499 NewMI = addFrameReference(MIB, FrameIndex);
501 } else { // move -> load
502 unsigned OutReg = MI->getOperand(0).getReg();
503 bool isDead = MI->getOperand(0).isDead();
504 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
506 MIB.addReg(OutReg, true, false, false, isDead);
507 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
508 ? SPU::STQDr32 : SPU::STQXr32;
509 NewMI = addFrameReference(MIB, FrameIndex);
519 \note This code was kiped from PPC. There may be more branch analysis for
520 CellSPU than what's currently done here.
523 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
524 MachineBasicBlock *&FBB,
525 SmallVectorImpl<MachineOperand> &Cond) const {
526 // If the block has no terminators, it just falls into the block after it.
527 MachineBasicBlock::iterator I = MBB.end();
528 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
531 // Get the last instruction in the block.
532 MachineInstr *LastInst = I;
534 // If there is only one terminator instruction, process it.
535 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
536 if (isUncondBranch(LastInst)) {
537 TBB = LastInst->getOperand(0).getMBB();
539 } else if (isCondBranch(LastInst)) {
540 // Block ends with fall-through condbranch.
541 TBB = LastInst->getOperand(1).getMBB();
542 DEBUG(cerr << "Pushing LastInst: ");
543 DEBUG(LastInst->dump());
544 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
545 Cond.push_back(LastInst->getOperand(0));
548 // Otherwise, don't know what this is.
552 // Get the instruction before it if it's a terminator.
553 MachineInstr *SecondLastInst = I;
555 // If there are three terminators, we don't know what sort of block this is.
556 if (SecondLastInst && I != MBB.begin() &&
557 isUnpredicatedTerminator(--I))
560 // If the block ends with a conditional and unconditional branch, handle it.
561 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
562 TBB = SecondLastInst->getOperand(1).getMBB();
563 DEBUG(cerr << "Pushing SecondLastInst: ");
564 DEBUG(SecondLastInst->dump());
565 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
566 Cond.push_back(SecondLastInst->getOperand(0));
567 FBB = LastInst->getOperand(0).getMBB();
571 // If the block ends with two unconditional branches, handle it. The second
572 // one is not executed, so remove it.
573 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
574 TBB = SecondLastInst->getOperand(0).getMBB();
576 I->eraseFromParent();
580 // Otherwise, can't handle this.
585 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
586 MachineBasicBlock::iterator I = MBB.end();
587 if (I == MBB.begin())
590 if (!isCondBranch(I) && !isUncondBranch(I))
593 // Remove the first branch.
594 DEBUG(cerr << "Removing branch: ");
596 I->eraseFromParent();
598 if (I == MBB.begin())
602 if (!(isCondBranch(I) || isUncondBranch(I)))
605 // Remove the second branch.
606 DEBUG(cerr << "Removing second branch: ");
608 I->eraseFromParent();
613 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
614 MachineBasicBlock *FBB,
615 const SmallVectorImpl<MachineOperand> &Cond) const {
616 // Shouldn't be a fall through.
617 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
618 assert((Cond.size() == 2 || Cond.size() == 0) &&
619 "SPU branch conditions have two components!");
624 // Unconditional branch
625 MachineInstrBuilder MIB = BuildMI(&MBB, get(SPU::BR));
628 DEBUG(cerr << "Inserted one-way uncond branch: ");
629 DEBUG((*MIB).dump());
631 // Conditional branch
632 MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
633 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
635 DEBUG(cerr << "Inserted one-way cond branch: ");
636 DEBUG((*MIB).dump());
640 MachineInstrBuilder MIB = BuildMI(&MBB, get(Cond[0].getImm()));
641 MachineInstrBuilder MIB2 = BuildMI(&MBB, get(SPU::BR));
643 // Two-way Conditional Branch.
644 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
647 DEBUG(cerr << "Inserted conditional branch: ");
648 DEBUG((*MIB).dump());
649 DEBUG(cerr << "part 2: ");
650 DEBUG((*MIB2).dump());
656 SPUInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
657 return (!MBB.empty() && isUncondBranch(&MBB.back()));
659 //! Reverses a branch's condition, returning false on success.
661 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
663 // Pretty brainless way of inverting the condition, but it works, considering
664 // there are only two conditions...
666 unsigned Opc; //! The incoming opcode
667 unsigned RevCondOpc; //! The reversed condition opcode
669 { SPU::BRNZr32, SPU::BRZr32 },
670 { SPU::BRNZv4i32, SPU::BRZv4i32 },
671 { SPU::BRZr32, SPU::BRNZr32 },
672 { SPU::BRZv4i32, SPU::BRNZv4i32 },
673 { SPU::BRHNZr16, SPU::BRHZr16 },
674 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
675 { SPU::BRHZr16, SPU::BRHNZr16 },
676 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
679 unsigned Opc = unsigned(Cond[0].getImm());
680 // Pretty dull mapping between the two conditions that SPU can generate:
681 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
682 if (revconds[i].Opc == Opc) {
683 Cond[0].setImm(revconds[i].RevCondOpc);