1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
27 //! Predicate for an unconditional branch instruction
28 inline bool isUncondBranch(const MachineInstr *I) {
29 unsigned opc = I->getOpcode();
31 return (opc == SPU::BR
36 //! Predicate for a conditional branch instruction
37 inline bool isCondBranch(const MachineInstr *I) {
38 unsigned opc = I->getOpcode();
40 return (opc == SPU::BRNZr32
41 || opc == SPU::BRNZv4i32
43 || opc == SPU::BRZv4i32
44 || opc == SPU::BRHNZr16
45 || opc == SPU::BRHNZv8i16
46 || opc == SPU::BRHZr16
47 || opc == SPU::BRHZv8i16);
51 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
52 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
54 RI(*TM.getSubtargetImpl(), *this)
58 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
61 unsigned& SrcSR, unsigned& DstSR) const {
62 SrcSR = DstSR = 0; // No sub-registers.
64 switch (MI.getOpcode()) {
79 assert(MI.getNumOperands() == 3 &&
80 MI.getOperand(0).isReg() &&
81 MI.getOperand(1).isReg() &&
82 MI.getOperand(2).isImm() &&
83 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
84 if (MI.getOperand(2).getImm() == 0) {
85 sourceReg = MI.getOperand(1).getReg();
86 destReg = MI.getOperand(0).getReg();
91 assert(MI.getNumOperands() == 3 &&
92 "wrong number of operands to AIr32");
93 if (MI.getOperand(0).isReg() &&
94 MI.getOperand(1).isReg() &&
95 (MI.getOperand(2).isImm() &&
96 MI.getOperand(2).getImm() == 0)) {
97 sourceReg = MI.getOperand(1).getReg();
98 destReg = MI.getOperand(0).getReg();
115 case SPU::ORv16i8_i8:
116 case SPU::ORv8i16_i16:
117 case SPU::ORv4i32_i32:
118 case SPU::ORv2i64_i64:
119 case SPU::ORv4f32_f32:
120 case SPU::ORv2f64_f64:
121 case SPU::ORi8_v16i8:
122 case SPU::ORi16_v8i16:
123 case SPU::ORi32_v4i32:
124 case SPU::ORi64_v2i64:
125 case SPU::ORf32_v4f32:
126 case SPU::ORf64_v2f64:
128 case SPU::ORi128_r64:
129 case SPU::ORi128_f64:
130 case SPU::ORi128_r32:
131 case SPU::ORi128_f32:
132 case SPU::ORi128_r16:
135 case SPU::ORi128_vec:
137 case SPU::ORr64_i128:
138 case SPU::ORf64_i128:
139 case SPU::ORr32_i128:
140 case SPU::ORf32_i128:
141 case SPU::ORr16_i128:
144 case SPU::ORvec_i128:
162 case SPU::ORr64_f64: {
163 assert(MI.getNumOperands() == 2 &&
164 MI.getOperand(0).isReg() &&
165 MI.getOperand(1).isReg() &&
166 "invalid SPU OR<type>_<vec> or LR instruction!");
167 sourceReg = MI.getOperand(1).getReg();
168 destReg = MI.getOperand(0).getReg();
183 assert(MI.getNumOperands() == 3 &&
184 MI.getOperand(0).isReg() &&
185 MI.getOperand(1).isReg() &&
186 MI.getOperand(2).isReg() &&
187 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
188 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
189 sourceReg = MI.getOperand(1).getReg();
190 destReg = MI.getOperand(0).getReg();
200 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
201 int &FrameIndex) const {
202 switch (MI->getOpcode()) {
213 const MachineOperand MOp1 = MI->getOperand(1);
214 const MachineOperand MOp2 = MI->getOperand(2);
215 if (MOp1.isImm() && MOp2.isFI()) {
216 FrameIndex = MOp2.getIndex();
217 return MI->getOperand(0).getReg();
226 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
227 int &FrameIndex) const {
228 switch (MI->getOpcode()) {
240 const MachineOperand MOp1 = MI->getOperand(1);
241 const MachineOperand MOp2 = MI->getOperand(2);
242 if (MOp1.isImm() && MOp2.isFI()) {
243 FrameIndex = MOp2.getIndex();
244 return MI->getOperand(0).getReg();
252 void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator I, DebugLoc DL,
254 unsigned DestReg, unsigned SrcReg,
257 // We support cross register class moves for our aliases, such as R3 in any
258 // reg class to any other reg class containing R3. This is required because
259 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
260 // types have no specific meaning.
262 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
263 .addReg(SrcReg, getKillRegState(KillSrc));
267 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
268 MachineBasicBlock::iterator MI,
269 unsigned SrcReg, bool isKill, int FrameIdx,
270 const TargetRegisterClass *RC,
271 const TargetRegisterInfo *TRI) const
274 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
275 if (RC == SPU::GPRCRegisterClass) {
276 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
277 } else if (RC == SPU::R64CRegisterClass) {
278 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
279 } else if (RC == SPU::R64FPRegisterClass) {
280 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
281 } else if (RC == SPU::R32CRegisterClass) {
282 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
283 } else if (RC == SPU::R32FPRegisterClass) {
284 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
285 } else if (RC == SPU::R16CRegisterClass) {
286 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
287 } else if (RC == SPU::R8CRegisterClass) {
288 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
289 } else if (RC == SPU::VECREGRegisterClass) {
290 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
292 llvm_unreachable("Unknown regclass!");
296 if (MI != MBB.end()) DL = MI->getDebugLoc();
297 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
298 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
302 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
303 MachineBasicBlock::iterator MI,
304 unsigned DestReg, int FrameIdx,
305 const TargetRegisterClass *RC,
306 const TargetRegisterInfo *TRI) const
309 bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset());
310 if (RC == SPU::GPRCRegisterClass) {
311 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
312 } else if (RC == SPU::R64CRegisterClass) {
313 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
314 } else if (RC == SPU::R64FPRegisterClass) {
315 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
316 } else if (RC == SPU::R32CRegisterClass) {
317 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
318 } else if (RC == SPU::R32FPRegisterClass) {
319 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
320 } else if (RC == SPU::R16CRegisterClass) {
321 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
322 } else if (RC == SPU::R8CRegisterClass) {
323 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
324 } else if (RC == SPU::VECREGRegisterClass) {
325 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
327 llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
331 if (MI != MBB.end()) DL = MI->getDebugLoc();
332 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
335 //! Return true if the specified load or store can be folded
337 SPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
338 const SmallVectorImpl<unsigned> &Ops) const {
339 if (Ops.size() != 1) return false;
341 // Make sure this is a reg-reg copy.
342 unsigned Opc = MI->getOpcode();
355 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
363 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
364 /// copy instructions, turning them into load/store instructions.
366 SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
368 const SmallVectorImpl<unsigned> &Ops,
369 int FrameIndex) const
371 if (Ops.size() != 1) return 0;
373 unsigned OpNum = Ops[0];
374 unsigned Opc = MI->getOpcode();
375 MachineInstr *NewMI = 0;
388 if (OpNum == 0) { // move -> store
389 unsigned InReg = MI->getOperand(1).getReg();
390 bool isKill = MI->getOperand(1).isKill();
391 bool isUndef = MI->getOperand(1).isUndef();
392 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
393 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(),
396 MIB.addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef));
397 NewMI = addFrameReference(MIB, FrameIndex);
399 } else { // move -> load
400 unsigned OutReg = MI->getOperand(0).getReg();
401 bool isDead = MI->getOperand(0).isDead();
402 bool isUndef = MI->getOperand(0).isUndef();
403 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc));
405 MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead) |
406 getUndefRegState(isUndef));
407 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
408 ? SPU::STQDr32 : SPU::STQXr32;
409 NewMI = addFrameReference(MIB, FrameIndex);
419 \note This code was kiped from PPC. There may be more branch analysis for
420 CellSPU than what's currently done here.
423 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
424 MachineBasicBlock *&FBB,
425 SmallVectorImpl<MachineOperand> &Cond,
426 bool AllowModify) const {
427 // If the block has no terminators, it just falls into the block after it.
428 MachineBasicBlock::iterator I = MBB.end();
429 if (I == MBB.begin())
432 while (I->isDebugValue()) {
433 if (I == MBB.begin())
437 if (!isUnpredicatedTerminator(I))
440 // Get the last instruction in the block.
441 MachineInstr *LastInst = I;
443 // If there is only one terminator instruction, process it.
444 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
445 if (isUncondBranch(LastInst)) {
446 // Check for jump tables
447 if (!LastInst->getOperand(0).isMBB())
449 TBB = LastInst->getOperand(0).getMBB();
451 } else if (isCondBranch(LastInst)) {
452 // Block ends with fall-through condbranch.
453 TBB = LastInst->getOperand(1).getMBB();
454 DEBUG(errs() << "Pushing LastInst: ");
455 DEBUG(LastInst->dump());
456 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
457 Cond.push_back(LastInst->getOperand(0));
460 // Otherwise, don't know what this is.
464 // Get the instruction before it if it's a terminator.
465 MachineInstr *SecondLastInst = I;
467 // If there are three terminators, we don't know what sort of block this is.
468 if (SecondLastInst && I != MBB.begin() &&
469 isUnpredicatedTerminator(--I))
472 // If the block ends with a conditional and unconditional branch, handle it.
473 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
474 TBB = SecondLastInst->getOperand(1).getMBB();
475 DEBUG(errs() << "Pushing SecondLastInst: ");
476 DEBUG(SecondLastInst->dump());
477 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
478 Cond.push_back(SecondLastInst->getOperand(0));
479 FBB = LastInst->getOperand(0).getMBB();
483 // If the block ends with two unconditional branches, handle it. The second
484 // one is not executed, so remove it.
485 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
486 TBB = SecondLastInst->getOperand(0).getMBB();
489 I->eraseFromParent();
493 // Otherwise, can't handle this.
498 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
499 MachineBasicBlock::iterator I = MBB.end();
500 if (I == MBB.begin())
503 while (I->isDebugValue()) {
504 if (I == MBB.begin())
508 if (!isCondBranch(I) && !isUncondBranch(I))
511 // Remove the first branch.
512 DEBUG(errs() << "Removing branch: ");
514 I->eraseFromParent();
516 if (I == MBB.begin())
520 if (!(isCondBranch(I) || isUncondBranch(I)))
523 // Remove the second branch.
524 DEBUG(errs() << "Removing second branch: ");
526 I->eraseFromParent();
531 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
532 MachineBasicBlock *FBB,
533 const SmallVectorImpl<MachineOperand> &Cond,
535 // Shouldn't be a fall through.
536 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
537 assert((Cond.size() == 2 || Cond.size() == 0) &&
538 "SPU branch conditions have two components!");
543 // Unconditional branch
544 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(SPU::BR));
547 DEBUG(errs() << "Inserted one-way uncond branch: ");
548 DEBUG((*MIB).dump());
550 // Conditional branch
551 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
552 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
554 DEBUG(errs() << "Inserted one-way cond branch: ");
555 DEBUG((*MIB).dump());
559 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
560 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
562 // Two-way Conditional Branch.
563 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
566 DEBUG(errs() << "Inserted conditional branch: ");
567 DEBUG((*MIB).dump());
568 DEBUG(errs() << "part 2: ");
569 DEBUG((*MIB2).dump());
574 //! Reverses a branch's condition, returning false on success.
576 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
578 // Pretty brainless way of inverting the condition, but it works, considering
579 // there are only two conditions...
581 unsigned Opc; //! The incoming opcode
582 unsigned RevCondOpc; //! The reversed condition opcode
584 { SPU::BRNZr32, SPU::BRZr32 },
585 { SPU::BRNZv4i32, SPU::BRZv4i32 },
586 { SPU::BRZr32, SPU::BRNZr32 },
587 { SPU::BRZv4i32, SPU::BRNZv4i32 },
588 { SPU::BRHNZr16, SPU::BRHZr16 },
589 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
590 { SPU::BRHZr16, SPU::BRHNZr16 },
591 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
594 unsigned Opc = unsigned(Cond[0].getImm());
595 // Pretty dull mapping between the two conditions that SPU can generate:
596 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
597 if (revconds[i].Opc == Opc) {
598 Cond[0].setImm(revconds[i].RevCondOpc);