1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUTargetMachine.h"
17 #include "SPUGenInstrInfo.inc"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
24 : TargetInstrInfo(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
26 RI(*TM.getSubtargetImpl(), *this)
31 /// getPointerRegClass - Return the register class to use to hold pointers.
32 /// This is used for addressing modes.
33 const TargetRegisterClass *
34 SPUInstrInfo::getPointerRegClass() const
36 return &SPU::R32CRegClass;
40 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
42 unsigned& destReg) const {
43 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
44 // cases where we can safely say that what's being done is really a move
45 // (see how PowerPC does this -- it's the model for this code too.)
46 switch (MI.getOpcode()) {
62 assert(MI.getNumOperands() == 3 &&
63 MI.getOperand(0).isRegister() &&
64 MI.getOperand(1).isRegister() &&
65 MI.getOperand(2).isImmediate() &&
66 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
67 if (MI.getOperand(2).getImmedValue() == 0) {
68 sourceReg = MI.getOperand(1).getReg();
69 destReg = MI.getOperand(0).getReg();
74 assert(MI.getNumOperands() == 3 &&
75 "wrong number of operands to AIr32");
76 if (MI.getOperand(0).isRegister() &&
77 (MI.getOperand(1).isRegister() ||
78 MI.getOperand(1).isFrameIndex()) &&
79 (MI.getOperand(2).isImmediate() &&
80 MI.getOperand(2).getImmedValue() == 0)) {
81 sourceReg = MI.getOperand(1).getReg();
82 destReg = MI.getOperand(0).getReg();
87 case SPU::ORv8i16_i16:
88 case SPU::ORv4i32_i32:
89 case SPU::ORv2i64_i64:
90 case SPU::ORv4f32_f32:
91 case SPU::ORv2f64_f64:
93 case SPU::ORi16_v8i16:
94 case SPU::ORi32_v4i32:
95 case SPU::ORi64_v2i64:
96 case SPU::ORf32_v4f32:
97 case SPU::ORf64_v2f64:
106 assert(MI.getNumOperands() == 3 &&
107 MI.getOperand(0).isRegister() &&
108 MI.getOperand(1).isRegister() &&
109 MI.getOperand(2).isRegister() &&
110 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
111 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
112 sourceReg = MI.getOperand(1).getReg();
113 destReg = MI.getOperand(0).getReg();
123 SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
124 switch (MI->getOpcode()) {
140 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
141 MI->getOperand(2).isFrameIndex()) {
142 FrameIndex = MI->getOperand(2).getFrameIndex();
143 return MI->getOperand(0).getReg();
151 SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
152 switch (MI->getOpcode()) {
174 if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
175 MI->getOperand(2).isFrameIndex()) {
176 FrameIndex = MI->getOperand(2).getFrameIndex();
177 return MI->getOperand(0).getReg();