1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUHazardRecognizers.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/Target/TargetRegistry.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
26 #define GET_INSTRINFO_CTOR
27 #define GET_INSTRINFO_MC_DESC
28 #include "SPUGenInstrInfo.inc"
33 //! Predicate for an unconditional branch instruction
34 inline bool isUncondBranch(const MachineInstr *I) {
35 unsigned opc = I->getOpcode();
37 return (opc == SPU::BR
42 //! Predicate for a conditional branch instruction
43 inline bool isCondBranch(const MachineInstr *I) {
44 unsigned opc = I->getOpcode();
46 return (opc == SPU::BRNZr32
47 || opc == SPU::BRNZv4i32
49 || opc == SPU::BRZv4i32
50 || opc == SPU::BRHNZr16
51 || opc == SPU::BRHNZv8i16
52 || opc == SPU::BRHZr16
53 || opc == SPU::BRHZv8i16);
57 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
58 : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
60 RI(*TM.getSubtargetImpl(), *this)
63 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
64 /// this target when scheduling the DAG.
65 ScheduleHazardRecognizer *SPUInstrInfo::CreateTargetHazardRecognizer(
66 const TargetMachine *TM,
67 const ScheduleDAG *DAG) const {
68 const TargetInstrInfo *TII = TM->getInstrInfo();
69 assert(TII && "No InstrInfo?");
70 return new SPUHazardRecognizer(*TII);
74 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
75 int &FrameIndex) const {
76 switch (MI->getOpcode()) {
87 const MachineOperand MOp1 = MI->getOperand(1);
88 const MachineOperand MOp2 = MI->getOperand(2);
89 if (MOp1.isImm() && MOp2.isFI()) {
90 FrameIndex = MOp2.getIndex();
91 return MI->getOperand(0).getReg();
100 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
101 int &FrameIndex) const {
102 switch (MI->getOpcode()) {
114 const MachineOperand MOp1 = MI->getOperand(1);
115 const MachineOperand MOp2 = MI->getOperand(2);
116 if (MOp1.isImm() && MOp2.isFI()) {
117 FrameIndex = MOp2.getIndex();
118 return MI->getOperand(0).getReg();
126 void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
127 MachineBasicBlock::iterator I, DebugLoc DL,
128 unsigned DestReg, unsigned SrcReg,
131 // We support cross register class moves for our aliases, such as R3 in any
132 // reg class to any other reg class containing R3. This is required because
133 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
134 // types have no specific meaning.
136 BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
137 .addReg(SrcReg, getKillRegState(KillSrc));
141 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
142 MachineBasicBlock::iterator MI,
143 unsigned SrcReg, bool isKill, int FrameIdx,
144 const TargetRegisterClass *RC,
145 const TargetRegisterInfo *TRI) const
148 bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
149 if (RC == SPU::GPRCRegisterClass) {
150 opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128);
151 } else if (RC == SPU::R64CRegisterClass) {
152 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
153 } else if (RC == SPU::R64FPRegisterClass) {
154 opc = (isValidFrameIdx ? SPU::STQDr64 : SPU::STQXr64);
155 } else if (RC == SPU::R32CRegisterClass) {
156 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
157 } else if (RC == SPU::R32FPRegisterClass) {
158 opc = (isValidFrameIdx ? SPU::STQDr32 : SPU::STQXr32);
159 } else if (RC == SPU::R16CRegisterClass) {
160 opc = (isValidFrameIdx ? SPU::STQDr16 : SPU::STQXr16);
161 } else if (RC == SPU::R8CRegisterClass) {
162 opc = (isValidFrameIdx ? SPU::STQDr8 : SPU::STQXr8);
163 } else if (RC == SPU::VECREGRegisterClass) {
164 opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
166 llvm_unreachable("Unknown regclass!");
170 if (MI != MBB.end()) DL = MI->getDebugLoc();
171 addFrameReference(BuildMI(MBB, MI, DL, get(opc))
172 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
176 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
177 MachineBasicBlock::iterator MI,
178 unsigned DestReg, int FrameIdx,
179 const TargetRegisterClass *RC,
180 const TargetRegisterInfo *TRI) const
183 bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset());
184 if (RC == SPU::GPRCRegisterClass) {
185 opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128);
186 } else if (RC == SPU::R64CRegisterClass) {
187 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
188 } else if (RC == SPU::R64FPRegisterClass) {
189 opc = (isValidFrameIdx ? SPU::LQDr64 : SPU::LQXr64);
190 } else if (RC == SPU::R32CRegisterClass) {
191 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
192 } else if (RC == SPU::R32FPRegisterClass) {
193 opc = (isValidFrameIdx ? SPU::LQDr32 : SPU::LQXr32);
194 } else if (RC == SPU::R16CRegisterClass) {
195 opc = (isValidFrameIdx ? SPU::LQDr16 : SPU::LQXr16);
196 } else if (RC == SPU::R8CRegisterClass) {
197 opc = (isValidFrameIdx ? SPU::LQDr8 : SPU::LQXr8);
198 } else if (RC == SPU::VECREGRegisterClass) {
199 opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
201 llvm_unreachable("Unknown regclass in loadRegFromStackSlot!");
205 if (MI != MBB.end()) DL = MI->getDebugLoc();
206 addFrameReference(BuildMI(MBB, MI, DL, get(opc), DestReg), FrameIdx);
211 \note This code was kiped from PPC. There may be more branch analysis for
212 CellSPU than what's currently done here.
215 SPUInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
216 MachineBasicBlock *&FBB,
217 SmallVectorImpl<MachineOperand> &Cond,
218 bool AllowModify) const {
219 // If the block has no terminators, it just falls into the block after it.
220 MachineBasicBlock::iterator I = MBB.end();
221 if (I == MBB.begin())
224 while (I->isDebugValue()) {
225 if (I == MBB.begin())
229 if (!isUnpredicatedTerminator(I))
232 // Get the last instruction in the block.
233 MachineInstr *LastInst = I;
235 // If there is only one terminator instruction, process it.
236 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
237 if (isUncondBranch(LastInst)) {
238 // Check for jump tables
239 if (!LastInst->getOperand(0).isMBB())
241 TBB = LastInst->getOperand(0).getMBB();
243 } else if (isCondBranch(LastInst)) {
244 // Block ends with fall-through condbranch.
245 TBB = LastInst->getOperand(1).getMBB();
246 DEBUG(errs() << "Pushing LastInst: ");
247 DEBUG(LastInst->dump());
248 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
249 Cond.push_back(LastInst->getOperand(0));
252 // Otherwise, don't know what this is.
256 // Get the instruction before it if it's a terminator.
257 MachineInstr *SecondLastInst = I;
259 // If there are three terminators, we don't know what sort of block this is.
260 if (SecondLastInst && I != MBB.begin() &&
261 isUnpredicatedTerminator(--I))
264 // If the block ends with a conditional and unconditional branch, handle it.
265 if (isCondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
266 TBB = SecondLastInst->getOperand(1).getMBB();
267 DEBUG(errs() << "Pushing SecondLastInst: ");
268 DEBUG(SecondLastInst->dump());
269 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
270 Cond.push_back(SecondLastInst->getOperand(0));
271 FBB = LastInst->getOperand(0).getMBB();
275 // If the block ends with two unconditional branches, handle it. The second
276 // one is not executed, so remove it.
277 if (isUncondBranch(SecondLastInst) && isUncondBranch(LastInst)) {
278 TBB = SecondLastInst->getOperand(0).getMBB();
281 I->eraseFromParent();
285 // Otherwise, can't handle this.
289 // search MBB for branch hint labels and branch hit ops
290 static void removeHBR( MachineBasicBlock &MBB) {
291 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I){
292 if (I->getOpcode() == SPU::HBRA ||
293 I->getOpcode() == SPU::HBR_LABEL){
300 SPUInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
301 MachineBasicBlock::iterator I = MBB.end();
303 if (I == MBB.begin())
306 while (I->isDebugValue()) {
307 if (I == MBB.begin())
311 if (!isCondBranch(I) && !isUncondBranch(I))
314 // Remove the first branch.
315 DEBUG(errs() << "Removing branch: ");
317 I->eraseFromParent();
319 if (I == MBB.begin())
323 if (!(isCondBranch(I) || isUncondBranch(I)))
326 // Remove the second branch.
327 DEBUG(errs() << "Removing second branch: ");
329 I->eraseFromParent();
333 /** Find the optimal position for a hint branch instruction in a basic block.
334 * This should take into account:
335 * -the branch hint delays
336 * -congestion of the memory bus
337 * -dual-issue scheduling (i.e. avoid insertion of nops)
338 * Current implementation is rather simplistic.
340 static MachineBasicBlock::iterator findHBRPosition(MachineBasicBlock &MBB)
342 MachineBasicBlock::iterator J = MBB.end();
343 for( int i=0; i<8; i++) {
344 if( J == MBB.begin() ) return J;
351 SPUInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
352 MachineBasicBlock *FBB,
353 const SmallVectorImpl<MachineOperand> &Cond,
355 // Shouldn't be a fall through.
356 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
357 assert((Cond.size() == 2 || Cond.size() == 0) &&
358 "SPU branch conditions have two components!");
360 MachineInstrBuilder MIB;
361 //TODO: make a more accurate algorithm.
362 bool haveHBR = MBB.size()>8;
365 MCSymbol *branchLabel = MBB.getParent()->getContext().CreateTempSymbol();
366 // Add a label just before the branch
368 MIB = BuildMI(&MBB, DL, get(SPU::HBR_LABEL)).addSym(branchLabel);
373 // Unconditional branch
374 MIB = BuildMI(&MBB, DL, get(SPU::BR));
377 DEBUG(errs() << "Inserted one-way uncond branch: ");
378 DEBUG((*MIB).dump());
380 // basic blocks have just one branch so it is safe to add the hint a its
382 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
383 MIB.addSym(branchLabel);
387 // Conditional branch
388 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
389 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
392 MIB = BuildMI(MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
393 MIB.addSym(branchLabel);
397 DEBUG(errs() << "Inserted one-way cond branch: ");
398 DEBUG((*MIB).dump());
402 MIB = BuildMI(&MBB, DL, get(Cond[0].getImm()));
403 MachineInstrBuilder MIB2 = BuildMI(&MBB, DL, get(SPU::BR));
405 // Two-way Conditional Branch.
406 MIB.addReg(Cond[1].getReg()).addMBB(TBB);
410 MIB = BuildMI( MBB, findHBRPosition(MBB), DL, get(SPU::HBRA));
411 MIB.addSym(branchLabel);
415 DEBUG(errs() << "Inserted conditional branch: ");
416 DEBUG((*MIB).dump());
417 DEBUG(errs() << "part 2: ");
418 DEBUG((*MIB2).dump());
423 //! Reverses a branch's condition, returning false on success.
425 SPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
427 // Pretty brainless way of inverting the condition, but it works, considering
428 // there are only two conditions...
430 unsigned Opc; //! The incoming opcode
431 unsigned RevCondOpc; //! The reversed condition opcode
433 { SPU::BRNZr32, SPU::BRZr32 },
434 { SPU::BRNZv4i32, SPU::BRZv4i32 },
435 { SPU::BRZr32, SPU::BRNZr32 },
436 { SPU::BRZv4i32, SPU::BRNZv4i32 },
437 { SPU::BRHNZr16, SPU::BRHZr16 },
438 { SPU::BRHNZv8i16, SPU::BRHZv8i16 },
439 { SPU::BRHZr16, SPU::BRHNZr16 },
440 { SPU::BRHZv8i16, SPU::BRHNZv8i16 }
443 unsigned Opc = unsigned(Cond[0].getImm());
444 // Pretty dull mapping between the two conditions that SPU can generate:
445 for (int i = sizeof(revconds)/sizeof(revconds[0]) - 1; i >= 0; --i) {
446 if (revconds[i].Opc == Opc) {
447 Cond[0].setImm(revconds[i].RevCondOpc);
455 MCInstrInfo *createSPUMCInstrInfo() {
456 MCInstrInfo *X = new MCInstrInfo();
457 InitSPUMCInstrInfo(X);
461 extern "C" void LLVMInitializeCellSPUMCInstrInfo() {
462 TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo);