1 //===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SPURegisterNames.h"
15 #include "SPUInstrInfo.h"
16 #include "SPUInstrBuilder.h"
17 #include "SPUTargetMachine.h"
18 #include "SPUGenInstrInfo.inc"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/Streams.h"
24 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
25 : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
27 RI(*TM.getSubtargetImpl(), *this)
32 /// getPointerRegClass - Return the register class to use to hold pointers.
33 /// This is used for addressing modes.
34 const TargetRegisterClass *
35 SPUInstrInfo::getPointerRegClass() const
37 return &SPU::R32CRegClass;
41 SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
43 unsigned& destReg) const {
44 // Primarily, ORI and OR are generated by copyRegToReg. But, there are other
45 // cases where we can safely say that what's being done is really a move
46 // (see how PowerPC does this -- it's the model for this code too.)
47 switch (MI.getOpcode()) {
62 assert(MI.getNumOperands() == 3 &&
63 MI.getOperand(0).isReg() &&
64 MI.getOperand(1).isReg() &&
65 MI.getOperand(2).isImm() &&
66 "invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
67 if (MI.getOperand(2).getImm() == 0) {
68 sourceReg = MI.getOperand(1).getReg();
69 destReg = MI.getOperand(0).getReg();
74 assert(MI.getNumOperands() == 3 &&
75 "wrong number of operands to AIr32");
76 if (MI.getOperand(0).isReg() &&
77 (MI.getOperand(1).isReg() ||
78 MI.getOperand(1).isFI()) &&
79 (MI.getOperand(2).isImm() &&
80 MI.getOperand(2).getImm() == 0)) {
81 sourceReg = MI.getOperand(1).getReg();
82 destReg = MI.getOperand(0).getReg();
87 case SPU::ORv8i16_i16:
88 case SPU::ORv4i32_i32:
89 case SPU::ORv2i64_i64:
90 case SPU::ORv4f32_f32:
91 case SPU::ORv2f64_f64:
93 case SPU::ORi16_v8i16:
94 case SPU::ORi32_v4i32:
95 case SPU::ORi64_v2i64:
96 case SPU::ORf32_v4f32:
97 case SPU::ORf64_v2f64:
105 assert(MI.getNumOperands() == 3 &&
106 MI.getOperand(0).isReg() &&
107 MI.getOperand(1).isReg() &&
108 MI.getOperand(2).isReg() &&
109 "invalid SPU OR(vec|r32|r64|gprc) instruction!");
110 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
111 sourceReg = MI.getOperand(1).getReg();
112 destReg = MI.getOperand(0).getReg();
122 SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
123 int &FrameIndex) const {
124 switch (MI->getOpcode()) {
140 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
141 MI->getOperand(2).isFI()) {
142 FrameIndex = MI->getOperand(2).getIndex();
143 return MI->getOperand(0).getReg();
151 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
152 int &FrameIndex) const {
153 switch (MI->getOpcode()) {
175 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
176 MI->getOperand(2).isFI()) {
177 FrameIndex = MI->getOperand(2).getIndex();
178 return MI->getOperand(0).getReg();
185 bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
186 MachineBasicBlock::iterator MI,
187 unsigned DestReg, unsigned SrcReg,
188 const TargetRegisterClass *DestRC,
189 const TargetRegisterClass *SrcRC) const
191 // We support cross register class moves for our aliases, such as R3 in any
192 // reg class to any other reg class containing R3. This is required because
193 // we instruction select bitconvert i64 -> f64 as a noop for example, so our
194 // types have no specific meaning.
196 //if (DestRC != SrcRC) {
197 // cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
201 if (DestRC == SPU::R8CRegisterClass) {
202 BuildMI(MBB, MI, get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
203 } else if (DestRC == SPU::R16CRegisterClass) {
204 BuildMI(MBB, MI, get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
205 } else if (DestRC == SPU::R32CRegisterClass) {
206 BuildMI(MBB, MI, get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
207 } else if (DestRC == SPU::R32FPRegisterClass) {
208 BuildMI(MBB, MI, get(SPU::ORf32), DestReg).addReg(SrcReg)
210 } else if (DestRC == SPU::R64CRegisterClass) {
211 BuildMI(MBB, MI, get(SPU::ORr64), DestReg).addReg(SrcReg)
213 } else if (DestRC == SPU::R64FPRegisterClass) {
214 BuildMI(MBB, MI, get(SPU::ORf64), DestReg).addReg(SrcReg)
216 } /* else if (DestRC == SPU::GPRCRegisterClass) {
217 BuildMI(MBB, MI, get(SPU::ORgprc), DestReg).addReg(SrcReg)
219 } */ else if (DestRC == SPU::VECREGRegisterClass) {
220 BuildMI(MBB, MI, get(SPU::ORv4i32), DestReg).addReg(SrcReg)
223 // Attempt to copy unknown/unsupported register class!
231 SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
232 MachineBasicBlock::iterator MI,
233 unsigned SrcReg, bool isKill, int FrameIdx,
234 const TargetRegisterClass *RC) const
237 if (RC == SPU::GPRCRegisterClass) {
238 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
241 } else if (RC == SPU::R64CRegisterClass) {
242 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
245 } else if (RC == SPU::R64FPRegisterClass) {
246 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
249 } else if (RC == SPU::R32CRegisterClass) {
250 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
253 } else if (RC == SPU::R32FPRegisterClass) {
254 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
257 } else if (RC == SPU::R16CRegisterClass) {
258 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
262 assert(0 && "Unknown regclass!");
266 addFrameReference(BuildMI(MBB, MI, get(opc))
267 .addReg(SrcReg, false, false, isKill), FrameIdx);
270 void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
272 SmallVectorImpl<MachineOperand> &Addr,
273 const TargetRegisterClass *RC,
274 SmallVectorImpl<MachineInstr*> &NewMIs) const {
275 cerr << "storeRegToAddr() invoked!\n";
278 if (Addr[0].isFI()) {
279 /* do what storeRegToStackSlot does here */
282 if (RC == SPU::GPRCRegisterClass) {
283 /* Opc = PPC::STW; */
284 } else if (RC == SPU::R16CRegisterClass) {
285 /* Opc = PPC::STD; */
286 } else if (RC == SPU::R32CRegisterClass) {
287 /* Opc = PPC::STFD; */
288 } else if (RC == SPU::R32FPRegisterClass) {
289 /* Opc = PPC::STFD; */
290 } else if (RC == SPU::R64FPRegisterClass) {
291 /* Opc = PPC::STFS; */
292 } else if (RC == SPU::VECREGRegisterClass) {
293 /* Opc = PPC::STVX; */
295 assert(0 && "Unknown regclass!");
298 MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
299 .addReg(SrcReg, false, false, isKill);
300 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
301 MachineOperand &MO = Addr[i];
303 MIB.addReg(MO.getReg());
305 MIB.addImm(MO.getImm());
307 MIB.addFrameIndex(MO.getIndex());
309 NewMIs.push_back(MIB);
314 SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
315 MachineBasicBlock::iterator MI,
316 unsigned DestReg, int FrameIdx,
317 const TargetRegisterClass *RC) const
320 if (RC == SPU::GPRCRegisterClass) {
321 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
324 } else if (RC == SPU::R64CRegisterClass) {
325 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
328 } else if (RC == SPU::R64FPRegisterClass) {
329 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
332 } else if (RC == SPU::R32CRegisterClass) {
333 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
336 } else if (RC == SPU::R32FPRegisterClass) {
337 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
340 } else if (RC == SPU::R16CRegisterClass) {
341 opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
345 assert(0 && "Unknown regclass in loadRegFromStackSlot!");
349 addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
353 \note We are really pessimistic here about what kind of a load we're doing.
355 void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
356 SmallVectorImpl<MachineOperand> &Addr,
357 const TargetRegisterClass *RC,
358 SmallVectorImpl<MachineInstr*> &NewMIs)
360 cerr << "loadRegToAddr() invoked!\n";
363 if (Addr[0].isFI()) {
364 /* do what loadRegFromStackSlot does here... */
367 if (RC == SPU::R8CRegisterClass) {
368 /* do brilliance here */
369 } else if (RC == SPU::R16CRegisterClass) {
370 /* Opc = PPC::LWZ; */
371 } else if (RC == SPU::R32CRegisterClass) {
373 } else if (RC == SPU::R32FPRegisterClass) {
374 /* Opc = PPC::LFD; */
375 } else if (RC == SPU::R64FPRegisterClass) {
376 /* Opc = PPC::LFS; */
377 } else if (RC == SPU::VECREGRegisterClass) {
378 /* Opc = PPC::LVX; */
379 } else if (RC == SPU::GPRCRegisterClass) {
380 /* Opc = something else! */
382 assert(0 && "Unknown regclass!");
385 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
386 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
387 MachineOperand &MO = Addr[i];
389 MIB.addReg(MO.getReg());
391 MIB.addImm(MO.getImm());
393 MIB.addFrameIndex(MO.getIndex());
395 NewMIs.push_back(MIB);
399 /// foldMemoryOperand - SPU, like PPC, can only fold spills into
400 /// copy instructions, turning them into load/store instructions.
402 SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
404 const SmallVectorImpl<unsigned> &Ops,
405 int FrameIndex) const
407 #if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
408 if (Ops.size() != 1) return NULL;
410 unsigned OpNum = Ops[0];
411 unsigned Opc = MI->getOpcode();
412 MachineInstr *NewMI = 0;
414 if ((Opc == SPU::ORr32
415 || Opc == SPU::ORv4i32)
416 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
417 if (OpNum == 0) { // move -> store
418 unsigned InReg = MI->getOperand(1).getReg();
419 bool isKill = MI->getOperand(1).isKill();
420 if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
421 NewMI = addFrameReference(BuildMI(MF, TII.get(SPU::STQDr32))
422 .addReg(InReg, false, false, isKill),
425 } else { // move -> load
426 unsigned OutReg = MI->getOperand(0).getReg();
427 bool isDead = MI->getOperand(0).isDead();
428 Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset())
429 ? SPU::STQDr32 : SPU::STQXr32;
430 NewMI = addFrameReference(BuildMI(MF, TII.get(Opc))
431 .addReg(OutReg, true, false, false, isDead), FrameIndex);