1 //===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the CellSPU implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef SPU_INSTRUCTIONINFO_H
15 #define SPU_INSTRUCTIONINFO_H
18 #include "llvm/Target/TargetInstrInfo.h"
19 #include "SPURegisterInfo.h"
22 //! Cell SPU instruction information class
23 class SPUInstrInfo : public TargetInstrInfoImpl {
25 const SPURegisterInfo RI;
27 explicit SPUInstrInfo(SPUTargetMachine &tm);
29 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
30 /// such, whenever a client has an instance of instruction info, it should
31 /// always be able to get register info as well (through this method).
33 virtual const SPURegisterInfo &getRegisterInfo() const { return RI; }
35 /// Return true if the instruction is a register to register move and return
36 /// the source and dest operands and their sub-register indices by reference.
37 virtual bool isMoveInstr(const MachineInstr &MI,
38 unsigned &SrcReg, unsigned &DstReg,
39 unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
41 unsigned isLoadFromStackSlot(const MachineInstr *MI,
42 int &FrameIndex) const;
43 unsigned isStoreToStackSlot(const MachineInstr *MI,
44 int &FrameIndex) const;
46 virtual void copyPhysReg(MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator I, DebugLoc DL,
48 unsigned DestReg, unsigned SrcReg,
51 //! Store a register to a stack slot, based on its register class.
52 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI,
54 unsigned SrcReg, bool isKill, int FrameIndex,
55 const TargetRegisterClass *RC,
56 const TargetRegisterInfo *TRI) const;
58 //! Load a register from a stack slot, based on its register class.
59 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator MBBI,
61 unsigned DestReg, int FrameIndex,
62 const TargetRegisterClass *RC,
63 const TargetRegisterInfo *TRI) const;
65 //! Reverses a branch's condition, returning false on success.
67 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
69 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
70 MachineBasicBlock *&FBB,
71 SmallVectorImpl<MachineOperand> &Cond,
72 bool AllowModify) const;
74 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
76 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
77 MachineBasicBlock *FBB,
78 const SmallVectorImpl<MachineOperand> &Cond,