1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start timm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end timm:$amt)]>;
33 //===----------------------------------------------------------------------===//
34 // DWARF debugging Pseudo Instructions
35 //===----------------------------------------------------------------------===//
37 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
38 "${:comment} .loc $file, $line, $col",
39 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
42 //===----------------------------------------------------------------------===//
44 // NB: The ordering is actually important, since the instruction selection
45 // will try each of the instructions in sequence, i.e., the D-form first with
46 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
47 // finally the X-form with the register-register.
48 //===----------------------------------------------------------------------===//
50 let isSimpleLoad = 1 in {
51 class LoadDFormVec<ValueType vectype>
52 : RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
55 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
58 class LoadDForm<RegisterClass rclass>
59 : RI10Form<0b00101100, (outs rclass:$rT), (ins memri10:$src),
62 [(set rclass:$rT, (load dform_addr:$src))]>
67 def v16i8: LoadDFormVec<v16i8>;
68 def v8i16: LoadDFormVec<v8i16>;
69 def v4i32: LoadDFormVec<v4i32>;
70 def v2i64: LoadDFormVec<v2i64>;
71 def v4f32: LoadDFormVec<v4f32>;
72 def v2f64: LoadDFormVec<v2f64>;
74 def r128: LoadDForm<GPRC>;
75 def r64: LoadDForm<R64C>;
76 def r32: LoadDForm<R32C>;
77 def f32: LoadDForm<R32FP>;
78 def f64: LoadDForm<R64FP>;
79 def r16: LoadDForm<R16C>;
80 def r8: LoadDForm<R8C>;
83 class LoadAFormVec<ValueType vectype>
84 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
87 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
90 class LoadAForm<RegisterClass rclass>
91 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
94 [(set rclass:$rT, (load aform_addr:$src))]>
99 def v16i8: LoadAFormVec<v16i8>;
100 def v8i16: LoadAFormVec<v8i16>;
101 def v4i32: LoadAFormVec<v4i32>;
102 def v2i64: LoadAFormVec<v2i64>;
103 def v4f32: LoadAFormVec<v4f32>;
104 def v2f64: LoadAFormVec<v2f64>;
106 def r128: LoadAForm<GPRC>;
107 def r64: LoadAForm<R64C>;
108 def r32: LoadAForm<R32C>;
109 def f32: LoadAForm<R32FP>;
110 def f64: LoadAForm<R64FP>;
111 def r16: LoadAForm<R16C>;
112 def r8: LoadAForm<R8C>;
115 class LoadXFormVec<ValueType vectype>
116 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
119 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
122 class LoadXForm<RegisterClass rclass>
123 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
126 [(set rclass:$rT, (load xform_addr:$src))]>
129 multiclass LoadXForms
131 def v16i8: LoadXFormVec<v16i8>;
132 def v8i16: LoadXFormVec<v8i16>;
133 def v4i32: LoadXFormVec<v4i32>;
134 def v2i64: LoadXFormVec<v2i64>;
135 def v4f32: LoadXFormVec<v4f32>;
136 def v2f64: LoadXFormVec<v2f64>;
138 def r128: LoadXForm<GPRC>;
139 def r64: LoadXForm<R64C>;
140 def r32: LoadXForm<R32C>;
141 def f32: LoadXForm<R32FP>;
142 def f64: LoadXForm<R64FP>;
143 def r16: LoadXForm<R16C>;
144 def r8: LoadXForm<R8C>;
147 defm LQA : LoadAForms;
148 defm LQD : LoadDForms;
149 defm LQX : LoadXForms;
151 /* Load quadword, PC relative: Not much use at this point in time.
152 Might be of use later for relocatable code. It's effectively the
153 same as LQA, but uses PC-relative addressing.
154 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
155 "lqr\t$rT, $disp", LoadStore,
156 [(set VECREG:$rT, (load iaddr:$disp))]>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
163 class StoreDFormVec<ValueType vectype>
164 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
167 [(store (vectype VECREG:$rT), dform_addr:$src)]>
170 class StoreDForm<RegisterClass rclass>
171 : RI10Form<0b00100100, (outs), (ins rclass:$rT, memri10:$src),
174 [(store rclass:$rT, dform_addr:$src)]>
177 multiclass StoreDForms
179 def v16i8: StoreDFormVec<v16i8>;
180 def v8i16: StoreDFormVec<v8i16>;
181 def v4i32: StoreDFormVec<v4i32>;
182 def v2i64: StoreDFormVec<v2i64>;
183 def v4f32: StoreDFormVec<v4f32>;
184 def v2f64: StoreDFormVec<v2f64>;
186 def r128: StoreDForm<GPRC>;
187 def r64: StoreDForm<R64C>;
188 def r32: StoreDForm<R32C>;
189 def f32: StoreDForm<R32FP>;
190 def f64: StoreDForm<R64FP>;
191 def r16: StoreDForm<R16C>;
192 def r8: StoreDForm<R8C>;
195 class StoreAFormVec<ValueType vectype>
196 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
199 [(store (vectype VECREG:$rT), aform_addr:$src)]>;
201 class StoreAForm<RegisterClass rclass>
202 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
205 [(store rclass:$rT, aform_addr:$src)]>;
207 multiclass StoreAForms
209 def v16i8: StoreAFormVec<v16i8>;
210 def v8i16: StoreAFormVec<v8i16>;
211 def v4i32: StoreAFormVec<v4i32>;
212 def v2i64: StoreAFormVec<v2i64>;
213 def v4f32: StoreAFormVec<v4f32>;
214 def v2f64: StoreAFormVec<v2f64>;
216 def r128: StoreAForm<GPRC>;
217 def r64: StoreAForm<R64C>;
218 def r32: StoreAForm<R32C>;
219 def f32: StoreAForm<R32FP>;
220 def f64: StoreAForm<R64FP>;
221 def r16: StoreAForm<R16C>;
222 def r8: StoreAForm<R8C>;
225 class StoreXFormVec<ValueType vectype>
226 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
229 [(store (vectype VECREG:$rT), xform_addr:$src)]>
232 class StoreXForm<RegisterClass rclass>
233 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
236 [(store rclass:$rT, xform_addr:$src)]>
239 multiclass StoreXForms
241 def v16i8: StoreXFormVec<v16i8>;
242 def v8i16: StoreXFormVec<v8i16>;
243 def v4i32: StoreXFormVec<v4i32>;
244 def v2i64: StoreXFormVec<v2i64>;
245 def v4f32: StoreXFormVec<v4f32>;
246 def v2f64: StoreXFormVec<v2f64>;
248 def r128: StoreXForm<GPRC>;
249 def r64: StoreXForm<R64C>;
250 def r32: StoreXForm<R32C>;
251 def f32: StoreXForm<R32FP>;
252 def f64: StoreXForm<R64FP>;
253 def r16: StoreXForm<R16C>;
254 def r8: StoreXForm<R8C>;
257 defm STQD : StoreDForms;
258 defm STQA : StoreAForms;
259 defm STQX : StoreXForms;
261 /* Store quadword, PC relative: Not much use at this point in time. Might
262 be useful for relocatable code.
263 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
264 "stqr\t$rT, $disp", LoadStore,
265 [(store VECREG:$rT, iaddr:$disp)]>;
268 //===----------------------------------------------------------------------===//
269 // Generate Controls for Insertion:
270 //===----------------------------------------------------------------------===//
273 RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
274 "cbd\t$rT, $src", ShuffleOp,
275 [(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
277 def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
278 "cbx\t$rT, $src", ShuffleOp,
279 [(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
281 def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
282 "chd\t$rT, $src", ShuffleOp,
283 [(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
285 def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
286 "chx\t$rT, $src", ShuffleOp,
287 [(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
289 def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
290 "cwd\t$rT, $src", ShuffleOp,
291 [(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
293 def CWDf32 : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
294 "cwd\t$rT, $src", ShuffleOp,
295 [(set (v4f32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
297 def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
298 "cwx\t$rT, $src", ShuffleOp,
299 [(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
301 def CWXf32 : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
302 "cwx\t$rT, $src", ShuffleOp,
303 [(set (v4f32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
305 def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
306 "cdd\t$rT, $src", ShuffleOp,
307 [(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
309 def CDDf64 : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
310 "cdd\t$rT, $src", ShuffleOp,
311 [(set (v2f64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
313 def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
314 "cdx\t$rT, $src", ShuffleOp,
315 [(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
317 def CDXf64 : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
318 "cdx\t$rT, $src", ShuffleOp,
319 [(set (v2f64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
321 //===----------------------------------------------------------------------===//
322 // Constant formation:
323 //===----------------------------------------------------------------------===//
326 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
327 "ilh\t$rT, $val", ImmLoad,
328 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
331 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
332 "ilh\t$rT, $val", ImmLoad,
333 [(set R16C:$rT, immSExt16:$val)]>;
335 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
336 // the right constant")
338 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
339 "ilh\t$rT, $val", ImmLoad,
340 [(set R8C:$rT, immSExt8:$val)]>;
342 // IL does sign extension!
344 class ILInst<dag OOL, dag IOL, list<dag> pattern>:
345 RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val",
348 class ILVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
349 ILInst<(outs VECREG:$rT), (ins immtype:$val),
350 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
352 class ILRegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
353 ILInst<(outs rclass:$rT), (ins immtype:$val),
354 [(set rclass:$rT, xform:$val)]>;
356 multiclass ImmediateLoad
358 def v2i64: ILVecInst<v2i64, s16imm_i64, v2i64SExt16Imm>;
359 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
361 // TODO: Need v2f64, v4f32
363 def r64: ILRegInst<R64C, s16imm_i64, immSExt16>;
364 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
365 def f32: ILRegInst<R32FP, s16imm_f32, fpimmSExt16>;
366 def f64: ILRegInst<R64FP, s16imm_f64, fpimmSExt16>;
369 defm IL : ImmediateLoad;
371 class ILHUInst<dag OOL, dag IOL, list<dag> pattern>:
372 RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val",
375 class ILHUVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
376 ILHUInst<(outs VECREG:$rT), (ins immtype:$val),
377 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
379 class ILHURegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
380 ILHUInst<(outs rclass:$rT), (ins immtype:$val),
381 [(set rclass:$rT, xform:$val)]>;
383 multiclass ImmLoadHalfwordUpper
385 def v2i64: ILHUVecInst<v2i64, u16imm_i64, immILHUvec_i64>;
386 def v4i32: ILHUVecInst<v4i32, u16imm_i32, immILHUvec>;
388 def r64: ILHURegInst<R64C, u16imm_i64, hi16>;
389 def r32: ILHURegInst<R32C, u16imm_i32, hi16>;
391 // Loads the high portion of an address
392 def hi: ILHURegInst<R32C, symbolHi, hi16>;
394 // Used in custom lowering constant SFP loads:
395 def f32: ILHURegInst<R32FP, f16imm, hi16_f32>;
398 defm ILHU : ImmLoadHalfwordUpper;
400 // Immediate load address (can also be used to load 18-bit unsigned constants,
401 // see the zext 16->32 pattern)
403 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
404 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
407 class ILAVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
408 ILAInst<(outs VECREG:$rT), (ins immtype:$val),
409 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
411 class ILARegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
412 ILAInst<(outs rclass:$rT), (ins immtype:$val),
413 [(set rclass:$rT, xform:$val)]>;
415 multiclass ImmLoadAddress
417 def v2i64: ILAVecInst<v2i64, u18imm, v2i64Uns18Imm>;
418 def v4i32: ILAVecInst<v4i32, u18imm, v4i32Uns18Imm>;
420 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
421 def r32: ILARegInst<R32C, u18imm, imm18>;
422 def f32: ILARegInst<R32FP, f18imm, fpimm18>;
423 def f64: ILARegInst<R64FP, f18imm_f64, fpimm18>;
425 def lo: ILARegInst<R32C, symbolLo, imm18>;
427 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
431 defm ILA : ImmLoadAddress;
433 // Immediate OR, Halfword Lower: The "other" part of loading large constants
434 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
435 // Note that these are really two operand instructions, but they're encoded
436 // as three operands with the first two arguments tied-to each other.
438 class IOHLInst<dag OOL, dag IOL, list<dag> pattern>:
439 RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val",
441 RegConstraint<"$rS = $rT">,
444 class IOHLVecInst<ValueType vectype, Operand immtype /* , PatLeaf xform */>:
445 IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val),
448 class IOHLRegInst<RegisterClass rclass, Operand immtype /* , PatLeaf xform */>:
449 IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val),
452 multiclass ImmOrHalfwordLower
454 def v2i64: IOHLVecInst<v2i64, u16imm_i64>;
455 def v4i32: IOHLVecInst<v4i32, u16imm_i32>;
457 def r32: IOHLRegInst<R32C, i32imm>;
458 def f32: IOHLRegInst<R32FP, f32imm>;
460 def lo: IOHLRegInst<R32C, symbolLo>;
463 defm IOHL: ImmOrHalfwordLower;
465 // Form select mask for bytes using immediate, used in conjunction with the
468 class FSMBIVec<ValueType vectype>:
469 RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
472 [(set (vectype VECREG:$rT), (SPUselmask (i16 immU16:$val)))]>;
474 multiclass FormSelectMaskBytesImm
476 def v16i8: FSMBIVec<v16i8>;
477 def v8i16: FSMBIVec<v8i16>;
478 def v4i32: FSMBIVec<v4i32>;
479 def v2i64: FSMBIVec<v2i64>;
482 defm FSMBI : FormSelectMaskBytesImm;
484 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
486 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
487 "fsmb\t$rT, $rA", SelectOp,
488 [(set (v16i8 VECREG:$rT), (SPUselmask R16C:$rA))]>;
490 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
491 // only 8-bits wide (even though it's input as 16-bits here)
493 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
494 "fsmh\t$rT, $rA", SelectOp,
495 [(set (v8i16 VECREG:$rT), (SPUselmask R16C:$rA))]>;
497 // fsm: Form select mask for words. Like the other fsm* instructions,
498 // only the lower 4 bits of $rA are significant.
499 class FSMInst<ValueType vectype, RegisterClass rclass>:
500 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins rclass:$rA),
503 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
505 multiclass FormSelectMaskWord {
506 def r32 : FSMInst<v4i32, R32C>;
507 def r16 : FSMInst<v4i32, R16C>;
510 defm FSM : FormSelectMaskWord;
512 // Special case when used for i64 math operations
513 multiclass FormSelectMaskWord64 {
514 def r32 : FSMInst<v2i64, R32C>;
515 def r16 : FSMInst<v2i64, R16C>;
518 defm FSM64 : FormSelectMaskWord64;
520 //===----------------------------------------------------------------------===//
521 // Integer and Logical Operations:
522 //===----------------------------------------------------------------------===//
525 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
526 "ah\t$rT, $rA, $rB", IntegerOp,
527 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
529 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
530 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
533 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
534 "ah\t$rT, $rA, $rB", IntegerOp,
535 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
538 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
539 "ahi\t$rT, $rA, $val", IntegerOp,
540 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
541 v8i16SExt10Imm:$val))]>;
544 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
545 "ahi\t$rT, $rA, $val", IntegerOp,
546 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
549 RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
550 "a\t$rT, $rA, $rB", IntegerOp,
551 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
553 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
554 (Avec VECREG:$rA, VECREG:$rB)>;
557 RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
558 "a\t$rT, $rA, $rB", IntegerOp,
559 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
562 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
563 "a\t$rT, $rA, $rB", IntegerOp,
567 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
568 "ai\t$rT, $rA, $val", IntegerOp,
569 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
570 v4i32SExt10Imm:$val))]>;
573 RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
574 "ai\t$rT, $rA, $val", IntegerOp,
575 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
578 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
579 "sfh\t$rT, $rA, $rB", IntegerOp,
580 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
581 (v8i16 VECREG:$rB)))]>;
584 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
585 "sfh\t$rT, $rA, $rB", IntegerOp,
586 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
589 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
590 "sfhi\t$rT, $rA, $val", IntegerOp,
591 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
592 (v8i16 VECREG:$rA)))]>;
594 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
595 "sfhi\t$rT, $rA, $val", IntegerOp,
596 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
598 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
599 (ins VECREG:$rA, VECREG:$rB),
600 "sf\t$rT, $rA, $rB", IntegerOp,
601 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
603 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
604 "sf\t$rT, $rA, $rB", IntegerOp,
605 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
608 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
609 "sfi\t$rT, $rA, $val", IntegerOp,
610 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
611 (v4i32 VECREG:$rA)))]>;
613 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
614 (ins R32C:$rA, s10imm_i32:$val),
615 "sfi\t$rT, $rA, $val", IntegerOp,
616 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
618 // ADDX: only available in vector form, doesn't match a pattern.
619 class ADDXInst<dag OOL, dag IOL, list<dag> pattern>:
620 RRForm<0b00000010110, OOL, IOL,
621 "addx\t$rT, $rA, $rB",
624 class ADDXVecInst<ValueType vectype>:
625 ADDXInst<(outs VECREG:$rT),
626 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
627 [(set (vectype VECREG:$rT),
628 (SPUaddx (vectype VECREG:$rA), (vectype VECREG:$rB),
629 (vectype VECREG:$rCarry)))]>,
630 RegConstraint<"$rCarry = $rT">,
633 class ADDXRegInst<RegisterClass rclass>:
634 ADDXInst<(outs rclass:$rT),
635 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
637 (SPUaddx rclass:$rA, rclass:$rB, rclass:$rCarry))]>,
638 RegConstraint<"$rCarry = $rT">,
641 multiclass AddExtended {
642 def v2i64 : ADDXVecInst<v2i64>;
643 def v4i32 : ADDXVecInst<v4i32>;
644 def r64 : ADDXRegInst<R64C>;
645 def r32 : ADDXRegInst<R32C>;
648 defm ADDX : AddExtended;
650 // CG: Generate carry for add
651 class CGInst<dag OOL, dag IOL, list<dag> pattern>:
652 RRForm<0b01000011000, OOL, IOL,
656 class CGVecInst<ValueType vectype>:
657 CGInst<(outs VECREG:$rT),
658 (ins VECREG:$rA, VECREG:$rB),
659 [(set (vectype VECREG:$rT),
660 (SPUcarry_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
662 class CGRegInst<RegisterClass rclass>:
663 CGInst<(outs rclass:$rT),
664 (ins rclass:$rA, rclass:$rB),
666 (SPUcarry_gen rclass:$rA, rclass:$rB))]>;
668 multiclass CarryGenerate {
669 def v2i64 : CGVecInst<v2i64>;
670 def v4i32 : CGVecInst<v4i32>;
671 def r64 : CGRegInst<R64C>;
672 def r32 : CGRegInst<R32C>;
675 defm CG : CarryGenerate;
677 // SFX: Subract from, extended. This is used in conjunction with BG to subtract
678 // with carry (borrow, in this case)
679 class SFXInst<dag OOL, dag IOL, list<dag> pattern>:
680 RRForm<0b10000010110, OOL, IOL,
681 "sfx\t$rT, $rA, $rB",
684 class SFXVecInst<ValueType vectype>:
685 SFXInst<(outs VECREG:$rT),
686 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
687 [(set (vectype VECREG:$rT),
688 (SPUsubx (vectype VECREG:$rA), (vectype VECREG:$rB),
689 (vectype VECREG:$rCarry)))]>,
690 RegConstraint<"$rCarry = $rT">,
693 class SFXRegInst<RegisterClass rclass>:
694 SFXInst<(outs rclass:$rT),
695 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
697 (SPUsubx rclass:$rA, rclass:$rB, rclass:$rCarry))]>,
698 RegConstraint<"$rCarry = $rT">,
701 multiclass SubtractExtended {
702 def v2i64 : SFXVecInst<v2i64>;
703 def v4i32 : SFXVecInst<v4i32>;
704 def r64 : SFXRegInst<R64C>;
705 def r32 : SFXRegInst<R32C>;
708 defm SFX : SubtractExtended;
710 // BG: only available in vector form, doesn't match a pattern.
711 class BGInst<dag OOL, dag IOL, list<dag> pattern>:
712 RRForm<0b01000010000, OOL, IOL,
716 class BGVecInst<ValueType vectype>:
717 BGInst<(outs VECREG:$rT),
718 (ins VECREG:$rA, VECREG:$rB),
719 [(set (vectype VECREG:$rT),
720 (SPUborrow_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
722 class BGRegInst<RegisterClass rclass>:
723 BGInst<(outs rclass:$rT),
724 (ins rclass:$rA, rclass:$rB),
726 (SPUborrow_gen rclass:$rA, rclass:$rB))]>;
728 multiclass BorrowGenerate {
729 def v4i32 : BGVecInst<v4i32>;
730 def v2i64 : BGVecInst<v2i64>;
731 def r64 : BGRegInst<R64C>;
732 def r32 : BGRegInst<R32C>;
735 defm BG : BorrowGenerate;
737 // BGX: Borrow generate, extended.
739 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
741 "bgx\t$rT, $rA, $rB", IntegerOp,
743 RegConstraint<"$rCarry = $rT">,
746 // Halfword multiply variants:
747 // N.B: These can be used to build up larger quantities (16x16 -> 32)
750 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
751 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
752 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
753 (v8i16 VECREG:$rB)))]>;
756 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
757 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
758 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
761 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
762 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
763 [(set (v4i32 VECREG:$rT),
764 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
767 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
768 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
769 [(set R32C:$rT, (mul (zext R16C:$rA),
773 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
774 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
775 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
777 // mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
778 // this only produces the lower 16 bits)
780 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
781 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
782 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
785 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
786 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
787 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
789 // mpyui: same issues as other multiplies, plus, this doesn't match a
790 // pattern... but may be used during target DAG selection or lowering
792 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
793 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
797 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
798 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
801 // mpya: 16 x 16 + 16 -> 32 bit result
803 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
804 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
805 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
806 (v8i16 VECREG:$rB)))),
807 (v4i32 VECREG:$rC)))]>;
810 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
811 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
812 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
815 def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
816 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
818 def MPYAr32_sextinreg:
819 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
820 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
821 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
822 (sext_inreg R32C:$rB, i16)),
826 // RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
827 // "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
828 // [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
831 // mpyh: multiply high, used to synthesize 32-bit multiplies
833 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
834 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
835 [(set (v4i32 VECREG:$rT),
836 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
839 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
840 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
841 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
843 // mpys: multiply high and shift right (returns the top half of
844 // a 16-bit multiply, sign extended to 32 bits.)
846 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
847 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
851 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
852 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
855 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
856 // the top 16 bits of the $rA, $rB)
858 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
859 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
860 [(set (v8i16 VECREG:$rT),
861 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
864 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
865 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
868 // mpyhha: Multiply high-high, add to $rT:
870 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
871 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
875 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
876 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
879 // mpyhhu: Multiply high-high, unsigned
881 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
882 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
886 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
887 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
890 // mpyhhau: Multiply high-high, unsigned
892 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
893 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
897 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
898 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
901 // clz: Count leading zeroes
903 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
904 "clz\t$rT, $rA", IntegerOp,
908 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
909 "clz\t$rT, $rA", IntegerOp,
910 [(set R32C:$rT, (ctlz R32C:$rA))]>;
912 // cntb: Count ones in bytes (aka "population count")
913 // NOTE: This instruction is really a vector instruction, but the custom
914 // lowering code uses it in unorthodox ways to support CTPOP for other
917 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
918 "cntb\t$rT, $rA", IntegerOp,
919 [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>;
922 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
923 "cntb\t$rT, $rA", IntegerOp,
924 [(set (v8i16 VECREG:$rT), (SPUcntb (v8i16 VECREG:$rA)))]>;
927 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
928 "cntb\t$rT, $rA", IntegerOp,
929 [(set (v4i32 VECREG:$rT), (SPUcntb (v4i32 VECREG:$rA)))]>;
931 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
932 // quantity stored into $rT
934 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
935 "gbb\t$rT, $rA", GatherOp,
938 // gbh: Gather all low order bits from each halfword in $rA into a single
939 // 8-bit quantity stored in $rT
941 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
942 "gbh\t$rT, $rA", GatherOp,
945 // gb: Gather all low order bits from each word in $rA into a single
946 // 4-bit quantity stored in $rT
948 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
949 "gb\t$rT, $rA", GatherOp,
952 // avgb: average bytes
954 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
955 "avgb\t$rT, $rA, $rB", ByteOp,
958 // absdb: absolute difference of bytes
960 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
961 "absdb\t$rT, $rA, $rB", ByteOp,
964 // sumb: sum bytes into halfwords
966 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
967 "sumb\t$rT, $rA, $rB", ByteOp,
970 // Sign extension operations:
971 class XSBHInst<dag OOL, dag IOL, list<dag> pattern>:
972 RRForm_1<0b01101101010, OOL, IOL,
973 "xsbh\t$rDst, $rSrc",
976 class XSBHVecInst<ValueType vectype>:
977 XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
978 [(set (v8i16 VECREG:$rDst), (sext (vectype VECREG:$rSrc)))]>;
980 class XSBHRegInst<RegisterClass rclass>:
981 XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc),
982 [(set rclass:$rDst, (sext_inreg rclass:$rSrc, i8))]>;
984 multiclass ExtendByteHalfword {
985 def v16i8: XSBHVecInst<v8i16>;
986 def r16: XSBHRegInst<R16C>;
988 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
989 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
990 // pattern below). Intentionally doesn't match a pattern because we want the
991 // sext 8->32 pattern to do the work for us, namely because we need the extra
993 def r32: XSBHRegInst<R32C>;
996 defm XSBH : ExtendByteHalfword;
998 // Sign-extend, but take an 8-bit register to a 16-bit register (not done as
1001 XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc),
1002 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
1004 // Sign extend halfwords to words:
1006 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
1007 "xshw\t$rDest, $rSrc", IntegerOp,
1008 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
1011 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
1012 "xshw\t$rDst, $rSrc", IntegerOp,
1013 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
1016 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
1017 "xshw\t$rDst, $rSrc", IntegerOp,
1018 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
1021 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
1022 "xswd\t$rDst, $rSrc", IntegerOp,
1023 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
1026 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
1027 "xswd\t$rDst, $rSrc", IntegerOp,
1028 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
1031 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
1032 "xswd\t$rDst, $rSrc", IntegerOp,
1033 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
1035 def : Pat<(sext R32C:$inp),
1036 (XSWDr32 R32C:$inp)>;
1040 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
1041 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
1042 IntegerOp, pattern>;
1044 class ANDVecInst<ValueType vectype>:
1045 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1046 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1047 (vectype VECREG:$rB)))]>;
1049 class ANDRegInst<RegisterClass rclass>:
1050 ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1051 [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>;
1053 multiclass BitwiseAnd
1055 def v16i8: ANDVecInst<v16i8>;
1056 def v8i16: ANDVecInst<v8i16>;
1057 def v4i32: ANDVecInst<v4i32>;
1058 def v2i64: ANDVecInst<v2i64>;
1060 def r128: ANDRegInst<GPRC>;
1061 def r64: ANDRegInst<R64C>;
1062 def r32: ANDRegInst<R32C>;
1063 def r16: ANDRegInst<R16C>;
1064 def r8: ANDRegInst<R8C>;
1066 //===---------------------------------------------
1067 // Special instructions to perform the fabs instruction
1068 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1069 [/* Intentionally does not match a pattern */]>;
1071 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1072 [/* Intentionally does not match a pattern */]>;
1074 // Could use v4i32, but won't for clarity
1075 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1076 [/* Intentionally does not match a pattern */]>;
1078 //===---------------------------------------------
1080 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
1081 // quantities -- see 16->32 zext pattern.
1083 // This pattern is somewhat artificial, since it might match some
1084 // compiler generated pattern but it is unlikely to do so.
1086 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
1087 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
1090 defm AND : BitwiseAnd;
1092 // N.B.: vnot_conv is one of those special target selection pattern fragments,
1093 // in which we expect there to be a bit_convert on the constant. Bear in mind
1094 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
1095 // constant -1 vector.)
1097 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
1098 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
1099 IntegerOp, pattern>;
1101 class ANDCVecInst<ValueType vectype>:
1102 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1103 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1104 (vnot (vectype VECREG:$rB))))]>;
1106 class ANDCRegInst<RegisterClass rclass>:
1107 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1108 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
1110 multiclass AndComplement
1112 def v16i8: ANDCVecInst<v16i8>;
1113 def v8i16: ANDCVecInst<v8i16>;
1114 def v4i32: ANDCVecInst<v4i32>;
1115 def v2i64: ANDCVecInst<v2i64>;
1117 def r128: ANDCRegInst<GPRC>;
1118 def r64: ANDCRegInst<R64C>;
1119 def r32: ANDCRegInst<R32C>;
1120 def r16: ANDCRegInst<R16C>;
1121 def r8: ANDCRegInst<R8C>;
1124 defm ANDC : AndComplement;
1126 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1127 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1128 IntegerOp, pattern>;
1130 multiclass AndByteImm
1132 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1133 [(set (v16i8 VECREG:$rT),
1134 (and (v16i8 VECREG:$rA),
1135 (v16i8 v16i8U8Imm:$val)))]>;
1137 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1138 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1141 defm ANDBI : AndByteImm;
1143 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1144 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1145 IntegerOp, pattern>;
1147 multiclass AndHalfwordImm
1149 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1150 [(set (v8i16 VECREG:$rT),
1151 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1153 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1154 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1156 // Zero-extend i8 to i16:
1157 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1158 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1161 defm ANDHI : AndHalfwordImm;
1163 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1164 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1165 IntegerOp, pattern>;
1167 multiclass AndWordImm
1169 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1170 [(set (v4i32 VECREG:$rT),
1171 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1173 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1174 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1176 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1178 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1180 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1182 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1183 // zext 16->32 pattern below.
1185 // Note that this pattern is somewhat artificial, since it might match
1186 // something the compiler generates but is unlikely to occur in practice.
1187 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1189 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1192 defm ANDI : AndWordImm;
1194 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1195 // Bitwise OR group:
1196 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1198 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1199 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1200 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1201 IntegerOp, pattern>;
1203 class ORVecInst<ValueType vectype>:
1204 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1205 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1206 (vectype VECREG:$rB)))]>;
1208 class ORRegInst<RegisterClass rclass>:
1209 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1210 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1212 class ORPromoteScalar<RegisterClass rclass>:
1213 ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB),
1214 [/* no pattern */]>;
1216 class ORExtractElt<RegisterClass rclass>:
1217 ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB),
1218 [/* no pattern */]>;
1220 multiclass BitwiseOr
1222 def v16i8: ORVecInst<v16i8>;
1223 def v8i16: ORVecInst<v8i16>;
1224 def v4i32: ORVecInst<v4i32>;
1225 def v2i64: ORVecInst<v2i64>;
1227 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1228 [(set (v4f32 VECREG:$rT),
1229 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1230 (v4i32 VECREG:$rB)))))]>;
1232 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1233 [(set (v2f64 VECREG:$rT),
1234 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1235 (v2i64 VECREG:$rB)))))]>;
1237 def r64: ORRegInst<R64C>;
1238 def r32: ORRegInst<R32C>;
1239 def r16: ORRegInst<R16C>;
1240 def r8: ORRegInst<R8C>;
1242 // OR instructions used to copy f32 and f64 registers.
1243 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1244 [/* no pattern */]>;
1246 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1247 [/* no pattern */]>;
1249 // scalar->vector promotion:
1250 def v16i8_i8: ORPromoteScalar<R8C>;
1251 def v8i16_i16: ORPromoteScalar<R16C>;
1252 def v4i32_i32: ORPromoteScalar<R32C>;
1253 def v2i64_i64: ORPromoteScalar<R64C>;
1254 def v4f32_f32: ORPromoteScalar<R32FP>;
1255 def v2f64_f64: ORPromoteScalar<R64FP>;
1257 // extract element 0:
1258 def i8_v16i8: ORExtractElt<R8C>;
1259 def i16_v8i16: ORExtractElt<R16C>;
1260 def i32_v4i32: ORExtractElt<R32C>;
1261 def i64_v2i64: ORExtractElt<R64C>;
1262 def f32_v4f32: ORExtractElt<R32FP>;
1263 def f64_v2f64: ORExtractElt<R64FP>;
1266 defm OR : BitwiseOr;
1268 // scalar->vector promotion patterns:
1269 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
1270 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
1272 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1273 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1275 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1276 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1278 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1279 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1281 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1282 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1284 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1285 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1287 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1289 def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)),
1290 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1292 def : Pat<(SPUextract_elt0_chained (v16i8 VECREG:$rA)),
1293 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1295 def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
1296 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1298 def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
1299 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1301 def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
1302 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1304 def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
1305 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1307 def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
1308 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1310 def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
1311 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1313 def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
1314 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1316 def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
1317 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1319 def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
1320 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1322 def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
1323 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1325 // ORC: Bitwise "or" with complement (c = a | ~b)
1327 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1328 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1329 IntegerOp, pattern>;
1331 class ORCVecInst<ValueType vectype>:
1332 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1333 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1334 (vnot (vectype VECREG:$rB))))]>;
1336 class ORCRegInst<RegisterClass rclass>:
1337 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1338 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1340 multiclass BitwiseOrComplement
1342 def v16i8: ORCVecInst<v16i8>;
1343 def v8i16: ORCVecInst<v8i16>;
1344 def v4i32: ORCVecInst<v4i32>;
1345 def v2i64: ORCVecInst<v2i64>;
1347 def r64: ORCRegInst<R64C>;
1348 def r32: ORCRegInst<R32C>;
1349 def r16: ORCRegInst<R16C>;
1350 def r8: ORCRegInst<R8C>;
1353 defm ORC : BitwiseOrComplement;
1355 // OR byte immediate
1356 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1357 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1358 IntegerOp, pattern>;
1360 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1361 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1362 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1363 (vectype immpred:$val)))]>;
1365 multiclass BitwiseOrByteImm
1367 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1369 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1370 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1373 defm ORBI : BitwiseOrByteImm;
1375 // Truncate i16 -> i8
1376 def ORBItrunc : ORBIInst<(outs R8C:$rT), (ins R16C:$rA, u10imm:$val),
1379 def : Pat<(trunc R16C:$rSrc),
1380 (ORBItrunc R16C:$rSrc, 0)>;
1382 // OR halfword immediate
1383 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1384 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1385 IntegerOp, pattern>;
1387 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1388 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1389 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1392 multiclass BitwiseOrHalfwordImm
1394 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1396 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1397 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1399 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1400 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1401 [(set R16C:$rT, (or (anyext R8C:$rA),
1402 i16ImmSExt10:$val))]>;
1405 defm ORHI : BitwiseOrHalfwordImm;
1407 // Truncate i32 -> i16
1408 def ORHItrunc : ORHIInst<(outs R16C:$rT), (ins R32C:$rA, u10imm:$val),
1411 def : Pat<(trunc R32C:$rSrc),
1412 (ORHItrunc R32C:$rSrc, 0)>;
1414 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1415 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1416 IntegerOp, pattern>;
1418 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1419 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1420 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1423 // Bitwise "or" with immediate
1424 multiclass BitwiseOrImm
1426 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1428 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1429 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1431 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1432 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1433 // infra "anyext 16->32" pattern.)
1434 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1435 [(set R32C:$rT, (or (anyext R16C:$rA),
1436 i32ImmSExt10:$val))]>;
1438 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1439 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1440 // infra "anyext 16->32" pattern.)
1441 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1442 [(set R32C:$rT, (or (anyext R8C:$rA),
1443 i32ImmSExt10:$val))]>;
1446 defm ORI : BitwiseOrImm;
1448 // Truncate i64 -> i32
1449 def ORItrunc : ORIInst<(outs R32C:$rT), (ins R64C:$rA, u10imm_i32:$val),
1452 def : Pat<(trunc R64C:$rSrc),
1453 (ORItrunc R64C:$rSrc, 0)>;
1455 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1456 // $rT[0], slots 1-3 are zeroed.
1458 // FIXME: Needs to match an intrinsic pattern.
1460 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1461 "orx\t$rT, $rA, $rB", IntegerOp,
1466 class XORInst<dag OOL, dag IOL, list<dag> pattern> :
1467 RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB",
1468 IntegerOp, pattern>;
1470 class XORVecInst<ValueType vectype>:
1471 XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1472 [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA),
1473 (vectype VECREG:$rB)))]>;
1475 class XORRegInst<RegisterClass rclass>:
1476 XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1477 [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>;
1479 multiclass BitwiseExclusiveOr
1481 def v16i8: XORVecInst<v16i8>;
1482 def v8i16: XORVecInst<v8i16>;
1483 def v4i32: XORVecInst<v4i32>;
1484 def v2i64: XORVecInst<v2i64>;
1486 def r128: XORRegInst<GPRC>;
1487 def r64: XORRegInst<R64C>;
1488 def r32: XORRegInst<R32C>;
1489 def r16: XORRegInst<R16C>;
1490 def r8: XORRegInst<R8C>;
1492 // Special forms for floating point instructions.
1493 // fneg and fabs require bitwise logical ops to manipulate the sign bit.
1495 def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1496 [/* no pattern */]>;
1498 def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1499 [/* no pattern */]>;
1501 def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1502 [/* no pattern, see fneg{32,64} */]>;
1505 defm XOR : BitwiseExclusiveOr;
1507 //==----------------------------------------------------------
1509 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1510 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1511 IntegerOp, pattern>;
1513 multiclass XorByteImm
1516 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1517 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1520 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1521 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1524 defm XORBI : XorByteImm;
1527 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1528 "xorhi\t$rT, $rA, $val", IntegerOp,
1529 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1530 v8i16SExt10Imm:$val))]>;
1533 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1534 "xorhi\t$rT, $rA, $val", IntegerOp,
1535 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1538 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
1539 "xori\t$rT, $rA, $val", IntegerOp,
1540 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1541 v4i32SExt10Imm:$val))]>;
1544 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1545 "xori\t$rT, $rA, $val", IntegerOp,
1546 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1550 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1551 "nand\t$rT, $rA, $rB", IntegerOp,
1552 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1553 (v16i8 VECREG:$rB))))]>;
1556 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1557 "nand\t$rT, $rA, $rB", IntegerOp,
1558 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1559 (v8i16 VECREG:$rB))))]>;
1562 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1563 "nand\t$rT, $rA, $rB", IntegerOp,
1564 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1565 (v4i32 VECREG:$rB))))]>;
1568 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1569 "nand\t$rT, $rA, $rB", IntegerOp,
1570 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1573 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1574 "nand\t$rT, $rA, $rB", IntegerOp,
1575 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1578 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1579 "nand\t$rT, $rA, $rB", IntegerOp,
1580 [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
1584 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1585 "nor\t$rT, $rA, $rB", IntegerOp,
1586 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1587 (v16i8 VECREG:$rB))))]>;
1590 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1591 "nor\t$rT, $rA, $rB", IntegerOp,
1592 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1593 (v8i16 VECREG:$rB))))]>;
1596 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1597 "nor\t$rT, $rA, $rB", IntegerOp,
1598 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1599 (v4i32 VECREG:$rB))))]>;
1602 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1603 "nor\t$rT, $rA, $rB", IntegerOp,
1604 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1607 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1608 "nor\t$rT, $rA, $rB", IntegerOp,
1609 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1612 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1613 "nor\t$rT, $rA, $rB", IntegerOp,
1614 [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
1617 class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
1618 RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC",
1619 IntegerOp, pattern>;
1621 class SELBVecInst<ValueType vectype>:
1622 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1623 [(set (vectype VECREG:$rT),
1624 (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)),
1625 (and (vnot (vectype VECREG:$rC)),
1626 (vectype VECREG:$rA))))]>;
1628 class SELBRegInst<RegisterClass rclass>:
1629 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
1631 (or (and rclass:$rA, rclass:$rC),
1632 (and rclass:$rB, (not rclass:$rC))))]>;
1634 multiclass SelectBits
1636 def v16i8: SELBVecInst<v16i8>;
1637 def v8i16: SELBVecInst<v8i16>;
1638 def v4i32: SELBVecInst<v4i32>;
1639 def v2i64: SELBVecInst<v2i64>;
1641 def r128: SELBRegInst<GPRC>;
1642 def r64: SELBRegInst<R64C>;
1643 def r32: SELBRegInst<R32C>;
1644 def r16: SELBRegInst<R16C>;
1645 def r8: SELBRegInst<R8C>;
1648 defm SELB : SelectBits;
1650 class SPUselbPat<ValueType vectype, SPUInstr inst>:
1651 Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)),
1652 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1654 def : SPUselbPat<v16i8, SELBv16i8>;
1655 def : SPUselbPat<v8i16, SELBv8i16>;
1656 def : SPUselbPat<v4i32, SELBv4i32>;
1657 def : SPUselbPat<v2i64, SELBv2i64>;
1659 class SelectConditional<RegisterClass rclass, SPUInstr inst>:
1660 Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse),
1661 (inst rclass:$rFalse, rclass:$rTrue, rclass:$rCond)>;
1663 def : SelectConditional<R32C, SELBr32>;
1664 def : SelectConditional<R16C, SELBr16>;
1665 def : SelectConditional<R8C, SELBr8>;
1667 // EQV: Equivalence (1 for each same bit, otherwise 0)
1669 // Note: There are a lot of ways to match this bit operator and these patterns
1670 // attempt to be as exhaustive as possible.
1672 class EQVInst<dag OOL, dag IOL, list<dag> pattern>:
1673 RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB",
1674 IntegerOp, pattern>;
1676 class EQVVecInst<ValueType vectype>:
1677 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1678 [(set (vectype VECREG:$rT),
1679 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1680 (and (vnot (vectype VECREG:$rA)),
1681 (vnot (vectype VECREG:$rB)))))]>;
1683 class EQVRegInst<RegisterClass rclass>:
1684 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1685 [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB),
1686 (and (not rclass:$rA), (not rclass:$rB))))]>;
1688 class EQVVecPattern1<ValueType vectype>:
1689 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1690 [(set (vectype VECREG:$rT),
1691 (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>;
1693 class EQVRegPattern1<RegisterClass rclass>:
1694 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1695 [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>;
1697 class EQVVecPattern2<ValueType vectype>:
1698 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1699 [(set (vectype VECREG:$rT),
1700 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1701 (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>;
1703 class EQVRegPattern2<RegisterClass rclass>:
1704 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1706 (or (and rclass:$rA, rclass:$rB),
1707 (not (or rclass:$rA, rclass:$rB))))]>;
1709 class EQVVecPattern3<ValueType vectype>:
1710 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1711 [(set (vectype VECREG:$rT),
1712 (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>;
1714 class EQVRegPattern3<RegisterClass rclass>:
1715 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1716 [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>;
1718 multiclass BitEquivalence
1720 def v16i8: EQVVecInst<v16i8>;
1721 def v8i16: EQVVecInst<v8i16>;
1722 def v4i32: EQVVecInst<v4i32>;
1723 def v2i64: EQVVecInst<v2i64>;
1725 def v16i8_1: EQVVecPattern1<v16i8>;
1726 def v8i16_1: EQVVecPattern1<v8i16>;
1727 def v4i32_1: EQVVecPattern1<v4i32>;
1728 def v2i64_1: EQVVecPattern1<v2i64>;
1730 def v16i8_2: EQVVecPattern2<v16i8>;
1731 def v8i16_2: EQVVecPattern2<v8i16>;
1732 def v4i32_2: EQVVecPattern2<v4i32>;
1733 def v2i64_2: EQVVecPattern2<v2i64>;
1735 def v16i8_3: EQVVecPattern3<v16i8>;
1736 def v8i16_3: EQVVecPattern3<v8i16>;
1737 def v4i32_3: EQVVecPattern3<v4i32>;
1738 def v2i64_3: EQVVecPattern3<v2i64>;
1740 def r128: EQVRegInst<GPRC>;
1741 def r64: EQVRegInst<R64C>;
1742 def r32: EQVRegInst<R32C>;
1743 def r16: EQVRegInst<R16C>;
1744 def r8: EQVRegInst<R8C>;
1746 def r128_1: EQVRegPattern1<GPRC>;
1747 def r64_1: EQVRegPattern1<R64C>;
1748 def r32_1: EQVRegPattern1<R32C>;
1749 def r16_1: EQVRegPattern1<R16C>;
1750 def r8_1: EQVRegPattern1<R8C>;
1752 def r128_2: EQVRegPattern2<GPRC>;
1753 def r64_2: EQVRegPattern2<R64C>;
1754 def r32_2: EQVRegPattern2<R32C>;
1755 def r16_2: EQVRegPattern2<R16C>;
1756 def r8_2: EQVRegPattern2<R8C>;
1758 def r128_3: EQVRegPattern3<GPRC>;
1759 def r64_3: EQVRegPattern3<R64C>;
1760 def r32_3: EQVRegPattern3<R32C>;
1761 def r16_3: EQVRegPattern3<R16C>;
1762 def r8_3: EQVRegPattern3<R8C>;
1765 defm EQV: BitEquivalence;
1767 //===----------------------------------------------------------------------===//
1768 // Vector shuffle...
1769 //===----------------------------------------------------------------------===//
1770 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
1771 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
1772 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
1773 // the SPUISD::SHUFB opcode.
1774 //===----------------------------------------------------------------------===//
1776 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
1777 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
1778 IntegerOp, pattern>;
1780 class SHUFBVecInst<ValueType vectype>:
1781 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1782 [(set (vectype VECREG:$rT), (SPUshuffle (vectype VECREG:$rA),
1783 (vectype VECREG:$rB),
1784 (vectype VECREG:$rC)))]>;
1786 // It's this pattern that's probably the most useful, since SPUISelLowering
1787 // methods create a v16i8 vector for $rC:
1788 class SHUFBVecPat1<ValueType vectype, ValueType masktype, SPUInstr inst>:
1789 Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB),
1790 (masktype VECREG:$rC)),
1791 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1793 multiclass ShuffleBytes
1795 def v16i8 : SHUFBVecInst<v16i8>;
1796 def v8i16 : SHUFBVecInst<v8i16>;
1797 def v4i32 : SHUFBVecInst<v4i32>;
1798 def v2i64 : SHUFBVecInst<v2i64>;
1800 def v4f32 : SHUFBVecInst<v4f32>;
1801 def v2f64 : SHUFBVecInst<v2f64>;
1804 defm SHUFB : ShuffleBytes;
1806 // Shuffle mask is a v16i8 vector
1807 def : SHUFBVecPat1<v8i16, v16i8, SHUFBv16i8>;
1808 def : SHUFBVecPat1<v4i32, v16i8, SHUFBv16i8>;
1809 def : SHUFBVecPat1<v2i64, v16i8, SHUFBv16i8>;
1810 def : SHUFBVecPat1<v4f32, v16i8, SHUFBv16i8>;
1811 def : SHUFBVecPat1<v2f64, v16i8, SHUFBv16i8>;
1813 // Shuffle mask is a v4i32 vector:
1814 def : SHUFBVecPat1<v8i16, v4i32, SHUFBv4i32>;
1815 def : SHUFBVecPat1<v4i32, v4i32, SHUFBv4i32>;
1816 def : SHUFBVecPat1<v2i64, v4i32, SHUFBv4i32>;
1817 def : SHUFBVecPat1<v4f32, v4i32, SHUFBv4i32>;
1818 def : SHUFBVecPat1<v2f64, v4i32, SHUFBv4i32>;
1820 //===----------------------------------------------------------------------===//
1821 // Shift and rotate group:
1822 //===----------------------------------------------------------------------===//
1824 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
1825 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
1826 RotateShift, pattern>;
1828 class SHLHVecInst<ValueType vectype>:
1829 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1830 [(set (vectype VECREG:$rT),
1831 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
1833 // $rB gets promoted to 32-bit register type when confronted with
1834 // this llvm assembly code:
1836 // define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
1837 // %A = shl i16 %arg1, %arg2
1841 multiclass ShiftLeftHalfword
1843 def v8i16: SHLHVecInst<v8i16>;
1844 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1845 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1846 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1847 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1850 defm SHLH : ShiftLeftHalfword;
1852 //===----------------------------------------------------------------------===//
1854 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
1855 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
1856 RotateShift, pattern>;
1858 class SHLHIVecInst<ValueType vectype>:
1859 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1860 [(set (vectype VECREG:$rT),
1861 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
1863 multiclass ShiftLeftHalfwordImm
1865 def v8i16: SHLHIVecInst<v8i16>;
1866 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
1867 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
1870 defm SHLHI : ShiftLeftHalfwordImm;
1872 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
1873 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
1875 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
1876 (SHLHIr16 R16C:$rA, uimm7:$val)>;
1878 //===----------------------------------------------------------------------===//
1880 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
1881 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
1882 RotateShift, pattern>;
1884 multiclass ShiftLeftWord
1887 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1888 [(set (v4i32 VECREG:$rT),
1889 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
1891 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1892 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
1895 defm SHL: ShiftLeftWord;
1897 //===----------------------------------------------------------------------===//
1899 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
1900 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
1901 RotateShift, pattern>;
1903 multiclass ShiftLeftWordImm
1906 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1907 [(set (v4i32 VECREG:$rT),
1908 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
1911 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
1912 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
1915 defm SHLI : ShiftLeftWordImm;
1917 //===----------------------------------------------------------------------===//
1918 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
1919 // register) to the left. Vector form is here to ensure type correctness.
1921 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
1922 // of 7 bits is actually possible.
1924 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
1925 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
1926 // bytes with SHLQBY.
1928 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
1929 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
1930 RotateShift, pattern>;
1932 class SHLQBIVecInst<ValueType vectype>:
1933 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1934 [(set (vectype VECREG:$rT),
1935 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
1937 multiclass ShiftLeftQuadByBits
1939 def v16i8: SHLQBIVecInst<v16i8>;
1940 def v8i16: SHLQBIVecInst<v8i16>;
1941 def v4i32: SHLQBIVecInst<v4i32>;
1942 def v2i64: SHLQBIVecInst<v2i64>;
1945 defm SHLQBI : ShiftLeftQuadByBits;
1947 // See note above on SHLQBI. In this case, the predicate actually does then
1948 // enforcement, whereas with SHLQBI, we have to "take it on faith."
1949 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
1950 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
1951 RotateShift, pattern>;
1953 class SHLQBIIVecInst<ValueType vectype>:
1954 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1955 [(set (vectype VECREG:$rT),
1956 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
1958 multiclass ShiftLeftQuadByBitsImm
1960 def v16i8 : SHLQBIIVecInst<v16i8>;
1961 def v8i16 : SHLQBIIVecInst<v8i16>;
1962 def v4i32 : SHLQBIIVecInst<v4i32>;
1963 def v2i64 : SHLQBIIVecInst<v2i64>;
1966 defm SHLQBII : ShiftLeftQuadByBitsImm;
1968 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
1969 // not by bits. See notes above on SHLQBI.
1971 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
1972 RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB",
1973 RotateShift, pattern>;
1975 class SHLQBYVecInst<ValueType vectype>:
1976 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1977 [(set (vectype VECREG:$rT),
1978 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
1980 multiclass ShiftLeftQuadBytes
1982 def v16i8: SHLQBYVecInst<v16i8>;
1983 def v8i16: SHLQBYVecInst<v8i16>;
1984 def v4i32: SHLQBYVecInst<v4i32>;
1985 def v2i64: SHLQBYVecInst<v2i64>;
1986 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
1987 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
1990 defm SHLQBY: ShiftLeftQuadBytes;
1992 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
1993 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
1994 RotateShift, pattern>;
1996 class SHLQBYIVecInst<ValueType vectype>:
1997 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1998 [(set (vectype VECREG:$rT),
1999 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2001 multiclass ShiftLeftQuadBytesImm
2003 def v16i8: SHLQBYIVecInst<v16i8>;
2004 def v8i16: SHLQBYIVecInst<v8i16>;
2005 def v4i32: SHLQBYIVecInst<v4i32>;
2006 def v2i64: SHLQBYIVecInst<v2i64>;
2007 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
2009 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
2012 defm SHLQBYI : ShiftLeftQuadBytesImm;
2014 // Special form for truncating i64 to i32:
2015 def SHLQBYItrunc64: SHLQBYIInst<(outs R32C:$rT), (ins R64C:$rA, u7imm_i32:$val),
2016 [/* no pattern, see below */]>;
2018 def : Pat<(trunc R64C:$rSrc),
2019 (SHLQBYItrunc64 R64C:$rSrc, 4)>;
2021 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2023 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2024 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
2025 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
2026 RotateShift, pattern>;
2028 class ROTHVecInst<ValueType vectype>:
2029 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2030 [(set (vectype VECREG:$rT),
2031 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
2033 class ROTHRegInst<RegisterClass rclass>:
2034 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2035 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
2037 multiclass RotateLeftHalfword
2039 def v8i16: ROTHVecInst<v8i16>;
2040 def r16: ROTHRegInst<R16C>;
2043 defm ROTH: RotateLeftHalfword;
2045 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2046 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2048 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2049 // Rotate halfword, immediate:
2050 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2051 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
2052 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
2053 RotateShift, pattern>;
2055 class ROTHIVecInst<ValueType vectype>:
2056 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2057 [(set (vectype VECREG:$rT),
2058 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
2060 multiclass RotateLeftHalfwordImm
2062 def v8i16: ROTHIVecInst<v8i16>;
2063 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2064 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2065 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2066 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2069 defm ROTHI: RotateLeftHalfwordImm;
2071 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
2072 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2074 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2076 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2078 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
2079 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
2080 RotateShift, pattern>;
2082 class ROTVecInst<ValueType vectype>:
2083 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2084 [(set (vectype VECREG:$rT),
2085 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
2087 class ROTRegInst<RegisterClass rclass>:
2088 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2090 (rotl rclass:$rA, R32C:$rB))]>;
2092 multiclass RotateLeftWord
2094 def v4i32: ROTVecInst<v4i32>;
2095 def r32: ROTRegInst<R32C>;
2098 defm ROT: RotateLeftWord;
2100 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2102 def ROTr32_r16_anyext:
2103 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2104 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2106 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
2107 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2109 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
2110 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2112 def ROTr32_r8_anyext:
2113 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2114 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2116 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
2117 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2119 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
2120 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2122 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2123 // Rotate word, immediate
2124 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2126 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
2127 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
2128 RotateShift, pattern>;
2130 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
2131 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2132 [(set (vectype VECREG:$rT),
2133 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2135 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2136 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2137 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2139 multiclass RotateLeftWordImm
2141 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2142 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
2143 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
2145 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
2146 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
2147 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
2150 defm ROTI : RotateLeftWordImm;
2152 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2153 // Rotate quad by byte (count)
2154 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2156 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2157 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2158 RotateShift, pattern>;
2160 class ROTQBYVecInst<ValueType vectype>:
2161 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2162 [(set (vectype VECREG:$rT),
2163 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2165 multiclass RotateQuadLeftByBytes
2167 def v16i8: ROTQBYVecInst<v16i8>;
2168 def v8i16: ROTQBYVecInst<v8i16>;
2169 def v4i32: ROTQBYVecInst<v4i32>;
2170 def v2i64: ROTQBYVecInst<v2i64>;
2173 defm ROTQBY: RotateQuadLeftByBytes;
2175 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
2176 (ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
2177 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
2178 (ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
2179 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
2180 (ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
2181 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
2182 (ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
2184 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2185 // Rotate quad by byte (count), immediate
2186 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2188 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2189 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2190 RotateShift, pattern>;
2192 class ROTQBYIVecInst<ValueType vectype>:
2193 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2194 [(set (vectype VECREG:$rT),
2195 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2197 multiclass RotateQuadByBytesImm
2199 def v16i8: ROTQBYIVecInst<v16i8>;
2200 def v8i16: ROTQBYIVecInst<v8i16>;
2201 def v4i32: ROTQBYIVecInst<v4i32>;
2202 def v2i64: ROTQBYIVecInst<v2i64>;
2205 defm ROTQBYI: RotateQuadByBytesImm;
2207 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2208 (ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
2209 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2210 (ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
2211 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2212 (ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
2213 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
2214 (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
2216 // See ROTQBY note above.
2217 class ROTQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2218 RI7Form<0b00110011100, OOL, IOL,
2219 "rotqbybi\t$rT, $rA, $shift",
2220 RotateShift, pattern>;
2222 class ROTQBYBIVecInst<ValueType vectype, RegisterClass rclass>:
2223 ROTQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, rclass:$shift),
2224 [(set (vectype VECREG:$rT),
2225 (SPUrotbytes_left_bits (vectype VECREG:$rA), rclass:$shift))]>;
2227 multiclass RotateQuadByBytesByBitshift {
2228 def v16i8_r32: ROTQBYBIVecInst<v16i8, R32C>;
2229 def v8i16_r32: ROTQBYBIVecInst<v8i16, R32C>;
2230 def v4i32_r32: ROTQBYBIVecInst<v4i32, R32C>;
2231 def v2i64_r32: ROTQBYBIVecInst<v2i64, R32C>;
2234 defm ROTQBYBI : RotateQuadByBytesByBitshift;
2236 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2237 // See ROTQBY note above.
2239 // Assume that the user of this instruction knows to shift the rotate count
2241 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2243 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2244 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2245 RotateShift, pattern>;
2247 class ROTQBIVecInst<ValueType vectype>:
2248 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2249 [/* no pattern yet */]>;
2251 class ROTQBIRegInst<RegisterClass rclass>:
2252 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2253 [/* no pattern yet */]>;
2255 multiclass RotateQuadByBitCount
2257 def v16i8: ROTQBIVecInst<v16i8>;
2258 def v8i16: ROTQBIVecInst<v8i16>;
2259 def v4i32: ROTQBIVecInst<v4i32>;
2260 def v2i64: ROTQBIVecInst<v2i64>;
2262 def r128: ROTQBIRegInst<GPRC>;
2263 def r64: ROTQBIRegInst<R64C>;
2266 defm ROTQBI: RotateQuadByBitCount;
2268 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2269 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2270 RotateShift, pattern>;
2272 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2274 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2275 [/* no pattern yet */]>;
2277 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2279 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2280 [/* no pattern yet */]>;
2282 multiclass RotateQuadByBitCountImm
2284 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2285 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2286 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2287 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2289 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2290 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2293 defm ROTQBII : RotateQuadByBitCountImm;
2295 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2296 // ROTHM v8i16 form:
2297 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2298 // so this only matches a synthetically generated/lowered code
2300 // NOTE(2): $rB must be negated before the right rotate!
2301 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2303 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2304 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2305 RotateShift, pattern>;
2308 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2309 [/* see patterns below - $rB must be negated */]>;
2311 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2312 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2314 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2315 (ROTHMv8i16 VECREG:$rA,
2316 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2318 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2319 (ROTHMv8i16 VECREG:$rA,
2320 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2322 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2323 // Note: This instruction doesn't match a pattern because rB must be negated
2324 // for the instruction to work. Thus, the pattern below the instruction!
2327 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2328 [/* see patterns below - $rB must be negated! */]>;
2330 def : Pat<(srl R16C:$rA, R32C:$rB),
2331 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2333 def : Pat<(srl R16C:$rA, R16C:$rB),
2335 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2337 def : Pat<(srl R16C:$rA, R8C:$rB),
2339 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2341 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2342 // that the immediate can be complemented, so that the user doesn't have to
2345 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2346 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2347 RotateShift, pattern>;
2350 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2351 [/* no pattern */]>;
2353 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2354 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2356 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2357 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2359 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2360 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2363 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2364 [/* no pattern */]>;
2366 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2367 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2369 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2370 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2372 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2373 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2375 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2376 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2377 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2378 RotateShift, pattern>;
2381 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2382 [/* see patterns below - $rB must be negated */]>;
2384 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
2385 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2387 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
2388 (ROTMv4i32 VECREG:$rA,
2389 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2391 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
2392 (ROTMv4i32 VECREG:$rA,
2393 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2396 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2397 [/* see patterns below - $rB must be negated */]>;
2399 def : Pat<(srl R32C:$rA, R32C:$rB),
2400 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2402 def : Pat<(srl R32C:$rA, R16C:$rB),
2404 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2406 def : Pat<(srl R32C:$rA, R8C:$rB),
2408 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2410 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2412 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2413 "rotmi\t$rT, $rA, $val", RotateShift,
2414 [(set (v4i32 VECREG:$rT),
2415 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2417 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
2418 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2420 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
2421 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2423 // ROTMI r32 form: know how to complement the immediate value.
2425 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2426 "rotmi\t$rT, $rA, $val", RotateShift,
2427 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2429 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2430 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2432 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2433 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2435 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2436 // ROTQMBYvec: This is a vector form merely so that when used in an
2437 // instruction pattern, type checking will succeed. This instruction assumes
2438 // that the user knew to negate $rB.
2440 // Using the SPUrotquad_rz_bytes target-specific DAG node, the patterns
2441 // ensure that $rB is negated.
2442 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2444 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2445 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2446 RotateShift, pattern>;
2448 class ROTQMBYVecInst<ValueType vectype>:
2449 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2450 [/* no pattern, $rB must be negated */]>;
2452 class ROTQMBYRegInst<RegisterClass rclass>:
2453 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2455 (SPUrotquad_rz_bytes rclass:$rA, R32C:$rB))]>;
2457 multiclass RotateQuadBytes
2459 def v16i8: ROTQMBYVecInst<v16i8>;
2460 def v8i16: ROTQMBYVecInst<v8i16>;
2461 def v4i32: ROTQMBYVecInst<v4i32>;
2462 def v2i64: ROTQMBYVecInst<v2i64>;
2464 def r128: ROTQMBYRegInst<GPRC>;
2465 def r64: ROTQMBYRegInst<R64C>;
2468 defm ROTQMBY : RotateQuadBytes;
2470 def : Pat<(SPUrotquad_rz_bytes (v16i8 VECREG:$rA), R32C:$rB),
2471 (ROTQMBYv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2472 def : Pat<(SPUrotquad_rz_bytes (v8i16 VECREG:$rA), R32C:$rB),
2473 (ROTQMBYv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2474 def : Pat<(SPUrotquad_rz_bytes (v4i32 VECREG:$rA), R32C:$rB),
2475 (ROTQMBYv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2476 def : Pat<(SPUrotquad_rz_bytes (v2i64 VECREG:$rA), R32C:$rB),
2477 (ROTQMBYv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2478 def : Pat<(SPUrotquad_rz_bytes GPRC:$rA, R32C:$rB),
2479 (ROTQMBYr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2480 def : Pat<(SPUrotquad_rz_bytes R64C:$rA, R32C:$rB),
2481 (ROTQMBYr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2483 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2484 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2485 RotateShift, pattern>;
2487 class ROTQMBYIVecInst<ValueType vectype>:
2488 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2489 [(set (vectype VECREG:$rT),
2490 (SPUrotquad_rz_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2492 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2493 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2495 (SPUrotquad_rz_bytes rclass:$rA, (inttype pred:$val)))]>;
2497 multiclass RotateQuadBytesImm
2499 def v16i8: ROTQMBYIVecInst<v16i8>;
2500 def v8i16: ROTQMBYIVecInst<v8i16>;
2501 def v4i32: ROTQMBYIVecInst<v4i32>;
2502 def v2i64: ROTQMBYIVecInst<v2i64>;
2504 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2505 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2508 defm ROTQMBYI : RotateQuadBytesImm;
2510 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2511 // Rotate right and mask by bit count
2512 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2514 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2515 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2516 RotateShift, pattern>;
2518 class ROTQMBYBIVecInst<ValueType vectype>:
2519 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2520 [/* no pattern, intrinsic? */]>;
2522 multiclass RotateMaskQuadByBitCount
2524 def v16i8: ROTQMBYBIVecInst<v16i8>;
2525 def v8i16: ROTQMBYBIVecInst<v8i16>;
2526 def v4i32: ROTQMBYBIVecInst<v4i32>;
2527 def v2i64: ROTQMBYBIVecInst<v2i64>;
2530 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2532 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2533 // Rotate quad and mask by bits
2534 // Note that the rotate amount has to be negated
2535 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2537 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2538 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2539 RotateShift, pattern>;
2541 class ROTQMBIVecInst<ValueType vectype>:
2542 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2543 [/* no pattern */]>;
2545 class ROTQMBIRegInst<RegisterClass rclass>:
2546 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2547 [/* no pattern */]>;
2549 multiclass RotateMaskQuadByBits
2551 def v16i8: ROTQMBIVecInst<v16i8>;
2552 def v8i16: ROTQMBIVecInst<v8i16>;
2553 def v4i32: ROTQMBIVecInst<v4i32>;
2554 def v2i64: ROTQMBIVecInst<v2i64>;
2556 def r128: ROTQMBIRegInst<GPRC>;
2557 def r64: ROTQMBIRegInst<R64C>;
2560 defm ROTQMBI: RotateMaskQuadByBits;
2562 def : Pat<(SPUrotquad_rz_bits (v16i8 VECREG:$rA), R32C:$rB),
2563 (ROTQMBIv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2564 def : Pat<(SPUrotquad_rz_bits (v8i16 VECREG:$rA), R32C:$rB),
2565 (ROTQMBIv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2566 def : Pat<(SPUrotquad_rz_bits (v4i32 VECREG:$rA), R32C:$rB),
2567 (ROTQMBIv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2568 def : Pat<(SPUrotquad_rz_bits (v2i64 VECREG:$rA), R32C:$rB),
2569 (ROTQMBIv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2570 def : Pat<(SPUrotquad_rz_bits GPRC:$rA, R32C:$rB),
2571 (ROTQMBIr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2572 def : Pat<(SPUrotquad_rz_bits R64C:$rA, R32C:$rB),
2573 (ROTQMBIr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2575 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2576 // Rotate quad and mask by bits, immediate
2577 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2579 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2580 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2581 RotateShift, pattern>;
2583 class ROTQMBIIVecInst<ValueType vectype>:
2584 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2585 [(set (vectype VECREG:$rT),
2586 (SPUrotquad_rz_bits (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2588 class ROTQMBIIRegInst<RegisterClass rclass>:
2589 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2591 (SPUrotquad_rz_bits rclass:$rA, (i32 uimm7:$val)))]>;
2593 multiclass RotateMaskQuadByBitsImm
2595 def v16i8: ROTQMBIIVecInst<v16i8>;
2596 def v8i16: ROTQMBIIVecInst<v8i16>;
2597 def v4i32: ROTQMBIIVecInst<v4i32>;
2598 def v2i64: ROTQMBIIVecInst<v2i64>;
2600 def r128: ROTQMBIIRegInst<GPRC>;
2601 def r64: ROTQMBIIRegInst<R64C>;
2604 defm ROTQMBII: RotateMaskQuadByBitsImm;
2606 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2607 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2610 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2611 "rotmah\t$rT, $rA, $rB", RotateShift,
2612 [/* see patterns below - $rB must be negated */]>;
2614 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2615 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2617 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2618 (ROTMAHv8i16 VECREG:$rA,
2619 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2621 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2622 (ROTMAHv8i16 VECREG:$rA,
2623 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2626 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2627 "rotmah\t$rT, $rA, $rB", RotateShift,
2628 [/* see patterns below - $rB must be negated */]>;
2630 def : Pat<(sra R16C:$rA, R32C:$rB),
2631 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2633 def : Pat<(sra R16C:$rA, R16C:$rB),
2634 (ROTMAHr16 R16C:$rA,
2635 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2637 def : Pat<(sra R16C:$rA, R8C:$rB),
2638 (ROTMAHr16 R16C:$rA,
2639 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2642 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2643 "rotmahi\t$rT, $rA, $val", RotateShift,
2644 [(set (v8i16 VECREG:$rT),
2645 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2647 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2648 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2650 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2651 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2654 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2655 "rotmahi\t$rT, $rA, $val", RotateShift,
2656 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2658 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2659 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2661 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2662 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2665 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2666 "rotma\t$rT, $rA, $rB", RotateShift,
2667 [/* see patterns below - $rB must be negated */]>;
2669 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2670 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2672 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2673 (ROTMAv4i32 (v4i32 VECREG:$rA),
2674 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2676 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2677 (ROTMAv4i32 (v4i32 VECREG:$rA),
2678 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2681 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2682 "rotma\t$rT, $rA, $rB", RotateShift,
2683 [/* see patterns below - $rB must be negated */]>;
2685 def : Pat<(sra R32C:$rA, R32C:$rB),
2686 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2688 def : Pat<(sra R32C:$rA, R16C:$rB),
2690 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2692 def : Pat<(sra R32C:$rA, R8C:$rB),
2694 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2696 class ROTMAIInst<dag OOL, dag IOL, list<dag> pattern>:
2697 RRForm<0b01011110000, OOL, IOL,
2698 "rotmai\t$rT, $rA, $val",
2699 RotateShift, pattern>;
2701 class ROTMAIVecInst<ValueType vectype, Operand intop, ValueType inttype>:
2702 ROTMAIInst<(outs VECREG:$rT), (ins VECREG:$rA, intop:$val),
2703 [(set (vectype VECREG:$rT),
2704 (SPUvec_sra VECREG:$rA, (inttype uimm7:$val)))]>;
2706 class ROTMAIRegInst<RegisterClass rclass, Operand intop, ValueType inttype>:
2707 ROTMAIInst<(outs rclass:$rT), (ins rclass:$rA, intop:$val),
2708 [(set rclass:$rT, (sra rclass:$rA, (inttype uimm7:$val)))]>;
2710 multiclass RotateMaskAlgebraicImm {
2711 def v2i64_i32 : ROTMAIVecInst<v2i64, rotNeg7imm, i32>;
2712 def v4i32_i32 : ROTMAIVecInst<v4i32, rotNeg7imm, i32>;
2713 def r64_i32 : ROTMAIRegInst<R64C, rotNeg7imm, i32>;
2714 def r32_i32 : ROTMAIRegInst<R32C, rotNeg7imm, i32>;
2717 defm ROTMAI : RotateMaskAlgebraicImm;
2719 //===----------------------------------------------------------------------===//
2720 // Branch and conditionals:
2721 //===----------------------------------------------------------------------===//
2723 let isTerminator = 1, isBarrier = 1 in {
2724 // Halt If Equal (r32 preferred slot only, no vector form)
2726 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2727 "heq\t$rA, $rB", BranchResolv,
2728 [/* no pattern to match */]>;
2731 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2732 "heqi\t$rA, $val", BranchResolv,
2733 [/* no pattern to match */]>;
2735 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2736 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2738 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2739 "hgt\t$rA, $rB", BranchResolv,
2740 [/* no pattern to match */]>;
2743 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2744 "hgti\t$rA, $val", BranchResolv,
2745 [/* no pattern to match */]>;
2748 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2749 "hlgt\t$rA, $rB", BranchResolv,
2750 [/* no pattern to match */]>;
2753 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2754 "hlgti\t$rA, $val", BranchResolv,
2755 [/* no pattern to match */]>;
2758 //------------------------------------------------------------------------
2759 // Comparison operators:
2760 //------------------------------------------------------------------------
2762 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
2763 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
2766 multiclass CmpEqualByte
2769 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2770 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2771 (v8i16 VECREG:$rB)))]>;
2774 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2775 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
2778 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
2779 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
2782 multiclass CmpEqualByteImm
2785 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2786 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
2787 v16i8SExt8Imm:$val))]>;
2789 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2790 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
2793 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
2794 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
2797 multiclass CmpEqualHalfword
2799 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2800 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2801 (v8i16 VECREG:$rB)))]>;
2803 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2804 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
2807 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
2808 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
2811 multiclass CmpEqualHalfwordImm
2813 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2814 [(set (v8i16 VECREG:$rT),
2815 (seteq (v8i16 VECREG:$rA),
2816 (v8i16 v8i16SExt10Imm:$val)))]>;
2817 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2818 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
2821 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
2822 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
2825 multiclass CmpEqualWord
2827 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2828 [(set (v4i32 VECREG:$rT),
2829 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2831 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2832 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2835 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
2836 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
2839 multiclass CmpEqualWordImm
2841 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2842 [(set (v4i32 VECREG:$rT),
2843 (seteq (v4i32 VECREG:$rA),
2844 (v4i32 v4i32SExt16Imm:$val)))]>;
2846 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2847 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2850 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2851 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
2854 multiclass CmpGtrByte
2857 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2858 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2859 (v8i16 VECREG:$rB)))]>;
2862 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2863 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
2866 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2867 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
2870 multiclass CmpGtrByteImm
2873 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2874 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
2875 v16i8SExt8Imm:$val))]>;
2877 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2878 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
2881 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2882 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
2885 multiclass CmpGtrHalfword
2887 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2888 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2889 (v8i16 VECREG:$rB)))]>;
2891 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2892 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
2895 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2896 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
2899 multiclass CmpGtrHalfwordImm
2901 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2902 [(set (v8i16 VECREG:$rT),
2903 (setgt (v8i16 VECREG:$rA),
2904 (v8i16 v8i16SExt10Imm:$val)))]>;
2905 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2906 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
2909 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
2910 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
2913 multiclass CmpGtrWord
2915 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2916 [(set (v4i32 VECREG:$rT),
2917 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2919 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2920 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
2923 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2924 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
2927 multiclass CmpGtrWordImm
2929 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2930 [(set (v4i32 VECREG:$rT),
2931 (setgt (v4i32 VECREG:$rA),
2932 (v4i32 v4i32SExt16Imm:$val)))]>;
2934 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2935 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
2938 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2939 RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB",
2942 multiclass CmpLGtrByte
2945 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2946 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2947 (v8i16 VECREG:$rB)))]>;
2950 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2951 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
2954 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2955 RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val",
2958 multiclass CmpLGtrByteImm
2961 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2962 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
2963 v16i8SExt8Imm:$val))]>;
2965 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2966 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
2969 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2970 RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB",
2973 multiclass CmpLGtrHalfword
2975 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2976 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2977 (v8i16 VECREG:$rB)))]>;
2979 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2980 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
2983 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2984 RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val",
2987 multiclass CmpLGtrHalfwordImm
2989 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2990 [(set (v8i16 VECREG:$rT),
2991 (setugt (v8i16 VECREG:$rA),
2992 (v8i16 v8i16SExt10Imm:$val)))]>;
2993 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2994 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
2997 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
2998 RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB",
3001 multiclass CmpLGtrWord
3003 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3004 [(set (v4i32 VECREG:$rT),
3005 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3007 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3008 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
3011 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
3012 RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val",
3015 multiclass CmpLGtrWordImm
3017 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3018 [(set (v4i32 VECREG:$rT),
3019 (setugt (v4i32 VECREG:$rA),
3020 (v4i32 v4i32SExt16Imm:$val)))]>;
3022 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3023 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
3026 defm CEQB : CmpEqualByte;
3027 defm CEQBI : CmpEqualByteImm;
3028 defm CEQH : CmpEqualHalfword;
3029 defm CEQHI : CmpEqualHalfwordImm;
3030 defm CEQ : CmpEqualWord;
3031 defm CEQI : CmpEqualWordImm;
3032 defm CGTB : CmpGtrByte;
3033 defm CGTBI : CmpGtrByteImm;
3034 defm CGTH : CmpGtrHalfword;
3035 defm CGTHI : CmpGtrHalfwordImm;
3036 defm CGT : CmpGtrWord;
3037 defm CGTI : CmpGtrWordImm;
3038 defm CLGTB : CmpLGtrByte;
3039 defm CLGTBI : CmpLGtrByteImm;
3040 defm CLGTH : CmpLGtrHalfword;
3041 defm CLGTHI : CmpLGtrHalfwordImm;
3042 defm CLGT : CmpLGtrWord;
3043 defm CLGTI : CmpLGtrWordImm;
3045 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3046 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
3047 // define a pattern to generate the right code, as a binary operator
3048 // (in a manner of speaking.)
3050 // N.B.: This only matches the setcc set of conditionals. Special pattern
3051 // matching is used for select conditionals.
3052 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3054 class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3055 SPUInstr xorinst, SPUInstr cmpare>:
3056 Pat<(cond rclass:$rA, rclass:$rB),
3057 (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
3059 class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3060 PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
3061 Pat<(cond rclass:$rA, (inttype immpred:$imm)),
3062 (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
3064 def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
3065 def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
3067 def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
3068 def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
3070 def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
3071 def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
3073 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
3074 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3075 Pat<(cond rclass:$rA, rclass:$rB),
3076 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3077 (cmpOp2 rclass:$rA, rclass:$rB))>;
3079 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3081 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3082 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
3083 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
3084 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
3086 def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
3087 def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
3088 def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
3089 def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
3090 def : Pat<(setle R8C:$rA, R8C:$rB),
3091 (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3092 def : Pat<(setle R8C:$rA, immU8:$imm),
3093 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3095 def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
3096 def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
3097 ORr16, CGTHIr16, CEQHIr16>;
3098 def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
3099 def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
3100 def : Pat<(setle R16C:$rA, R16C:$rB),
3101 (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3102 def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
3103 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3105 def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
3106 def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
3107 ORr32, CGTIr32, CEQIr32>;
3108 def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
3109 def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
3110 def : Pat<(setle R32C:$rA, R32C:$rB),
3111 (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3112 def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
3113 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3115 def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
3116 def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
3117 def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
3118 def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
3119 def : Pat<(setule R8C:$rA, R8C:$rB),
3120 (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3121 def : Pat<(setule R8C:$rA, immU8:$imm),
3122 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3124 def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
3125 def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
3126 ORr16, CLGTHIr16, CEQHIr16>;
3127 def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
3128 def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
3129 CLGTHIr16, CEQHIr16>;
3130 def : Pat<(setule R16C:$rA, R16C:$rB),
3131 (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3132 def : Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
3133 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3135 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
3136 def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
3137 ORr32, CLGTIr32, CEQIr32>;
3138 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
3139 def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
3140 def : Pat<(setule R32C:$rA, R32C:$rB),
3141 (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3142 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
3143 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3145 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3146 // select conditional patterns:
3147 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3149 class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3150 SPUInstr selinstr, SPUInstr cmpare>:
3151 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3152 rclass:$rTrue, rclass:$rFalse),
3153 (selinstr rclass:$rTrue, rclass:$rFalse,
3154 (cmpare rclass:$rA, rclass:$rB))>;
3156 class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3157 PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
3158 Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
3159 rclass:$rTrue, rclass:$rFalse),
3160 (selinstr rclass:$rTrue, rclass:$rFalse,
3161 (cmpare rclass:$rA, immpred:$imm))>;
3163 def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
3164 def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
3165 def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
3166 def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
3167 def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
3168 def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
3170 def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
3171 def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
3172 def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
3173 def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
3174 def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
3175 def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
3177 def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
3178 def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
3179 def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
3180 def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
3181 def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
3182 def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
3184 class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3185 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3187 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3188 rclass:$rFalse, rclass:$rTrue),
3189 (selinstr rclass:$rTrue, rclass:$rFalse,
3190 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3191 (cmpOp2 rclass:$rA, rclass:$rB)))>;
3193 class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3195 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3197 Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
3198 rclass:$rTrue, rclass:$rFalse),
3199 (selinstr rclass:$rFalse, rclass:$rTrue,
3200 (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
3201 (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
3203 def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
3204 def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
3205 SELBr8, ORr8, CGTBIr8, CEQBIr8>;
3207 def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
3208 def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
3209 SELBr16, ORr16, CGTHIr16, CEQHIr16>;
3211 def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
3212 def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
3213 SELBr32, ORr32, CGTIr32, CEQIr32>;
3215 def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
3216 def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
3217 SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
3219 def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
3220 def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
3221 SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
3223 def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
3224 def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
3225 SELBr32, ORr32, CLGTIr32, CEQIr32>;
3227 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3230 // All calls clobber the non-callee-saved registers:
3231 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
3232 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
3233 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
3234 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
3235 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
3236 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
3237 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
3238 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
3239 // All of these instructions use $lr (aka $0)
3241 // Branch relative and set link: Used if we actually know that the target
3242 // is within [-32768, 32767] bytes of the target
3244 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
3245 "brsl\t$$lr, $func",
3246 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
3248 // Branch absolute and set link: Used if we actually know that the target
3249 // is an absolute address
3251 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
3252 "brasl\t$$lr, $func",
3253 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
3255 // Branch indirect and set link if external data. These instructions are not
3256 // actually generated, matched by an intrinsic:
3257 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
3258 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
3259 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
3260 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
3262 // Branch indirect and set link. This is the "X-form" address version of a
3265 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
3268 // Unconditional branches:
3269 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
3271 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3275 // Unconditional, absolute address branch
3277 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3279 [/* no pattern */]>;
3283 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3285 // Various branches:
3287 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
3288 "brnz\t$rCond,$dest",
3290 [(brcond R32C:$rCond, bb:$dest)]>;
3293 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
3296 [/* no pattern */]>;
3299 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
3300 "brhnz\t$rCond,$dest",
3302 [(brcond R16C:$rCond, bb:$dest)]>;
3305 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
3308 [/* no pattern */]>;
3312 BICondForm<0b10010100100, "binz\t$rA, $func",
3313 [(SPUbinz R32C:$rA, R32C:$func)]>;
3316 BICondForm<0b00010100100, "biz\t$rA, $func",
3317 [(SPUbiz R32C:$rA, R32C:$func)]>;
3321 //===----------------------------------------------------------------------===//
3322 // setcc and brcond patterns:
3323 //===----------------------------------------------------------------------===//
3325 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3326 (BRHZ R16C:$rA, bb:$dest)>;
3327 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3328 (BRHNZ R16C:$rA, bb:$dest)>;
3330 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3331 (BRZ R32C:$rA, bb:$dest)>;
3332 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3333 (BRNZ R32C:$rA, bb:$dest)>;
3335 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3337 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3338 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3340 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3341 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3343 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3344 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3346 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3347 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3350 defm BRCONDeq : BranchCondEQ<seteq, BRHZ, BRZ>;
3351 defm BRCONDne : BranchCondEQ<setne, BRHNZ, BRNZ>;
3353 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3355 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3356 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3358 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3359 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3361 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3362 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3364 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3365 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3368 defm BRCONDugt : BranchCondLGT<setugt, BRHNZ, BRNZ>;
3369 defm BRCONDule : BranchCondLGT<setule, BRHZ, BRZ>;
3371 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3372 SPUInstr orinst32, SPUInstr brinst32>
3374 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3375 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3376 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3379 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3380 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3381 (CEQHr16 R16C:$rA, R16:$rB)),
3384 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3385 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3386 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3389 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3390 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3391 (CEQr32 R32C:$rA, R32C:$rB)),
3395 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZ, ORr32, BRNZ>;
3396 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZ, ORr32, BRZ>;
3398 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3400 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3401 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3403 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3404 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3406 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3407 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3409 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3410 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3413 defm BRCONDgt : BranchCondGT<setgt, BRHNZ, BRNZ>;
3414 defm BRCONDle : BranchCondGT<setle, BRHZ, BRZ>;
3416 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3417 SPUInstr orinst32, SPUInstr brinst32>
3419 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3420 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3421 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3424 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3425 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3426 (CEQHr16 R16C:$rA, R16:$rB)),
3429 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3430 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3431 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3434 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3435 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3436 (CEQr32 R32C:$rA, R32C:$rB)),
3440 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZ, ORr32, BRNZ>;
3441 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZ, ORr32, BRZ>;
3443 let isTerminator = 1, isBarrier = 1 in {
3444 let isReturn = 1 in {
3446 RETForm<"bi\t$$lr", [(retflag)]>;
3450 //===----------------------------------------------------------------------===//
3451 // Single precision floating point instructions
3452 //===----------------------------------------------------------------------===//
3455 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3456 "fa\t$rT, $rA, $rB", SPrecFP,
3457 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3460 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3461 "fa\t$rT, $rA, $rB", SPrecFP,
3462 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3465 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3466 "fs\t$rT, $rA, $rB", SPrecFP,
3467 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3470 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3471 "fs\t$rT, $rA, $rB", SPrecFP,
3472 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3474 // Floating point reciprocal estimate
3476 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
3477 "frest\t$rT, $rA", SPrecFP,
3478 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
3481 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
3482 "frest\t$rT, $rA", SPrecFP,
3483 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
3485 // Floating point interpolate (used in conjunction with reciprocal estimate)
3487 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3488 "fi\t$rT, $rA, $rB", SPrecFP,
3489 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
3490 (v4f32 VECREG:$rB)))]>;
3493 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3494 "fi\t$rT, $rA, $rB", SPrecFP,
3495 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
3497 // Floating Compare Equal
3499 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3500 "fceq\t$rT, $rA, $rB", SPrecFP,
3501 [(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
3504 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3505 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3506 [(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3509 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3510 "fcgt\t$rT, $rA, $rB", SPrecFP,
3511 [(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
3514 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3515 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3516 [(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3518 // FP Status and Control Register Write
3519 // Why isn't rT a don't care in the ISA?
3520 // Should we create a special RRForm_3 for this guy and zero out the rT?
3522 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3523 "fscrwr\t$rA", SPrecFP,
3524 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3526 // FP Status and Control Register Read
3528 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3529 "fscrrd\t$rT", SPrecFP,
3530 [/* This instruction requires an intrinsic */]>;
3532 // llvm instruction space
3533 // How do these map onto cell instructions?
3535 // frest rC rB # c = 1/b (both lines)
3537 // fm rD rA rC # d = a * 1/b
3538 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3539 // fma rB rB rC rD # b = b * c + d
3540 // = -(d *b -a) * c + d
3541 // = a * c - c ( a *b *c - a)
3546 // These llvm instructions will actually map to library calls.
3547 // All that's needed, then, is to check that the appropriate library is
3548 // imported and do a brsl to the proper function name.
3549 // frem # fmod(x, y): x - (x/y) * y
3550 // (Note: fmod(double, double), fmodf(float,float)
3554 // Unimplemented SPU instruction space
3555 // floating reciprocal absolute square root estimate (frsqest)
3557 // The following are probably just intrinsics
3558 // status and control register write
3559 // status and control register read
3561 //--------------------------------------
3562 // Floating point multiply instructions
3563 //--------------------------------------
3566 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3567 "fm\t$rT, $rA, $rB", SPrecFP,
3568 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
3569 (v4f32 VECREG:$rB)))]>;
3572 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3573 "fm\t$rT, $rA, $rB", SPrecFP,
3574 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
3576 // Floating point multiply and add
3577 // e.g. d = c + (a * b)
3579 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3580 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3581 [(set (v4f32 VECREG:$rT),
3582 (fadd (v4f32 VECREG:$rC),
3583 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
3586 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3587 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3588 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3590 // FP multiply and subtract
3591 // Subtracts value in rC from product
3594 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3595 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3596 [(set (v4f32 VECREG:$rT),
3597 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
3598 (v4f32 VECREG:$rC)))]>;
3601 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3602 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3604 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
3606 // Floating Negative Mulitply and Subtract
3607 // Subtracts product from value in rC
3608 // res = fneg(fms a b c)
3611 // NOTE: subtraction order
3615 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3616 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3617 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3620 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3621 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3622 [(set (v4f32 VECREG:$rT),
3623 (fsub (v4f32 VECREG:$rC),
3624 (fmul (v4f32 VECREG:$rA),
3625 (v4f32 VECREG:$rB))))]>;
3627 //--------------------------------------
3628 // Floating Point Conversions
3629 // Signed conversions:
3631 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3632 "csflt\t$rT, $rA, 0", SPrecFP,
3633 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
3635 // Convert signed integer to floating point
3637 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
3638 "csflt\t$rT, $rA, 0", SPrecFP,
3639 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
3641 // Convert unsigned into to float
3643 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3644 "cuflt\t$rT, $rA, 0", SPrecFP,
3645 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
3648 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
3649 "cuflt\t$rT, $rA, 0", SPrecFP,
3650 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
3652 // Convert float to unsigned int
3653 // Assume that scale = 0
3656 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3657 "cfltu\t$rT, $rA, 0", SPrecFP,
3658 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
3661 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3662 "cfltu\t$rT, $rA, 0", SPrecFP,
3663 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
3665 // Convert float to signed int
3666 // Assume that scale = 0
3669 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3670 "cflts\t$rT, $rA, 0", SPrecFP,
3671 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
3674 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3675 "cflts\t$rT, $rA, 0", SPrecFP,
3676 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
3678 //===----------------------------------------------------------------------==//
3679 // Single<->Double precision conversions
3680 //===----------------------------------------------------------------------==//
3682 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
3683 // v4f32, output is v2f64--which goes in the name?)
3685 // Floating point extend single to double
3686 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
3687 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
3690 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3691 "fesd\t$rT, $rA", SPrecFP,
3692 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
3695 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
3696 "fesd\t$rT, $rA", SPrecFP,
3697 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
3699 // Floating point round double to single
3701 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3702 // "frds\t$rT, $rA,", SPrecFP,
3703 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
3706 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
3707 "frds\t$rT, $rA", SPrecFP,
3708 [(set R32FP:$rT, (fround R64FP:$rA))]>;
3710 //ToDo include anyextend?
3712 //===----------------------------------------------------------------------==//
3713 // Double precision floating point instructions
3714 //===----------------------------------------------------------------------==//
3716 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3717 "dfa\t$rT, $rA, $rB", DPrecFP,
3718 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
3721 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3722 "dfa\t$rT, $rA, $rB", DPrecFP,
3723 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3726 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3727 "dfs\t$rT, $rA, $rB", DPrecFP,
3728 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
3731 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3732 "dfs\t$rT, $rA, $rB", DPrecFP,
3733 [(set (v2f64 VECREG:$rT),
3734 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3737 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3738 "dfm\t$rT, $rA, $rB", DPrecFP,
3739 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
3742 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3743 "dfm\t$rT, $rA, $rB", DPrecFP,
3744 [(set (v2f64 VECREG:$rT),
3745 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3748 RRForm<0b00111010110, (outs R64FP:$rT),
3749 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3750 "dfma\t$rT, $rA, $rB", DPrecFP,
3751 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3752 RegConstraint<"$rC = $rT">,
3756 RRForm<0b00111010110, (outs VECREG:$rT),
3757 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3758 "dfma\t$rT, $rA, $rB", DPrecFP,
3759 [(set (v2f64 VECREG:$rT),
3760 (fadd (v2f64 VECREG:$rC),
3761 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
3762 RegConstraint<"$rC = $rT">,
3766 RRForm<0b10111010110, (outs R64FP:$rT),
3767 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3768 "dfms\t$rT, $rA, $rB", DPrecFP,
3769 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
3770 RegConstraint<"$rC = $rT">,
3774 RRForm<0b10111010110, (outs VECREG:$rT),
3775 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3776 "dfms\t$rT, $rA, $rB", DPrecFP,
3777 [(set (v2f64 VECREG:$rT),
3778 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3779 (v2f64 VECREG:$rC)))]>;
3781 // FNMS: - (a * b - c)
3782 // - (a * b) + c => c - (a * b)
3784 RRForm<0b01111010110, (outs R64FP:$rT),
3785 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3786 "dfnms\t$rT, $rA, $rB", DPrecFP,
3787 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3788 RegConstraint<"$rC = $rT">,
3791 def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
3792 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
3795 RRForm<0b01111010110, (outs VECREG:$rT),
3796 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3797 "dfnms\t$rT, $rA, $rB", DPrecFP,
3798 [(set (v2f64 VECREG:$rT),
3799 (fsub (v2f64 VECREG:$rC),
3800 (fmul (v2f64 VECREG:$rA),
3801 (v2f64 VECREG:$rB))))]>,
3802 RegConstraint<"$rC = $rT">,
3805 def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3806 (v2f64 VECREG:$rC))),
3807 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
3812 RRForm<0b11111010110, (outs R64FP:$rT),
3813 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3814 "dfnma\t$rT, $rA, $rB", DPrecFP,
3815 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
3816 RegConstraint<"$rC = $rT">,
3820 RRForm<0b11111010110, (outs VECREG:$rT),
3821 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3822 "dfnma\t$rT, $rA, $rB", DPrecFP,
3823 [(set (v2f64 VECREG:$rT),
3824 (fneg (fadd (v2f64 VECREG:$rC),
3825 (fmul (v2f64 VECREG:$rA),
3826 (v2f64 VECREG:$rB)))))]>,
3827 RegConstraint<"$rC = $rT">,
3830 //===----------------------------------------------------------------------==//
3831 // Floating point negation and absolute value
3832 //===----------------------------------------------------------------------==//
3834 def : Pat<(fneg (v4f32 VECREG:$rA)),
3835 (XORfnegvec (v4f32 VECREG:$rA),
3836 (v4f32 (ILHUv4i32 0x8000)))>;
3838 def : Pat<(fneg R32FP:$rA),
3839 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
3841 def : Pat<(fneg (v2f64 VECREG:$rA)),
3842 (XORfnegvec (v2f64 VECREG:$rA),
3843 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
3845 def : Pat<(fneg R64FP:$rA),
3846 (XORfneg64 R64FP:$rA,
3847 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
3849 // Floating point absolute value
3851 def : Pat<(fabs R32FP:$rA),
3852 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
3854 def : Pat<(fabs (v4f32 VECREG:$rA)),
3855 (ANDfabsvec (v4f32 VECREG:$rA),
3856 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3858 def : Pat<(fabs R64FP:$rA),
3859 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
3861 def : Pat<(fabs (v2f64 VECREG:$rA)),
3862 (ANDfabsvec (v2f64 VECREG:$rA),
3863 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3865 //===----------------------------------------------------------------------===//
3866 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
3867 // in the odd pipeline)
3868 //===----------------------------------------------------------------------===//
3870 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
3873 let Inst{0-10} = 0b10000000010;
3874 let Inst{11-17} = 0;
3875 let Inst{18-24} = 0;
3876 let Inst{25-31} = 0;
3879 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
3882 let Inst{0-10} = 0b10000000000;
3883 let Inst{11-17} = 0;
3884 let Inst{18-24} = 0;
3885 let Inst{25-31} = 0;
3888 //===----------------------------------------------------------------------===//
3889 // Bit conversions (type conversions between vector/packed types)
3890 // NOTE: Promotions are handled using the XS* instructions. Truncation
3892 //===----------------------------------------------------------------------===//
3893 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3894 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3895 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3896 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3897 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3899 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3900 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3901 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3902 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3903 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3905 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3906 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3907 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3908 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3909 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3911 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3912 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3913 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3914 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3915 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3917 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3918 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3919 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3920 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3921 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3923 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3924 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3925 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3926 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3927 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3929 def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3930 def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
3932 //===----------------------------------------------------------------------===//
3933 // Instruction patterns:
3934 //===----------------------------------------------------------------------===//
3936 // General 32-bit constants:
3937 def : Pat<(i32 imm:$imm),
3938 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3940 // Single precision float constants:
3941 def : Pat<(f32 fpimm:$imm),
3942 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3944 // General constant 32-bit vectors
3945 def : Pat<(v4i32 v4i32Imm:$imm),
3946 (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
3947 (LO16_vec v4i32Imm:$imm))>;
3950 def : Pat<(i8 imm:$imm),
3953 //===----------------------------------------------------------------------===//
3954 // Call instruction patterns:
3955 //===----------------------------------------------------------------------===//
3960 //===----------------------------------------------------------------------===//
3961 // Zero/Any/Sign extensions
3962 //===----------------------------------------------------------------------===//
3964 // zext 1->32: Zero extend i1 to i32
3965 def : Pat<(SPUextract_i1_zext R32C:$rSrc),
3966 (ANDIr32 R32C:$rSrc, 0x1)>;
3968 // sext 8->32: Sign extend bytes to words
3969 def : Pat<(sext_inreg R32C:$rSrc, i8),
3970 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
3972 def : Pat<(i32 (sext R8C:$rSrc)),
3973 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
3975 def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
3976 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
3977 (v4i32 VECREG:$rSrc))))>;
3979 // zext 8->16: Zero extend bytes to halfwords
3980 def : Pat<(i16 (zext R8C:$rSrc)),
3981 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
3983 // zext 8->32 from preferred slot in load/store
3984 def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
3985 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
3988 // zext 8->32: Zero extend bytes to words
3989 def : Pat<(i32 (zext R8C:$rSrc)),
3990 (ANDIi8i32 R8C:$rSrc, 0xff)>;
3992 // anyext 8->16: Extend 8->16 bits, irrespective of sign
3993 def : Pat<(i16 (anyext R8C:$rSrc)),
3994 (ORHIi8i16 R8C:$rSrc, 0)>;
3996 // anyext 8->32: Extend 8->32 bits, irrespective of sign
3997 def : Pat<(i32 (anyext R8C:$rSrc)),
3998 (ORIi8i32 R8C:$rSrc, 0)>;
4000 // zext 16->32: Zero extend halfwords to words
4001 def : Pat<(i32 (zext R16C:$rSrc)),
4002 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
4004 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
4005 (ANDIi16i32 R16C:$rSrc, 0xf)>;
4007 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
4008 (ANDIi16i32 R16C:$rSrc, 0xff)>;
4010 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
4011 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
4013 // anyext 16->32: Extend 16->32 bits, irrespective of sign
4014 def : Pat<(i32 (anyext R16C:$rSrc)),
4015 (ORIi16i32 R16C:$rSrc, 0)>;
4017 //===----------------------------------------------------------------------===//
4018 // Address generation: SPU, like PPC, has to split addresses into high and
4019 // low parts in order to load them into a register.
4020 //===----------------------------------------------------------------------===//
4022 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
4023 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
4024 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
4025 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
4027 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
4028 (SPUlo tglobaladdr:$in, 0)),
4029 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4031 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
4032 (SPUlo texternalsym:$in, 0)),
4033 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4035 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
4036 (SPUlo tjumptable:$in, 0)),
4037 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4039 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
4040 (SPUlo tconstpool:$in, 0)),
4041 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4043 def : Pat<(SPUindirect R32C:$sp, i32ImmSExt10:$imm),
4044 (AIr32 R32C:$sp, i32ImmSExt10:$imm)>;
4046 def : Pat<(SPUindirect R32C:$sp, imm:$imm),
4048 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm)))>;
4050 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
4051 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4053 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
4054 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4056 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
4057 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4059 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
4060 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4063 include "CellSDKIntrinsics.td"