1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start timm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end timm:$amt)]>;
33 //===----------------------------------------------------------------------===//
34 // DWARF debugging Pseudo Instructions
35 //===----------------------------------------------------------------------===//
37 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
38 "${:comment} .loc $file, $line, $col",
39 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
42 //===----------------------------------------------------------------------===//
44 // NB: The ordering is actually important, since the instruction selection
45 // will try each of the instructions in sequence, i.e., the D-form first with
46 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
47 // finally the X-form with the register-register.
48 //===----------------------------------------------------------------------===//
50 let canFoldAsLoad = 1 in {
51 class LoadDFormVec<ValueType vectype>
52 : RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
55 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
58 class LoadDForm<RegisterClass rclass>
59 : RI10Form<0b00101100, (outs rclass:$rT), (ins memri10:$src),
62 [(set rclass:$rT, (load dform_addr:$src))]>
67 def v16i8: LoadDFormVec<v16i8>;
68 def v8i16: LoadDFormVec<v8i16>;
69 def v4i32: LoadDFormVec<v4i32>;
70 def v2i64: LoadDFormVec<v2i64>;
71 def v4f32: LoadDFormVec<v4f32>;
72 def v2f64: LoadDFormVec<v2f64>;
74 def r128: LoadDForm<GPRC>;
75 def r64: LoadDForm<R64C>;
76 def r32: LoadDForm<R32C>;
77 def f32: LoadDForm<R32FP>;
78 def f64: LoadDForm<R64FP>;
79 def r16: LoadDForm<R16C>;
80 def r8: LoadDForm<R8C>;
83 class LoadAFormVec<ValueType vectype>
84 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
87 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
90 class LoadAForm<RegisterClass rclass>
91 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
94 [(set rclass:$rT, (load aform_addr:$src))]>
99 def v16i8: LoadAFormVec<v16i8>;
100 def v8i16: LoadAFormVec<v8i16>;
101 def v4i32: LoadAFormVec<v4i32>;
102 def v2i64: LoadAFormVec<v2i64>;
103 def v4f32: LoadAFormVec<v4f32>;
104 def v2f64: LoadAFormVec<v2f64>;
106 def r128: LoadAForm<GPRC>;
107 def r64: LoadAForm<R64C>;
108 def r32: LoadAForm<R32C>;
109 def f32: LoadAForm<R32FP>;
110 def f64: LoadAForm<R64FP>;
111 def r16: LoadAForm<R16C>;
112 def r8: LoadAForm<R8C>;
115 class LoadXFormVec<ValueType vectype>
116 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
119 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
122 class LoadXForm<RegisterClass rclass>
123 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
126 [(set rclass:$rT, (load xform_addr:$src))]>
129 multiclass LoadXForms
131 def v16i8: LoadXFormVec<v16i8>;
132 def v8i16: LoadXFormVec<v8i16>;
133 def v4i32: LoadXFormVec<v4i32>;
134 def v2i64: LoadXFormVec<v2i64>;
135 def v4f32: LoadXFormVec<v4f32>;
136 def v2f64: LoadXFormVec<v2f64>;
138 def r128: LoadXForm<GPRC>;
139 def r64: LoadXForm<R64C>;
140 def r32: LoadXForm<R32C>;
141 def f32: LoadXForm<R32FP>;
142 def f64: LoadXForm<R64FP>;
143 def r16: LoadXForm<R16C>;
144 def r8: LoadXForm<R8C>;
147 defm LQA : LoadAForms;
148 defm LQD : LoadDForms;
149 defm LQX : LoadXForms;
151 /* Load quadword, PC relative: Not much use at this point in time.
152 Might be of use later for relocatable code. It's effectively the
153 same as LQA, but uses PC-relative addressing.
154 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
155 "lqr\t$rT, $disp", LoadStore,
156 [(set VECREG:$rT, (load iaddr:$disp))]>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
163 class StoreDFormVec<ValueType vectype>
164 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
167 [(store (vectype VECREG:$rT), dform_addr:$src)]>
170 class StoreDForm<RegisterClass rclass>
171 : RI10Form<0b00100100, (outs), (ins rclass:$rT, memri10:$src),
174 [(store rclass:$rT, dform_addr:$src)]>
177 multiclass StoreDForms
179 def v16i8: StoreDFormVec<v16i8>;
180 def v8i16: StoreDFormVec<v8i16>;
181 def v4i32: StoreDFormVec<v4i32>;
182 def v2i64: StoreDFormVec<v2i64>;
183 def v4f32: StoreDFormVec<v4f32>;
184 def v2f64: StoreDFormVec<v2f64>;
186 def r128: StoreDForm<GPRC>;
187 def r64: StoreDForm<R64C>;
188 def r32: StoreDForm<R32C>;
189 def f32: StoreDForm<R32FP>;
190 def f64: StoreDForm<R64FP>;
191 def r16: StoreDForm<R16C>;
192 def r8: StoreDForm<R8C>;
195 class StoreAFormVec<ValueType vectype>
196 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
199 [(store (vectype VECREG:$rT), aform_addr:$src)]>;
201 class StoreAForm<RegisterClass rclass>
202 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
205 [(store rclass:$rT, aform_addr:$src)]>;
207 multiclass StoreAForms
209 def v16i8: StoreAFormVec<v16i8>;
210 def v8i16: StoreAFormVec<v8i16>;
211 def v4i32: StoreAFormVec<v4i32>;
212 def v2i64: StoreAFormVec<v2i64>;
213 def v4f32: StoreAFormVec<v4f32>;
214 def v2f64: StoreAFormVec<v2f64>;
216 def r128: StoreAForm<GPRC>;
217 def r64: StoreAForm<R64C>;
218 def r32: StoreAForm<R32C>;
219 def f32: StoreAForm<R32FP>;
220 def f64: StoreAForm<R64FP>;
221 def r16: StoreAForm<R16C>;
222 def r8: StoreAForm<R8C>;
225 class StoreXFormVec<ValueType vectype>
226 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
229 [(store (vectype VECREG:$rT), xform_addr:$src)]>
232 class StoreXForm<RegisterClass rclass>
233 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
236 [(store rclass:$rT, xform_addr:$src)]>
239 multiclass StoreXForms
241 def v16i8: StoreXFormVec<v16i8>;
242 def v8i16: StoreXFormVec<v8i16>;
243 def v4i32: StoreXFormVec<v4i32>;
244 def v2i64: StoreXFormVec<v2i64>;
245 def v4f32: StoreXFormVec<v4f32>;
246 def v2f64: StoreXFormVec<v2f64>;
248 def r128: StoreXForm<GPRC>;
249 def r64: StoreXForm<R64C>;
250 def r32: StoreXForm<R32C>;
251 def f32: StoreXForm<R32FP>;
252 def f64: StoreXForm<R64FP>;
253 def r16: StoreXForm<R16C>;
254 def r8: StoreXForm<R8C>;
257 defm STQD : StoreDForms;
258 defm STQA : StoreAForms;
259 defm STQX : StoreXForms;
261 /* Store quadword, PC relative: Not much use at this point in time. Might
262 be useful for relocatable code.
263 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
264 "stqr\t$rT, $disp", LoadStore,
265 [(store VECREG:$rT, iaddr:$disp)]>;
268 //===----------------------------------------------------------------------===//
269 // Generate Controls for Insertion:
270 //===----------------------------------------------------------------------===//
272 def CBD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
273 "cbd\t$rT, $src", ShuffleOp,
274 [(set (v16i8 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
276 def CBX: RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
277 "cbx\t$rT, $src", ShuffleOp,
278 [(set (v16i8 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
280 def CHD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
281 "chd\t$rT, $src", ShuffleOp,
282 [(set (v8i16 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
284 def CHX: RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
285 "chx\t$rT, $src", ShuffleOp,
286 [(set (v8i16 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
288 def CWD: RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
289 "cwd\t$rT, $src", ShuffleOp,
290 [(set (v4i32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
292 def CWX: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
293 "cwx\t$rT, $src", ShuffleOp,
294 [(set (v4i32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
296 def CWDf32: RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
297 "cwd\t$rT, $src", ShuffleOp,
298 [(set (v4f32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
300 def CWXf32: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
301 "cwx\t$rT, $src", ShuffleOp,
302 [(set (v4f32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
304 def CDD: RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
305 "cdd\t$rT, $src", ShuffleOp,
306 [(set (v2i64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
308 def CDX: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
309 "cdx\t$rT, $src", ShuffleOp,
310 [(set (v2i64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
312 def CDDf64: RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
313 "cdd\t$rT, $src", ShuffleOp,
314 [(set (v2f64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
316 def CDXf64: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
317 "cdx\t$rT, $src", ShuffleOp,
318 [(set (v2f64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
320 //===----------------------------------------------------------------------===//
321 // Constant formation:
322 //===----------------------------------------------------------------------===//
325 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
326 "ilh\t$rT, $val", ImmLoad,
327 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
330 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
331 "ilh\t$rT, $val", ImmLoad,
332 [(set R16C:$rT, immSExt16:$val)]>;
334 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
335 // the right constant")
337 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
338 "ilh\t$rT, $val", ImmLoad,
339 [(set R8C:$rT, immSExt8:$val)]>;
341 // IL does sign extension!
343 class ILInst<dag OOL, dag IOL, list<dag> pattern>:
344 RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val",
347 class ILVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
348 ILInst<(outs VECREG:$rT), (ins immtype:$val),
349 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
351 class ILRegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
352 ILInst<(outs rclass:$rT), (ins immtype:$val),
353 [(set rclass:$rT, xform:$val)]>;
355 multiclass ImmediateLoad
357 def v2i64: ILVecInst<v2i64, s16imm_i64, v2i64SExt16Imm>;
358 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
360 // TODO: Need v2f64, v4f32
362 def r64: ILRegInst<R64C, s16imm_i64, immSExt16>;
363 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
364 def f32: ILRegInst<R32FP, s16imm_f32, fpimmSExt16>;
365 def f64: ILRegInst<R64FP, s16imm_f64, fpimmSExt16>;
368 defm IL : ImmediateLoad;
370 class ILHUInst<dag OOL, dag IOL, list<dag> pattern>:
371 RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val",
374 class ILHUVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
375 ILHUInst<(outs VECREG:$rT), (ins immtype:$val),
376 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
378 class ILHURegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
379 ILHUInst<(outs rclass:$rT), (ins immtype:$val),
380 [(set rclass:$rT, xform:$val)]>;
382 multiclass ImmLoadHalfwordUpper
384 def v2i64: ILHUVecInst<v2i64, u16imm_i64, immILHUvec_i64>;
385 def v4i32: ILHUVecInst<v4i32, u16imm_i32, immILHUvec>;
387 def r64: ILHURegInst<R64C, u16imm_i64, hi16>;
388 def r32: ILHURegInst<R32C, u16imm_i32, hi16>;
390 // Loads the high portion of an address
391 def hi: ILHURegInst<R32C, symbolHi, hi16>;
393 // Used in custom lowering constant SFP loads:
394 def f32: ILHURegInst<R32FP, f16imm, hi16_f32>;
397 defm ILHU : ImmLoadHalfwordUpper;
399 // Immediate load address (can also be used to load 18-bit unsigned constants,
400 // see the zext 16->32 pattern)
402 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
403 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
406 class ILAVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
407 ILAInst<(outs VECREG:$rT), (ins immtype:$val),
408 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
410 class ILARegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
411 ILAInst<(outs rclass:$rT), (ins immtype:$val),
412 [(set rclass:$rT, xform:$val)]>;
414 multiclass ImmLoadAddress
416 def v2i64: ILAVecInst<v2i64, u18imm, v2i64Uns18Imm>;
417 def v4i32: ILAVecInst<v4i32, u18imm, v4i32Uns18Imm>;
419 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
420 def r32: ILARegInst<R32C, u18imm, imm18>;
421 def f32: ILARegInst<R32FP, f18imm, fpimm18>;
422 def f64: ILARegInst<R64FP, f18imm_f64, fpimm18>;
424 def lo: ILARegInst<R32C, symbolLo, imm18>;
426 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
430 defm ILA : ImmLoadAddress;
432 // Immediate OR, Halfword Lower: The "other" part of loading large constants
433 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
434 // Note that these are really two operand instructions, but they're encoded
435 // as three operands with the first two arguments tied-to each other.
437 class IOHLInst<dag OOL, dag IOL, list<dag> pattern>:
438 RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val",
440 RegConstraint<"$rS = $rT">,
443 class IOHLVecInst<ValueType vectype, Operand immtype /* , PatLeaf xform */>:
444 IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val),
447 class IOHLRegInst<RegisterClass rclass, Operand immtype /* , PatLeaf xform */>:
448 IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val),
451 multiclass ImmOrHalfwordLower
453 def v2i64: IOHLVecInst<v2i64, u16imm_i64>;
454 def v4i32: IOHLVecInst<v4i32, u16imm_i32>;
456 def r32: IOHLRegInst<R32C, i32imm>;
457 def f32: IOHLRegInst<R32FP, f32imm>;
459 def lo: IOHLRegInst<R32C, symbolLo>;
462 defm IOHL: ImmOrHalfwordLower;
464 // Form select mask for bytes using immediate, used in conjunction with the
467 class FSMBIVec<ValueType vectype>:
468 RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
471 [(set (vectype VECREG:$rT), (SPUselmask (i16 immU16:$val)))]>;
473 multiclass FormSelectMaskBytesImm
475 def v16i8: FSMBIVec<v16i8>;
476 def v8i16: FSMBIVec<v8i16>;
477 def v4i32: FSMBIVec<v4i32>;
478 def v2i64: FSMBIVec<v2i64>;
481 defm FSMBI : FormSelectMaskBytesImm;
483 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
485 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
486 "fsmb\t$rT, $rA", SelectOp,
487 [(set (v16i8 VECREG:$rT), (SPUselmask R16C:$rA))]>;
489 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
490 // only 8-bits wide (even though it's input as 16-bits here)
492 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
493 "fsmh\t$rT, $rA", SelectOp,
494 [(set (v8i16 VECREG:$rT), (SPUselmask R16C:$rA))]>;
496 // fsm: Form select mask for words. Like the other fsm* instructions,
497 // only the lower 4 bits of $rA are significant.
498 class FSMInst<ValueType vectype, RegisterClass rclass>:
499 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins rclass:$rA),
502 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
504 multiclass FormSelectMaskWord {
505 def r32 : FSMInst<v4i32, R32C>;
506 def r16 : FSMInst<v4i32, R16C>;
509 defm FSM : FormSelectMaskWord;
511 // Special case when used for i64 math operations
512 multiclass FormSelectMaskWord64 {
513 def r32 : FSMInst<v2i64, R32C>;
514 def r16 : FSMInst<v2i64, R16C>;
517 defm FSM64 : FormSelectMaskWord64;
519 //===----------------------------------------------------------------------===//
520 // Integer and Logical Operations:
521 //===----------------------------------------------------------------------===//
524 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
525 "ah\t$rT, $rA, $rB", IntegerOp,
526 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
528 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
529 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
532 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
533 "ah\t$rT, $rA, $rB", IntegerOp,
534 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
537 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
538 "ahi\t$rT, $rA, $val", IntegerOp,
539 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
540 v8i16SExt10Imm:$val))]>;
543 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
544 "ahi\t$rT, $rA, $val", IntegerOp,
545 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
548 RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
549 "a\t$rT, $rA, $rB", IntegerOp,
550 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
552 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
553 (Avec VECREG:$rA, VECREG:$rB)>;
556 RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
557 "a\t$rT, $rA, $rB", IntegerOp,
558 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
561 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
562 "a\t$rT, $rA, $rB", IntegerOp,
566 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
567 "ai\t$rT, $rA, $val", IntegerOp,
568 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
569 v4i32SExt10Imm:$val))]>;
572 RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
573 "ai\t$rT, $rA, $val", IntegerOp,
574 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
577 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
578 "sfh\t$rT, $rA, $rB", IntegerOp,
579 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
580 (v8i16 VECREG:$rB)))]>;
583 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
584 "sfh\t$rT, $rA, $rB", IntegerOp,
585 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
588 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
589 "sfhi\t$rT, $rA, $val", IntegerOp,
590 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
591 (v8i16 VECREG:$rA)))]>;
593 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
594 "sfhi\t$rT, $rA, $val", IntegerOp,
595 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
597 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
598 (ins VECREG:$rA, VECREG:$rB),
599 "sf\t$rT, $rA, $rB", IntegerOp,
600 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
602 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
603 "sf\t$rT, $rA, $rB", IntegerOp,
604 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
607 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
608 "sfi\t$rT, $rA, $val", IntegerOp,
609 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
610 (v4i32 VECREG:$rA)))]>;
612 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
613 (ins R32C:$rA, s10imm_i32:$val),
614 "sfi\t$rT, $rA, $val", IntegerOp,
615 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
617 // ADDX: only available in vector form, doesn't match a pattern.
618 class ADDXInst<dag OOL, dag IOL, list<dag> pattern>:
619 RRForm<0b00000010110, OOL, IOL,
620 "addx\t$rT, $rA, $rB",
623 class ADDXVecInst<ValueType vectype>:
624 ADDXInst<(outs VECREG:$rT),
625 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
626 [(set (vectype VECREG:$rT),
627 (SPUaddx (vectype VECREG:$rA), (vectype VECREG:$rB),
628 (vectype VECREG:$rCarry)))]>,
629 RegConstraint<"$rCarry = $rT">,
632 class ADDXRegInst<RegisterClass rclass>:
633 ADDXInst<(outs rclass:$rT),
634 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
636 (SPUaddx rclass:$rA, rclass:$rB, rclass:$rCarry))]>,
637 RegConstraint<"$rCarry = $rT">,
640 multiclass AddExtended {
641 def v2i64 : ADDXVecInst<v2i64>;
642 def v4i32 : ADDXVecInst<v4i32>;
643 def r64 : ADDXRegInst<R64C>;
644 def r32 : ADDXRegInst<R32C>;
647 defm ADDX : AddExtended;
649 // CG: Generate carry for add
650 class CGInst<dag OOL, dag IOL, list<dag> pattern>:
651 RRForm<0b01000011000, OOL, IOL,
655 class CGVecInst<ValueType vectype>:
656 CGInst<(outs VECREG:$rT),
657 (ins VECREG:$rA, VECREG:$rB),
658 [(set (vectype VECREG:$rT),
659 (SPUcarry_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
661 class CGRegInst<RegisterClass rclass>:
662 CGInst<(outs rclass:$rT),
663 (ins rclass:$rA, rclass:$rB),
665 (SPUcarry_gen rclass:$rA, rclass:$rB))]>;
667 multiclass CarryGenerate {
668 def v2i64 : CGVecInst<v2i64>;
669 def v4i32 : CGVecInst<v4i32>;
670 def r64 : CGRegInst<R64C>;
671 def r32 : CGRegInst<R32C>;
674 defm CG : CarryGenerate;
676 // SFX: Subract from, extended. This is used in conjunction with BG to subtract
677 // with carry (borrow, in this case)
678 class SFXInst<dag OOL, dag IOL, list<dag> pattern>:
679 RRForm<0b10000010110, OOL, IOL,
680 "sfx\t$rT, $rA, $rB",
683 class SFXVecInst<ValueType vectype>:
684 SFXInst<(outs VECREG:$rT),
685 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
686 [(set (vectype VECREG:$rT),
687 (SPUsubx (vectype VECREG:$rA), (vectype VECREG:$rB),
688 (vectype VECREG:$rCarry)))]>,
689 RegConstraint<"$rCarry = $rT">,
692 class SFXRegInst<RegisterClass rclass>:
693 SFXInst<(outs rclass:$rT),
694 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
696 (SPUsubx rclass:$rA, rclass:$rB, rclass:$rCarry))]>,
697 RegConstraint<"$rCarry = $rT">,
700 multiclass SubtractExtended {
701 def v2i64 : SFXVecInst<v2i64>;
702 def v4i32 : SFXVecInst<v4i32>;
703 def r64 : SFXRegInst<R64C>;
704 def r32 : SFXRegInst<R32C>;
707 defm SFX : SubtractExtended;
709 // BG: only available in vector form, doesn't match a pattern.
710 class BGInst<dag OOL, dag IOL, list<dag> pattern>:
711 RRForm<0b01000010000, OOL, IOL,
715 class BGVecInst<ValueType vectype>:
716 BGInst<(outs VECREG:$rT),
717 (ins VECREG:$rA, VECREG:$rB),
718 [(set (vectype VECREG:$rT),
719 (SPUborrow_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
721 class BGRegInst<RegisterClass rclass>:
722 BGInst<(outs rclass:$rT),
723 (ins rclass:$rA, rclass:$rB),
725 (SPUborrow_gen rclass:$rA, rclass:$rB))]>;
727 multiclass BorrowGenerate {
728 def v4i32 : BGVecInst<v4i32>;
729 def v2i64 : BGVecInst<v2i64>;
730 def r64 : BGRegInst<R64C>;
731 def r32 : BGRegInst<R32C>;
734 defm BG : BorrowGenerate;
736 // BGX: Borrow generate, extended.
738 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
740 "bgx\t$rT, $rA, $rB", IntegerOp,
742 RegConstraint<"$rCarry = $rT">,
745 // Halfword multiply variants:
746 // N.B: These can be used to build up larger quantities (16x16 -> 32)
749 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
750 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
751 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
752 (v8i16 VECREG:$rB)))]>;
755 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
756 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
757 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
760 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
761 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
762 [(set (v4i32 VECREG:$rT),
763 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
766 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
767 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
768 [(set R32C:$rT, (mul (zext R16C:$rA),
772 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
773 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
774 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
776 // mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
777 // this only produces the lower 16 bits)
779 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
780 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
781 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
784 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
785 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
786 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
788 // mpyui: same issues as other multiplies, plus, this doesn't match a
789 // pattern... but may be used during target DAG selection or lowering
791 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
792 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
796 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
797 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
800 // mpya: 16 x 16 + 16 -> 32 bit result
802 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
803 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
804 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
805 (v8i16 VECREG:$rB)))),
806 (v4i32 VECREG:$rC)))]>;
809 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
810 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
811 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
814 def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
815 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
817 def MPYAr32_sextinreg:
818 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
819 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
820 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
821 (sext_inreg R32C:$rB, i16)),
825 // RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
826 // "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
827 // [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
830 // mpyh: multiply high, used to synthesize 32-bit multiplies
832 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
833 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
834 [(set (v4i32 VECREG:$rT),
835 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
838 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
839 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
840 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
842 // mpys: multiply high and shift right (returns the top half of
843 // a 16-bit multiply, sign extended to 32 bits.)
845 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
846 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
850 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
851 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
854 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
855 // the top 16 bits of the $rA, $rB)
857 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
858 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
859 [(set (v8i16 VECREG:$rT),
860 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
863 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
864 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
867 // mpyhha: Multiply high-high, add to $rT:
869 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
870 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
874 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
875 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
878 // mpyhhu: Multiply high-high, unsigned
880 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
881 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
885 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
886 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
889 // mpyhhau: Multiply high-high, unsigned
891 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
892 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
896 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
897 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
900 // clz: Count leading zeroes
902 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
903 "clz\t$rT, $rA", IntegerOp,
907 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
908 "clz\t$rT, $rA", IntegerOp,
909 [(set R32C:$rT, (ctlz R32C:$rA))]>;
911 // cntb: Count ones in bytes (aka "population count")
912 // NOTE: This instruction is really a vector instruction, but the custom
913 // lowering code uses it in unorthodox ways to support CTPOP for other
916 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
917 "cntb\t$rT, $rA", IntegerOp,
918 [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>;
921 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
922 "cntb\t$rT, $rA", IntegerOp,
923 [(set (v8i16 VECREG:$rT), (SPUcntb (v8i16 VECREG:$rA)))]>;
926 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
927 "cntb\t$rT, $rA", IntegerOp,
928 [(set (v4i32 VECREG:$rT), (SPUcntb (v4i32 VECREG:$rA)))]>;
930 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
931 // quantity stored into $rT
933 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
934 "gbb\t$rT, $rA", GatherOp,
937 // gbh: Gather all low order bits from each halfword in $rA into a single
938 // 8-bit quantity stored in $rT
940 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
941 "gbh\t$rT, $rA", GatherOp,
944 // gb: Gather all low order bits from each word in $rA into a single
945 // 4-bit quantity stored in $rT
947 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
948 "gb\t$rT, $rA", GatherOp,
951 // avgb: average bytes
953 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
954 "avgb\t$rT, $rA, $rB", ByteOp,
957 // absdb: absolute difference of bytes
959 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
960 "absdb\t$rT, $rA, $rB", ByteOp,
963 // sumb: sum bytes into halfwords
965 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
966 "sumb\t$rT, $rA, $rB", ByteOp,
969 // Sign extension operations:
970 class XSBHInst<dag OOL, dag IOL, list<dag> pattern>:
971 RRForm_1<0b01101101010, OOL, IOL,
972 "xsbh\t$rDst, $rSrc",
975 class XSBHVecInst<ValueType vectype>:
976 XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
977 [(set (v8i16 VECREG:$rDst), (sext (vectype VECREG:$rSrc)))]>;
979 class XSBHRegInst<RegisterClass rclass>:
980 XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc),
981 [(set rclass:$rDst, (sext_inreg rclass:$rSrc, i8))]>;
983 multiclass ExtendByteHalfword {
984 def v16i8: XSBHVecInst<v8i16>;
985 def r16: XSBHRegInst<R16C>;
987 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
988 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
989 // pattern below). Intentionally doesn't match a pattern because we want the
990 // sext 8->32 pattern to do the work for us, namely because we need the extra
992 def r32: XSBHRegInst<R32C>;
995 defm XSBH : ExtendByteHalfword;
997 // Sign-extend, but take an 8-bit register to a 16-bit register (not done as
1000 XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc),
1001 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
1003 // Sign extend halfwords to words:
1005 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
1006 "xshw\t$rDest, $rSrc", IntegerOp,
1007 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
1010 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
1011 "xshw\t$rDst, $rSrc", IntegerOp,
1012 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
1015 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
1016 "xshw\t$rDst, $rSrc", IntegerOp,
1017 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
1020 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
1021 "xswd\t$rDst, $rSrc", IntegerOp,
1022 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
1025 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
1026 "xswd\t$rDst, $rSrc", IntegerOp,
1027 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
1030 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
1031 "xswd\t$rDst, $rSrc", IntegerOp,
1032 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
1034 def : Pat<(sext R32C:$inp),
1035 (XSWDr32 R32C:$inp)>;
1039 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
1040 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
1041 IntegerOp, pattern>;
1043 class ANDVecInst<ValueType vectype>:
1044 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1045 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1046 (vectype VECREG:$rB)))]>;
1048 class ANDRegInst<RegisterClass rclass>:
1049 ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1050 [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>;
1052 multiclass BitwiseAnd
1054 def v16i8: ANDVecInst<v16i8>;
1055 def v8i16: ANDVecInst<v8i16>;
1056 def v4i32: ANDVecInst<v4i32>;
1057 def v2i64: ANDVecInst<v2i64>;
1059 def r128: ANDRegInst<GPRC>;
1060 def r64: ANDRegInst<R64C>;
1061 def r32: ANDRegInst<R32C>;
1062 def r16: ANDRegInst<R16C>;
1063 def r8: ANDRegInst<R8C>;
1065 //===---------------------------------------------
1066 // Special instructions to perform the fabs instruction
1067 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1068 [/* Intentionally does not match a pattern */]>;
1070 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1071 [/* Intentionally does not match a pattern */]>;
1073 // Could use v4i32, but won't for clarity
1074 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1075 [/* Intentionally does not match a pattern */]>;
1077 //===---------------------------------------------
1079 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
1080 // quantities -- see 16->32 zext pattern.
1082 // This pattern is somewhat artificial, since it might match some
1083 // compiler generated pattern but it is unlikely to do so.
1085 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
1086 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
1089 defm AND : BitwiseAnd;
1091 // N.B.: vnot_conv is one of those special target selection pattern fragments,
1092 // in which we expect there to be a bit_convert on the constant. Bear in mind
1093 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
1094 // constant -1 vector.)
1096 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
1097 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
1098 IntegerOp, pattern>;
1100 class ANDCVecInst<ValueType vectype>:
1101 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1102 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1103 (vnot (vectype VECREG:$rB))))]>;
1105 class ANDCRegInst<RegisterClass rclass>:
1106 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1107 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
1109 multiclass AndComplement
1111 def v16i8: ANDCVecInst<v16i8>;
1112 def v8i16: ANDCVecInst<v8i16>;
1113 def v4i32: ANDCVecInst<v4i32>;
1114 def v2i64: ANDCVecInst<v2i64>;
1116 def r128: ANDCRegInst<GPRC>;
1117 def r64: ANDCRegInst<R64C>;
1118 def r32: ANDCRegInst<R32C>;
1119 def r16: ANDCRegInst<R16C>;
1120 def r8: ANDCRegInst<R8C>;
1123 defm ANDC : AndComplement;
1125 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1126 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1127 IntegerOp, pattern>;
1129 multiclass AndByteImm
1131 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1132 [(set (v16i8 VECREG:$rT),
1133 (and (v16i8 VECREG:$rA),
1134 (v16i8 v16i8U8Imm:$val)))]>;
1136 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1137 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1140 defm ANDBI : AndByteImm;
1142 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1143 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1144 IntegerOp, pattern>;
1146 multiclass AndHalfwordImm
1148 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1149 [(set (v8i16 VECREG:$rT),
1150 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1152 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1153 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1155 // Zero-extend i8 to i16:
1156 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1157 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1160 defm ANDHI : AndHalfwordImm;
1162 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1163 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1164 IntegerOp, pattern>;
1166 multiclass AndWordImm
1168 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1169 [(set (v4i32 VECREG:$rT),
1170 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1172 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1173 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1175 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1177 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1179 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1181 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1182 // zext 16->32 pattern below.
1184 // Note that this pattern is somewhat artificial, since it might match
1185 // something the compiler generates but is unlikely to occur in practice.
1186 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1188 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1191 defm ANDI : AndWordImm;
1193 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1194 // Bitwise OR group:
1195 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1197 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1198 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1199 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1200 IntegerOp, pattern>;
1202 class ORVecInst<ValueType vectype>:
1203 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1204 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1205 (vectype VECREG:$rB)))]>;
1207 class ORRegInst<RegisterClass rclass>:
1208 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1209 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1211 class ORPromoteScalar<RegisterClass rclass>:
1212 ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB),
1213 [/* no pattern */]>;
1215 class ORExtractElt<RegisterClass rclass>:
1216 ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB),
1217 [/* no pattern */]>;
1219 multiclass BitwiseOr
1221 def v16i8: ORVecInst<v16i8>;
1222 def v8i16: ORVecInst<v8i16>;
1223 def v4i32: ORVecInst<v4i32>;
1224 def v2i64: ORVecInst<v2i64>;
1226 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1227 [(set (v4f32 VECREG:$rT),
1228 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1229 (v4i32 VECREG:$rB)))))]>;
1231 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1232 [(set (v2f64 VECREG:$rT),
1233 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1234 (v2i64 VECREG:$rB)))))]>;
1236 def r64: ORRegInst<R64C>;
1237 def r32: ORRegInst<R32C>;
1238 def r16: ORRegInst<R16C>;
1239 def r8: ORRegInst<R8C>;
1241 // OR instructions used to copy f32 and f64 registers.
1242 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1243 [/* no pattern */]>;
1245 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1246 [/* no pattern */]>;
1248 // scalar->vector promotion:
1249 def v16i8_i8: ORPromoteScalar<R8C>;
1250 def v8i16_i16: ORPromoteScalar<R16C>;
1251 def v4i32_i32: ORPromoteScalar<R32C>;
1252 def v2i64_i64: ORPromoteScalar<R64C>;
1253 def v4f32_f32: ORPromoteScalar<R32FP>;
1254 def v2f64_f64: ORPromoteScalar<R64FP>;
1256 // extract element 0:
1257 def i8_v16i8: ORExtractElt<R8C>;
1258 def i16_v8i16: ORExtractElt<R16C>;
1259 def i32_v4i32: ORExtractElt<R32C>;
1260 def i64_v2i64: ORExtractElt<R64C>;
1261 def f32_v4f32: ORExtractElt<R32FP>;
1262 def f64_v2f64: ORExtractElt<R64FP>;
1265 defm OR : BitwiseOr;
1267 // scalar->vector promotion patterns:
1268 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
1269 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
1271 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1272 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1274 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1275 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1277 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1278 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1280 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1281 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1283 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1284 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1286 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1288 def : Pat<(SPUvec2prefslot (v16i8 VECREG:$rA)),
1289 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1291 def : Pat<(SPUvec2prefslot_chained (v16i8 VECREG:$rA)),
1292 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1294 def : Pat<(SPUvec2prefslot (v8i16 VECREG:$rA)),
1295 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1297 def : Pat<(SPUvec2prefslot_chained (v8i16 VECREG:$rA)),
1298 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1300 def : Pat<(SPUvec2prefslot (v4i32 VECREG:$rA)),
1301 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1303 def : Pat<(SPUvec2prefslot_chained (v4i32 VECREG:$rA)),
1304 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1306 def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)),
1307 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1309 def : Pat<(SPUvec2prefslot_chained (v2i64 VECREG:$rA)),
1310 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1312 def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)),
1313 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1315 def : Pat<(SPUvec2prefslot_chained (v4f32 VECREG:$rA)),
1316 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1318 def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)),
1319 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1321 def : Pat<(SPUvec2prefslot_chained (v2f64 VECREG:$rA)),
1322 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1324 // ORC: Bitwise "or" with complement (c = a | ~b)
1326 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1327 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1328 IntegerOp, pattern>;
1330 class ORCVecInst<ValueType vectype>:
1331 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1332 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1333 (vnot (vectype VECREG:$rB))))]>;
1335 class ORCRegInst<RegisterClass rclass>:
1336 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1337 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1339 multiclass BitwiseOrComplement
1341 def v16i8: ORCVecInst<v16i8>;
1342 def v8i16: ORCVecInst<v8i16>;
1343 def v4i32: ORCVecInst<v4i32>;
1344 def v2i64: ORCVecInst<v2i64>;
1346 def r64: ORCRegInst<R64C>;
1347 def r32: ORCRegInst<R32C>;
1348 def r16: ORCRegInst<R16C>;
1349 def r8: ORCRegInst<R8C>;
1352 defm ORC : BitwiseOrComplement;
1354 // OR byte immediate
1355 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1356 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1357 IntegerOp, pattern>;
1359 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1360 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1361 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1362 (vectype immpred:$val)))]>;
1364 multiclass BitwiseOrByteImm
1366 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1368 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1369 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1372 defm ORBI : BitwiseOrByteImm;
1374 // OR halfword immediate
1375 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1376 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1377 IntegerOp, pattern>;
1379 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1380 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1381 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1384 multiclass BitwiseOrHalfwordImm
1386 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1388 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1389 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1391 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1392 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1393 [(set R16C:$rT, (or (anyext R8C:$rA),
1394 i16ImmSExt10:$val))]>;
1397 defm ORHI : BitwiseOrHalfwordImm;
1399 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1400 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1401 IntegerOp, pattern>;
1403 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1404 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1405 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1408 // Bitwise "or" with immediate
1409 multiclass BitwiseOrImm
1411 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1413 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1414 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1416 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1417 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1418 // infra "anyext 16->32" pattern.)
1419 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1420 [(set R32C:$rT, (or (anyext R16C:$rA),
1421 i32ImmSExt10:$val))]>;
1423 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1424 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1425 // infra "anyext 16->32" pattern.)
1426 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1427 [(set R32C:$rT, (or (anyext R8C:$rA),
1428 i32ImmSExt10:$val))]>;
1431 defm ORI : BitwiseOrImm;
1433 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1434 // $rT[0], slots 1-3 are zeroed.
1436 // FIXME: Needs to match an intrinsic pattern.
1438 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1439 "orx\t$rT, $rA, $rB", IntegerOp,
1444 class XORInst<dag OOL, dag IOL, list<dag> pattern> :
1445 RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB",
1446 IntegerOp, pattern>;
1448 class XORVecInst<ValueType vectype>:
1449 XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1450 [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA),
1451 (vectype VECREG:$rB)))]>;
1453 class XORRegInst<RegisterClass rclass>:
1454 XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1455 [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>;
1457 multiclass BitwiseExclusiveOr
1459 def v16i8: XORVecInst<v16i8>;
1460 def v8i16: XORVecInst<v8i16>;
1461 def v4i32: XORVecInst<v4i32>;
1462 def v2i64: XORVecInst<v2i64>;
1464 def r128: XORRegInst<GPRC>;
1465 def r64: XORRegInst<R64C>;
1466 def r32: XORRegInst<R32C>;
1467 def r16: XORRegInst<R16C>;
1468 def r8: XORRegInst<R8C>;
1470 // Special forms for floating point instructions.
1471 // fneg and fabs require bitwise logical ops to manipulate the sign bit.
1473 def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1474 [/* no pattern */]>;
1476 def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1477 [/* no pattern */]>;
1479 def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1480 [/* no pattern, see fneg{32,64} */]>;
1483 defm XOR : BitwiseExclusiveOr;
1485 //==----------------------------------------------------------
1487 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1488 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1489 IntegerOp, pattern>;
1491 multiclass XorByteImm
1494 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1495 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1498 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1499 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1502 defm XORBI : XorByteImm;
1505 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1506 "xorhi\t$rT, $rA, $val", IntegerOp,
1507 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1508 v8i16SExt10Imm:$val))]>;
1511 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1512 "xorhi\t$rT, $rA, $val", IntegerOp,
1513 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1516 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
1517 "xori\t$rT, $rA, $val", IntegerOp,
1518 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1519 v4i32SExt10Imm:$val))]>;
1522 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1523 "xori\t$rT, $rA, $val", IntegerOp,
1524 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1528 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1529 "nand\t$rT, $rA, $rB", IntegerOp,
1530 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1531 (v16i8 VECREG:$rB))))]>;
1534 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1535 "nand\t$rT, $rA, $rB", IntegerOp,
1536 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1537 (v8i16 VECREG:$rB))))]>;
1540 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1541 "nand\t$rT, $rA, $rB", IntegerOp,
1542 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1543 (v4i32 VECREG:$rB))))]>;
1546 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1547 "nand\t$rT, $rA, $rB", IntegerOp,
1548 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1551 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1552 "nand\t$rT, $rA, $rB", IntegerOp,
1553 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1556 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1557 "nand\t$rT, $rA, $rB", IntegerOp,
1558 [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
1562 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1563 "nor\t$rT, $rA, $rB", IntegerOp,
1564 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1565 (v16i8 VECREG:$rB))))]>;
1568 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1569 "nor\t$rT, $rA, $rB", IntegerOp,
1570 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1571 (v8i16 VECREG:$rB))))]>;
1574 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1575 "nor\t$rT, $rA, $rB", IntegerOp,
1576 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1577 (v4i32 VECREG:$rB))))]>;
1580 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1581 "nor\t$rT, $rA, $rB", IntegerOp,
1582 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1585 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1586 "nor\t$rT, $rA, $rB", IntegerOp,
1587 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1590 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1591 "nor\t$rT, $rA, $rB", IntegerOp,
1592 [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
1595 class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
1596 RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC",
1597 IntegerOp, pattern>;
1599 class SELBVecInst<ValueType vectype>:
1600 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1601 [(set (vectype VECREG:$rT),
1602 (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)),
1603 (and (vnot (vectype VECREG:$rC)),
1604 (vectype VECREG:$rA))))]>;
1606 class SELBRegInst<RegisterClass rclass>:
1607 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
1609 (or (and rclass:$rA, rclass:$rC),
1610 (and rclass:$rB, (not rclass:$rC))))]>;
1612 multiclass SelectBits
1614 def v16i8: SELBVecInst<v16i8>;
1615 def v8i16: SELBVecInst<v8i16>;
1616 def v4i32: SELBVecInst<v4i32>;
1617 def v2i64: SELBVecInst<v2i64>;
1619 def r128: SELBRegInst<GPRC>;
1620 def r64: SELBRegInst<R64C>;
1621 def r32: SELBRegInst<R32C>;
1622 def r16: SELBRegInst<R16C>;
1623 def r8: SELBRegInst<R8C>;
1626 defm SELB : SelectBits;
1628 class SPUselbPatVec<ValueType vectype, SPUInstr inst>:
1629 Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)),
1630 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1632 def : SPUselbPatVec<v16i8, SELBv16i8>;
1633 def : SPUselbPatVec<v8i16, SELBv8i16>;
1634 def : SPUselbPatVec<v4i32, SELBv4i32>;
1635 def : SPUselbPatVec<v2i64, SELBv2i64>;
1637 class SPUselbPatReg<RegisterClass rclass, SPUInstr inst>:
1638 Pat<(SPUselb rclass:$rA, rclass:$rB, rclass:$rC),
1639 (inst rclass:$rA, rclass:$rB, rclass:$rC)>;
1641 def : SPUselbPatReg<R8C, SELBr8>;
1642 def : SPUselbPatReg<R16C, SELBr16>;
1643 def : SPUselbPatReg<R32C, SELBr32>;
1644 def : SPUselbPatReg<R64C, SELBr64>;
1646 class SelectConditional<RegisterClass rclass, SPUInstr inst>:
1647 Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse),
1648 (inst rclass:$rFalse, rclass:$rTrue, rclass:$rCond)>;
1650 def : SelectConditional<R32C, SELBr32>;
1651 def : SelectConditional<R16C, SELBr16>;
1652 def : SelectConditional<R8C, SELBr8>;
1654 // EQV: Equivalence (1 for each same bit, otherwise 0)
1656 // Note: There are a lot of ways to match this bit operator and these patterns
1657 // attempt to be as exhaustive as possible.
1659 class EQVInst<dag OOL, dag IOL, list<dag> pattern>:
1660 RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB",
1661 IntegerOp, pattern>;
1663 class EQVVecInst<ValueType vectype>:
1664 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1665 [(set (vectype VECREG:$rT),
1666 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1667 (and (vnot (vectype VECREG:$rA)),
1668 (vnot (vectype VECREG:$rB)))))]>;
1670 class EQVRegInst<RegisterClass rclass>:
1671 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1672 [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB),
1673 (and (not rclass:$rA), (not rclass:$rB))))]>;
1675 class EQVVecPattern1<ValueType vectype>:
1676 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1677 [(set (vectype VECREG:$rT),
1678 (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>;
1680 class EQVRegPattern1<RegisterClass rclass>:
1681 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1682 [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>;
1684 class EQVVecPattern2<ValueType vectype>:
1685 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1686 [(set (vectype VECREG:$rT),
1687 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1688 (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>;
1690 class EQVRegPattern2<RegisterClass rclass>:
1691 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1693 (or (and rclass:$rA, rclass:$rB),
1694 (not (or rclass:$rA, rclass:$rB))))]>;
1696 class EQVVecPattern3<ValueType vectype>:
1697 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1698 [(set (vectype VECREG:$rT),
1699 (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>;
1701 class EQVRegPattern3<RegisterClass rclass>:
1702 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1703 [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>;
1705 multiclass BitEquivalence
1707 def v16i8: EQVVecInst<v16i8>;
1708 def v8i16: EQVVecInst<v8i16>;
1709 def v4i32: EQVVecInst<v4i32>;
1710 def v2i64: EQVVecInst<v2i64>;
1712 def v16i8_1: EQVVecPattern1<v16i8>;
1713 def v8i16_1: EQVVecPattern1<v8i16>;
1714 def v4i32_1: EQVVecPattern1<v4i32>;
1715 def v2i64_1: EQVVecPattern1<v2i64>;
1717 def v16i8_2: EQVVecPattern2<v16i8>;
1718 def v8i16_2: EQVVecPattern2<v8i16>;
1719 def v4i32_2: EQVVecPattern2<v4i32>;
1720 def v2i64_2: EQVVecPattern2<v2i64>;
1722 def v16i8_3: EQVVecPattern3<v16i8>;
1723 def v8i16_3: EQVVecPattern3<v8i16>;
1724 def v4i32_3: EQVVecPattern3<v4i32>;
1725 def v2i64_3: EQVVecPattern3<v2i64>;
1727 def r128: EQVRegInst<GPRC>;
1728 def r64: EQVRegInst<R64C>;
1729 def r32: EQVRegInst<R32C>;
1730 def r16: EQVRegInst<R16C>;
1731 def r8: EQVRegInst<R8C>;
1733 def r128_1: EQVRegPattern1<GPRC>;
1734 def r64_1: EQVRegPattern1<R64C>;
1735 def r32_1: EQVRegPattern1<R32C>;
1736 def r16_1: EQVRegPattern1<R16C>;
1737 def r8_1: EQVRegPattern1<R8C>;
1739 def r128_2: EQVRegPattern2<GPRC>;
1740 def r64_2: EQVRegPattern2<R64C>;
1741 def r32_2: EQVRegPattern2<R32C>;
1742 def r16_2: EQVRegPattern2<R16C>;
1743 def r8_2: EQVRegPattern2<R8C>;
1745 def r128_3: EQVRegPattern3<GPRC>;
1746 def r64_3: EQVRegPattern3<R64C>;
1747 def r32_3: EQVRegPattern3<R32C>;
1748 def r16_3: EQVRegPattern3<R16C>;
1749 def r8_3: EQVRegPattern3<R8C>;
1752 defm EQV: BitEquivalence;
1754 //===----------------------------------------------------------------------===//
1755 // Vector shuffle...
1756 //===----------------------------------------------------------------------===//
1757 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
1758 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
1759 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
1760 // the SPUISD::SHUFB opcode.
1761 //===----------------------------------------------------------------------===//
1763 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
1764 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
1765 IntegerOp, pattern>;
1767 class SHUFBVecInst<ValueType resultvec, ValueType maskvec>:
1768 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1769 [(set (resultvec VECREG:$rT),
1770 (SPUshuffle (resultvec VECREG:$rA),
1771 (resultvec VECREG:$rB),
1772 (maskvec VECREG:$rC)))]>;
1774 multiclass ShuffleBytes
1776 def v16i8 : SHUFBVecInst<v16i8, v16i8>;
1777 def v16i8_m32 : SHUFBVecInst<v16i8, v4i32>;
1778 def v8i16 : SHUFBVecInst<v8i16, v16i8>;
1779 def v8i16_m32 : SHUFBVecInst<v8i16, v4i32>;
1780 def v4i32 : SHUFBVecInst<v4i32, v16i8>;
1781 def v4i32_m32 : SHUFBVecInst<v4i32, v4i32>;
1782 def v2i64 : SHUFBVecInst<v2i64, v16i8>;
1783 def v2i64_m32 : SHUFBVecInst<v2i64, v4i32>;
1785 def v4f32 : SHUFBVecInst<v4f32, v16i8>;
1786 def v4f32_m32 : SHUFBVecInst<v4f32, v4i32>;
1788 def v2f64 : SHUFBVecInst<v2f64, v16i8>;
1789 def v2f64_m32 : SHUFBVecInst<v2f64, v4i32>;
1792 defm SHUFB : ShuffleBytes;
1794 //===----------------------------------------------------------------------===//
1795 // Shift and rotate group:
1796 //===----------------------------------------------------------------------===//
1798 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
1799 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
1800 RotateShift, pattern>;
1802 class SHLHVecInst<ValueType vectype>:
1803 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1804 [(set (vectype VECREG:$rT),
1805 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
1807 // $rB gets promoted to 32-bit register type when confronted with
1808 // this llvm assembly code:
1810 // define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
1811 // %A = shl i16 %arg1, %arg2
1815 multiclass ShiftLeftHalfword
1817 def v8i16: SHLHVecInst<v8i16>;
1818 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1819 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1820 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1821 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1824 defm SHLH : ShiftLeftHalfword;
1826 //===----------------------------------------------------------------------===//
1828 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
1829 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
1830 RotateShift, pattern>;
1832 class SHLHIVecInst<ValueType vectype>:
1833 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1834 [(set (vectype VECREG:$rT),
1835 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
1837 multiclass ShiftLeftHalfwordImm
1839 def v8i16: SHLHIVecInst<v8i16>;
1840 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
1841 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
1844 defm SHLHI : ShiftLeftHalfwordImm;
1846 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
1847 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
1849 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
1850 (SHLHIr16 R16C:$rA, uimm7:$val)>;
1852 //===----------------------------------------------------------------------===//
1854 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
1855 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
1856 RotateShift, pattern>;
1858 multiclass ShiftLeftWord
1861 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1862 [(set (v4i32 VECREG:$rT),
1863 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
1865 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1866 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
1869 defm SHL: ShiftLeftWord;
1871 //===----------------------------------------------------------------------===//
1873 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
1874 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
1875 RotateShift, pattern>;
1877 multiclass ShiftLeftWordImm
1880 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1881 [(set (v4i32 VECREG:$rT),
1882 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
1885 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
1886 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
1889 defm SHLI : ShiftLeftWordImm;
1891 //===----------------------------------------------------------------------===//
1892 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
1893 // register) to the left. Vector form is here to ensure type correctness.
1895 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
1896 // of 7 bits is actually possible.
1898 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
1899 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
1900 // bytes with SHLQBY.
1902 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
1903 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
1904 RotateShift, pattern>;
1906 class SHLQBIVecInst<ValueType vectype>:
1907 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1908 [(set (vectype VECREG:$rT),
1909 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
1911 multiclass ShiftLeftQuadByBits
1913 def v16i8: SHLQBIVecInst<v16i8>;
1914 def v8i16: SHLQBIVecInst<v8i16>;
1915 def v4i32: SHLQBIVecInst<v4i32>;
1916 def v4f32: SHLQBIVecInst<v4f32>;
1917 def v2i64: SHLQBIVecInst<v2i64>;
1918 def v2f64: SHLQBIVecInst<v2f64>;
1921 defm SHLQBI : ShiftLeftQuadByBits;
1923 // See note above on SHLQBI. In this case, the predicate actually does then
1924 // enforcement, whereas with SHLQBI, we have to "take it on faith."
1925 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
1926 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
1927 RotateShift, pattern>;
1929 class SHLQBIIVecInst<ValueType vectype>:
1930 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1931 [(set (vectype VECREG:$rT),
1932 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
1934 multiclass ShiftLeftQuadByBitsImm
1936 def v16i8 : SHLQBIIVecInst<v16i8>;
1937 def v8i16 : SHLQBIIVecInst<v8i16>;
1938 def v4i32 : SHLQBIIVecInst<v4i32>;
1939 def v4f32 : SHLQBIIVecInst<v4f32>;
1940 def v2i64 : SHLQBIIVecInst<v2i64>;
1941 def v2f64 : SHLQBIIVecInst<v2f64>;
1944 defm SHLQBII : ShiftLeftQuadByBitsImm;
1946 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
1947 // not by bits. See notes above on SHLQBI.
1949 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
1950 RI7Form<0b11111011100, OOL, IOL, "shlqby\t$rT, $rA, $rB",
1951 RotateShift, pattern>;
1953 class SHLQBYVecInst<ValueType vectype>:
1954 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1955 [(set (vectype VECREG:$rT),
1956 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
1958 multiclass ShiftLeftQuadBytes
1960 def v16i8: SHLQBYVecInst<v16i8>;
1961 def v8i16: SHLQBYVecInst<v8i16>;
1962 def v4i32: SHLQBYVecInst<v4i32>;
1963 def v4f32: SHLQBYVecInst<v4f32>;
1964 def v2i64: SHLQBYVecInst<v2i64>;
1965 def v2f64: SHLQBYVecInst<v2f64>;
1966 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
1967 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
1970 defm SHLQBY: ShiftLeftQuadBytes;
1972 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
1973 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
1974 RotateShift, pattern>;
1976 class SHLQBYIVecInst<ValueType vectype>:
1977 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1978 [(set (vectype VECREG:$rT),
1979 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
1981 multiclass ShiftLeftQuadBytesImm
1983 def v16i8: SHLQBYIVecInst<v16i8>;
1984 def v8i16: SHLQBYIVecInst<v8i16>;
1985 def v4i32: SHLQBYIVecInst<v4i32>;
1986 def v4f32: SHLQBYIVecInst<v4f32>;
1987 def v2i64: SHLQBYIVecInst<v2i64>;
1988 def v2f64: SHLQBYIVecInst<v2f64>;
1989 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
1991 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
1994 defm SHLQBYI : ShiftLeftQuadBytesImm;
1996 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1998 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1999 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
2000 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
2001 RotateShift, pattern>;
2003 class ROTHVecInst<ValueType vectype>:
2004 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2005 [(set (vectype VECREG:$rT),
2006 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
2008 class ROTHRegInst<RegisterClass rclass>:
2009 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2010 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
2012 multiclass RotateLeftHalfword
2014 def v8i16: ROTHVecInst<v8i16>;
2015 def r16: ROTHRegInst<R16C>;
2018 defm ROTH: RotateLeftHalfword;
2020 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2021 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2023 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2024 // Rotate halfword, immediate:
2025 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2026 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
2027 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
2028 RotateShift, pattern>;
2030 class ROTHIVecInst<ValueType vectype>:
2031 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2032 [(set (vectype VECREG:$rT),
2033 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
2035 multiclass RotateLeftHalfwordImm
2037 def v8i16: ROTHIVecInst<v8i16>;
2038 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2039 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2040 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2041 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2044 defm ROTHI: RotateLeftHalfwordImm;
2046 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
2047 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2049 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2051 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2053 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
2054 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
2055 RotateShift, pattern>;
2057 class ROTVecInst<ValueType vectype>:
2058 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2059 [(set (vectype VECREG:$rT),
2060 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
2062 class ROTRegInst<RegisterClass rclass>:
2063 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2065 (rotl rclass:$rA, R32C:$rB))]>;
2067 multiclass RotateLeftWord
2069 def v4i32: ROTVecInst<v4i32>;
2070 def r32: ROTRegInst<R32C>;
2073 defm ROT: RotateLeftWord;
2075 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2077 def ROTr32_r16_anyext:
2078 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2079 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2081 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
2082 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2084 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
2085 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2087 def ROTr32_r8_anyext:
2088 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2089 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2091 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
2092 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2094 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
2095 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2097 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2098 // Rotate word, immediate
2099 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2101 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
2102 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
2103 RotateShift, pattern>;
2105 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
2106 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2107 [(set (vectype VECREG:$rT),
2108 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2110 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2111 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2112 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2114 multiclass RotateLeftWordImm
2116 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2117 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
2118 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
2120 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
2121 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
2122 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
2125 defm ROTI : RotateLeftWordImm;
2127 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2128 // Rotate quad by byte (count)
2129 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2131 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2132 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2133 RotateShift, pattern>;
2135 class ROTQBYVecInst<ValueType vectype>:
2136 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2137 [(set (vectype VECREG:$rT),
2138 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2140 multiclass RotateQuadLeftByBytes
2142 def v16i8: ROTQBYVecInst<v16i8>;
2143 def v8i16: ROTQBYVecInst<v8i16>;
2144 def v4i32: ROTQBYVecInst<v4i32>;
2145 def v2i64: ROTQBYVecInst<v2i64>;
2148 defm ROTQBY: RotateQuadLeftByBytes;
2150 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
2151 (ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
2152 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
2153 (ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
2154 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
2155 (ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
2156 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
2157 (ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
2159 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2160 // Rotate quad by byte (count), immediate
2161 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2163 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2164 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2165 RotateShift, pattern>;
2167 class ROTQBYIVecInst<ValueType vectype>:
2168 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2169 [(set (vectype VECREG:$rT),
2170 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2172 multiclass RotateQuadByBytesImm
2174 def v16i8: ROTQBYIVecInst<v16i8>;
2175 def v8i16: ROTQBYIVecInst<v8i16>;
2176 def v4i32: ROTQBYIVecInst<v4i32>;
2177 def v2i64: ROTQBYIVecInst<v2i64>;
2180 defm ROTQBYI: RotateQuadByBytesImm;
2182 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2183 (ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
2184 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2185 (ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
2186 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2187 (ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
2188 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
2189 (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
2191 // See ROTQBY note above.
2192 class ROTQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2193 RI7Form<0b00110011100, OOL, IOL,
2194 "rotqbybi\t$rT, $rA, $shift",
2195 RotateShift, pattern>;
2197 class ROTQBYBIVecInst<ValueType vectype, RegisterClass rclass>:
2198 ROTQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, rclass:$shift),
2199 [(set (vectype VECREG:$rT),
2200 (SPUrotbytes_left_bits (vectype VECREG:$rA), rclass:$shift))]>;
2202 multiclass RotateQuadByBytesByBitshift {
2203 def v16i8_r32: ROTQBYBIVecInst<v16i8, R32C>;
2204 def v8i16_r32: ROTQBYBIVecInst<v8i16, R32C>;
2205 def v4i32_r32: ROTQBYBIVecInst<v4i32, R32C>;
2206 def v2i64_r32: ROTQBYBIVecInst<v2i64, R32C>;
2209 defm ROTQBYBI : RotateQuadByBytesByBitshift;
2211 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2212 // See ROTQBY note above.
2214 // Assume that the user of this instruction knows to shift the rotate count
2216 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2218 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2219 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2220 RotateShift, pattern>;
2222 class ROTQBIVecInst<ValueType vectype>:
2223 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2224 [/* no pattern yet */]>;
2226 class ROTQBIRegInst<RegisterClass rclass>:
2227 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2228 [/* no pattern yet */]>;
2230 multiclass RotateQuadByBitCount
2232 def v16i8: ROTQBIVecInst<v16i8>;
2233 def v8i16: ROTQBIVecInst<v8i16>;
2234 def v4i32: ROTQBIVecInst<v4i32>;
2235 def v2i64: ROTQBIVecInst<v2i64>;
2237 def r128: ROTQBIRegInst<GPRC>;
2238 def r64: ROTQBIRegInst<R64C>;
2241 defm ROTQBI: RotateQuadByBitCount;
2243 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2244 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2245 RotateShift, pattern>;
2247 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2249 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2250 [/* no pattern yet */]>;
2252 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2254 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2255 [/* no pattern yet */]>;
2257 multiclass RotateQuadByBitCountImm
2259 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2260 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2261 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2262 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2264 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2265 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2268 defm ROTQBII : RotateQuadByBitCountImm;
2270 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2271 // ROTHM v8i16 form:
2272 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2273 // so this only matches a synthetically generated/lowered code
2275 // NOTE(2): $rB must be negated before the right rotate!
2276 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2278 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2279 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2280 RotateShift, pattern>;
2283 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2284 [/* see patterns below - $rB must be negated */]>;
2286 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2287 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2289 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2290 (ROTHMv8i16 VECREG:$rA,
2291 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2293 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2294 (ROTHMv8i16 VECREG:$rA,
2295 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2297 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2298 // Note: This instruction doesn't match a pattern because rB must be negated
2299 // for the instruction to work. Thus, the pattern below the instruction!
2302 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2303 [/* see patterns below - $rB must be negated! */]>;
2305 def : Pat<(srl R16C:$rA, R32C:$rB),
2306 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2308 def : Pat<(srl R16C:$rA, R16C:$rB),
2310 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2312 def : Pat<(srl R16C:$rA, R8C:$rB),
2314 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2316 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2317 // that the immediate can be complemented, so that the user doesn't have to
2320 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2321 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2322 RotateShift, pattern>;
2325 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2326 [/* no pattern */]>;
2328 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2329 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2331 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2332 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2334 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2335 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2338 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2339 [/* no pattern */]>;
2341 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2342 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2344 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2345 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2347 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2348 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2350 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2351 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2352 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2353 RotateShift, pattern>;
2356 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2357 [/* see patterns below - $rB must be negated */]>;
2359 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
2360 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2362 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
2363 (ROTMv4i32 VECREG:$rA,
2364 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2366 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
2367 (ROTMv4i32 VECREG:$rA,
2368 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2371 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2372 [/* see patterns below - $rB must be negated */]>;
2374 def : Pat<(srl R32C:$rA, R32C:$rB),
2375 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2377 def : Pat<(srl R32C:$rA, R16C:$rB),
2379 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2381 def : Pat<(srl R32C:$rA, R8C:$rB),
2383 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2385 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2387 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2388 "rotmi\t$rT, $rA, $val", RotateShift,
2389 [(set (v4i32 VECREG:$rT),
2390 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2392 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
2393 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2395 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
2396 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2398 // ROTMI r32 form: know how to complement the immediate value.
2400 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2401 "rotmi\t$rT, $rA, $val", RotateShift,
2402 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2404 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2405 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2407 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2408 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2410 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2411 // ROTQMBYvec: This is a vector form merely so that when used in an
2412 // instruction pattern, type checking will succeed. This instruction assumes
2413 // that the user knew to negate $rB.
2415 // Using the SPUrotquad_rz_bytes target-specific DAG node, the patterns
2416 // ensure that $rB is negated.
2417 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2419 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2420 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2421 RotateShift, pattern>;
2423 class ROTQMBYVecInst<ValueType vectype>:
2424 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2425 [/* no pattern, $rB must be negated */]>;
2427 class ROTQMBYRegInst<RegisterClass rclass>:
2428 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2430 (SPUrotquad_rz_bytes rclass:$rA, R32C:$rB))]>;
2432 multiclass RotateQuadBytes
2434 def v16i8: ROTQMBYVecInst<v16i8>;
2435 def v8i16: ROTQMBYVecInst<v8i16>;
2436 def v4i32: ROTQMBYVecInst<v4i32>;
2437 def v2i64: ROTQMBYVecInst<v2i64>;
2439 def r128: ROTQMBYRegInst<GPRC>;
2440 def r64: ROTQMBYRegInst<R64C>;
2443 defm ROTQMBY : RotateQuadBytes;
2445 def : Pat<(SPUrotquad_rz_bytes (v16i8 VECREG:$rA), R32C:$rB),
2446 (ROTQMBYv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2447 def : Pat<(SPUrotquad_rz_bytes (v8i16 VECREG:$rA), R32C:$rB),
2448 (ROTQMBYv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2449 def : Pat<(SPUrotquad_rz_bytes (v4i32 VECREG:$rA), R32C:$rB),
2450 (ROTQMBYv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2451 def : Pat<(SPUrotquad_rz_bytes (v2i64 VECREG:$rA), R32C:$rB),
2452 (ROTQMBYv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2453 def : Pat<(SPUrotquad_rz_bytes GPRC:$rA, R32C:$rB),
2454 (ROTQMBYr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2455 def : Pat<(SPUrotquad_rz_bytes R64C:$rA, R32C:$rB),
2456 (ROTQMBYr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2458 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2459 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2460 RotateShift, pattern>;
2462 class ROTQMBYIVecInst<ValueType vectype>:
2463 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2464 [(set (vectype VECREG:$rT),
2465 (SPUrotquad_rz_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2467 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2468 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2470 (SPUrotquad_rz_bytes rclass:$rA, (inttype pred:$val)))]>;
2472 multiclass RotateQuadBytesImm
2474 def v16i8: ROTQMBYIVecInst<v16i8>;
2475 def v8i16: ROTQMBYIVecInst<v8i16>;
2476 def v4i32: ROTQMBYIVecInst<v4i32>;
2477 def v2i64: ROTQMBYIVecInst<v2i64>;
2479 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2480 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2483 defm ROTQMBYI : RotateQuadBytesImm;
2485 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2486 // Rotate right and mask by bit count
2487 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2489 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2490 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2491 RotateShift, pattern>;
2493 class ROTQMBYBIVecInst<ValueType vectype>:
2494 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2495 [/* no pattern, intrinsic? */]>;
2497 multiclass RotateMaskQuadByBitCount
2499 def v16i8: ROTQMBYBIVecInst<v16i8>;
2500 def v8i16: ROTQMBYBIVecInst<v8i16>;
2501 def v4i32: ROTQMBYBIVecInst<v4i32>;
2502 def v2i64: ROTQMBYBIVecInst<v2i64>;
2505 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2507 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2508 // Rotate quad and mask by bits
2509 // Note that the rotate amount has to be negated
2510 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2512 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2513 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2514 RotateShift, pattern>;
2516 class ROTQMBIVecInst<ValueType vectype>:
2517 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2518 [/* no pattern */]>;
2520 class ROTQMBIRegInst<RegisterClass rclass>:
2521 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2522 [/* no pattern */]>;
2524 multiclass RotateMaskQuadByBits
2526 def v16i8: ROTQMBIVecInst<v16i8>;
2527 def v8i16: ROTQMBIVecInst<v8i16>;
2528 def v4i32: ROTQMBIVecInst<v4i32>;
2529 def v2i64: ROTQMBIVecInst<v2i64>;
2531 def r128: ROTQMBIRegInst<GPRC>;
2532 def r64: ROTQMBIRegInst<R64C>;
2535 defm ROTQMBI: RotateMaskQuadByBits;
2537 def : Pat<(SPUrotquad_rz_bits (v16i8 VECREG:$rA), R32C:$rB),
2538 (ROTQMBIv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2539 def : Pat<(SPUrotquad_rz_bits (v8i16 VECREG:$rA), R32C:$rB),
2540 (ROTQMBIv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2541 def : Pat<(SPUrotquad_rz_bits (v4i32 VECREG:$rA), R32C:$rB),
2542 (ROTQMBIv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2543 def : Pat<(SPUrotquad_rz_bits (v2i64 VECREG:$rA), R32C:$rB),
2544 (ROTQMBIv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2545 def : Pat<(SPUrotquad_rz_bits GPRC:$rA, R32C:$rB),
2546 (ROTQMBIr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2547 def : Pat<(SPUrotquad_rz_bits R64C:$rA, R32C:$rB),
2548 (ROTQMBIr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2550 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2551 // Rotate quad and mask by bits, immediate
2552 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2554 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2555 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2556 RotateShift, pattern>;
2558 class ROTQMBIIVecInst<ValueType vectype>:
2559 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2560 [(set (vectype VECREG:$rT),
2561 (SPUrotquad_rz_bits (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2563 class ROTQMBIIRegInst<RegisterClass rclass>:
2564 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2566 (SPUrotquad_rz_bits rclass:$rA, (i32 uimm7:$val)))]>;
2568 multiclass RotateMaskQuadByBitsImm
2570 def v16i8: ROTQMBIIVecInst<v16i8>;
2571 def v8i16: ROTQMBIIVecInst<v8i16>;
2572 def v4i32: ROTQMBIIVecInst<v4i32>;
2573 def v2i64: ROTQMBIIVecInst<v2i64>;
2575 def r128: ROTQMBIIRegInst<GPRC>;
2576 def r64: ROTQMBIIRegInst<R64C>;
2579 defm ROTQMBII: RotateMaskQuadByBitsImm;
2581 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2582 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2585 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2586 "rotmah\t$rT, $rA, $rB", RotateShift,
2587 [/* see patterns below - $rB must be negated */]>;
2589 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2590 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2592 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2593 (ROTMAHv8i16 VECREG:$rA,
2594 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2596 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2597 (ROTMAHv8i16 VECREG:$rA,
2598 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2601 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2602 "rotmah\t$rT, $rA, $rB", RotateShift,
2603 [/* see patterns below - $rB must be negated */]>;
2605 def : Pat<(sra R16C:$rA, R32C:$rB),
2606 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2608 def : Pat<(sra R16C:$rA, R16C:$rB),
2609 (ROTMAHr16 R16C:$rA,
2610 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2612 def : Pat<(sra R16C:$rA, R8C:$rB),
2613 (ROTMAHr16 R16C:$rA,
2614 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2617 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2618 "rotmahi\t$rT, $rA, $val", RotateShift,
2619 [(set (v8i16 VECREG:$rT),
2620 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2622 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2623 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2625 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2626 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2629 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2630 "rotmahi\t$rT, $rA, $val", RotateShift,
2631 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2633 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2634 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2636 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2637 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2640 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2641 "rotma\t$rT, $rA, $rB", RotateShift,
2642 [/* see patterns below - $rB must be negated */]>;
2644 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2645 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2647 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2648 (ROTMAv4i32 (v4i32 VECREG:$rA),
2649 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2651 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2652 (ROTMAv4i32 (v4i32 VECREG:$rA),
2653 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2656 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2657 "rotma\t$rT, $rA, $rB", RotateShift,
2658 [/* see patterns below - $rB must be negated */]>;
2660 def : Pat<(sra R32C:$rA, R32C:$rB),
2661 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2663 def : Pat<(sra R32C:$rA, R16C:$rB),
2665 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2667 def : Pat<(sra R32C:$rA, R8C:$rB),
2669 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2671 class ROTMAIInst<dag OOL, dag IOL, list<dag> pattern>:
2672 RRForm<0b01011110000, OOL, IOL,
2673 "rotmai\t$rT, $rA, $val",
2674 RotateShift, pattern>;
2676 class ROTMAIVecInst<ValueType vectype, Operand intop, ValueType inttype>:
2677 ROTMAIInst<(outs VECREG:$rT), (ins VECREG:$rA, intop:$val),
2678 [(set (vectype VECREG:$rT),
2679 (SPUvec_sra VECREG:$rA, (inttype uimm7:$val)))]>;
2681 class ROTMAIRegInst<RegisterClass rclass, Operand intop, ValueType inttype>:
2682 ROTMAIInst<(outs rclass:$rT), (ins rclass:$rA, intop:$val),
2683 [(set rclass:$rT, (sra rclass:$rA, (inttype uimm7:$val)))]>;
2685 multiclass RotateMaskAlgebraicImm {
2686 def v2i64_i32 : ROTMAIVecInst<v2i64, rotNeg7imm, i32>;
2687 def v4i32_i32 : ROTMAIVecInst<v4i32, rotNeg7imm, i32>;
2688 def r64_i32 : ROTMAIRegInst<R64C, rotNeg7imm, i32>;
2689 def r32_i32 : ROTMAIRegInst<R32C, rotNeg7imm, i32>;
2692 defm ROTMAI : RotateMaskAlgebraicImm;
2694 //===----------------------------------------------------------------------===//
2695 // Branch and conditionals:
2696 //===----------------------------------------------------------------------===//
2698 let isTerminator = 1, isBarrier = 1 in {
2699 // Halt If Equal (r32 preferred slot only, no vector form)
2701 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2702 "heq\t$rA, $rB", BranchResolv,
2703 [/* no pattern to match */]>;
2706 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2707 "heqi\t$rA, $val", BranchResolv,
2708 [/* no pattern to match */]>;
2710 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2711 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2713 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2714 "hgt\t$rA, $rB", BranchResolv,
2715 [/* no pattern to match */]>;
2718 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2719 "hgti\t$rA, $val", BranchResolv,
2720 [/* no pattern to match */]>;
2723 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2724 "hlgt\t$rA, $rB", BranchResolv,
2725 [/* no pattern to match */]>;
2728 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2729 "hlgti\t$rA, $val", BranchResolv,
2730 [/* no pattern to match */]>;
2733 //------------------------------------------------------------------------
2734 // Comparison operators:
2735 //------------------------------------------------------------------------
2737 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
2738 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
2741 multiclass CmpEqualByte
2744 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2745 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2746 (v8i16 VECREG:$rB)))]>;
2749 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2750 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
2753 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
2754 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
2757 multiclass CmpEqualByteImm
2760 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2761 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
2762 v16i8SExt8Imm:$val))]>;
2764 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2765 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
2768 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
2769 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
2772 multiclass CmpEqualHalfword
2774 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2775 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2776 (v8i16 VECREG:$rB)))]>;
2778 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2779 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
2782 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
2783 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
2786 multiclass CmpEqualHalfwordImm
2788 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2789 [(set (v8i16 VECREG:$rT),
2790 (seteq (v8i16 VECREG:$rA),
2791 (v8i16 v8i16SExt10Imm:$val)))]>;
2792 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2793 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
2796 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
2797 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
2800 multiclass CmpEqualWord
2802 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2803 [(set (v4i32 VECREG:$rT),
2804 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2806 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2807 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2810 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
2811 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
2814 multiclass CmpEqualWordImm
2816 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2817 [(set (v4i32 VECREG:$rT),
2818 (seteq (v4i32 VECREG:$rA),
2819 (v4i32 v4i32SExt16Imm:$val)))]>;
2821 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2822 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2825 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2826 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
2829 multiclass CmpGtrByte
2832 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2833 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2834 (v8i16 VECREG:$rB)))]>;
2837 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2838 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
2841 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2842 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
2845 multiclass CmpGtrByteImm
2848 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2849 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
2850 v16i8SExt8Imm:$val))]>;
2852 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2853 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
2856 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2857 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
2860 multiclass CmpGtrHalfword
2862 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2863 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2864 (v8i16 VECREG:$rB)))]>;
2866 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2867 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
2870 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2871 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
2874 multiclass CmpGtrHalfwordImm
2876 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2877 [(set (v8i16 VECREG:$rT),
2878 (setgt (v8i16 VECREG:$rA),
2879 (v8i16 v8i16SExt10Imm:$val)))]>;
2880 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2881 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
2884 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
2885 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
2888 multiclass CmpGtrWord
2890 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2891 [(set (v4i32 VECREG:$rT),
2892 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2894 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2895 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
2898 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2899 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
2902 multiclass CmpGtrWordImm
2904 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2905 [(set (v4i32 VECREG:$rT),
2906 (setgt (v4i32 VECREG:$rA),
2907 (v4i32 v4i32SExt16Imm:$val)))]>;
2909 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2910 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
2913 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2914 RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB",
2917 multiclass CmpLGtrByte
2920 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2921 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2922 (v8i16 VECREG:$rB)))]>;
2925 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2926 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
2929 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2930 RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val",
2933 multiclass CmpLGtrByteImm
2936 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2937 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
2938 v16i8SExt8Imm:$val))]>;
2940 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2941 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
2944 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2945 RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB",
2948 multiclass CmpLGtrHalfword
2950 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2951 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2952 (v8i16 VECREG:$rB)))]>;
2954 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2955 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
2958 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2959 RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val",
2962 multiclass CmpLGtrHalfwordImm
2964 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2965 [(set (v8i16 VECREG:$rT),
2966 (setugt (v8i16 VECREG:$rA),
2967 (v8i16 v8i16SExt10Imm:$val)))]>;
2968 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2969 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
2972 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
2973 RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB",
2976 multiclass CmpLGtrWord
2978 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2979 [(set (v4i32 VECREG:$rT),
2980 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2982 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2983 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
2986 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2987 RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val",
2990 multiclass CmpLGtrWordImm
2992 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2993 [(set (v4i32 VECREG:$rT),
2994 (setugt (v4i32 VECREG:$rA),
2995 (v4i32 v4i32SExt16Imm:$val)))]>;
2997 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2998 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
3001 defm CEQB : CmpEqualByte;
3002 defm CEQBI : CmpEqualByteImm;
3003 defm CEQH : CmpEqualHalfword;
3004 defm CEQHI : CmpEqualHalfwordImm;
3005 defm CEQ : CmpEqualWord;
3006 defm CEQI : CmpEqualWordImm;
3007 defm CGTB : CmpGtrByte;
3008 defm CGTBI : CmpGtrByteImm;
3009 defm CGTH : CmpGtrHalfword;
3010 defm CGTHI : CmpGtrHalfwordImm;
3011 defm CGT : CmpGtrWord;
3012 defm CGTI : CmpGtrWordImm;
3013 defm CLGTB : CmpLGtrByte;
3014 defm CLGTBI : CmpLGtrByteImm;
3015 defm CLGTH : CmpLGtrHalfword;
3016 defm CLGTHI : CmpLGtrHalfwordImm;
3017 defm CLGT : CmpLGtrWord;
3018 defm CLGTI : CmpLGtrWordImm;
3020 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3021 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
3022 // define a pattern to generate the right code, as a binary operator
3023 // (in a manner of speaking.)
3025 // N.B.: This only matches the setcc set of conditionals. Special pattern
3026 // matching is used for select conditionals.
3027 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3029 class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3030 SPUInstr xorinst, SPUInstr cmpare>:
3031 Pat<(cond rclass:$rA, rclass:$rB),
3032 (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
3034 class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3035 PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
3036 Pat<(cond rclass:$rA, (inttype immpred:$imm)),
3037 (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
3039 def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
3040 def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
3042 def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
3043 def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
3045 def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
3046 def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
3048 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
3049 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3050 Pat<(cond rclass:$rA, rclass:$rB),
3051 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3052 (cmpOp2 rclass:$rA, rclass:$rB))>;
3054 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3056 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3057 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
3058 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
3059 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
3061 def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
3062 def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
3063 def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
3064 def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
3065 def : Pat<(setle R8C:$rA, R8C:$rB),
3066 (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3067 def : Pat<(setle R8C:$rA, immU8:$imm),
3068 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3070 def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
3071 def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
3072 ORr16, CGTHIr16, CEQHIr16>;
3073 def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
3074 def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
3075 def : Pat<(setle R16C:$rA, R16C:$rB),
3076 (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3077 def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
3078 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3080 def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
3081 def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
3082 ORr32, CGTIr32, CEQIr32>;
3083 def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
3084 def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
3085 def : Pat<(setle R32C:$rA, R32C:$rB),
3086 (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3087 def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
3088 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3090 def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
3091 def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
3092 def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
3093 def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
3094 def : Pat<(setule R8C:$rA, R8C:$rB),
3095 (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3096 def : Pat<(setule R8C:$rA, immU8:$imm),
3097 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3099 def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
3100 def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
3101 ORr16, CLGTHIr16, CEQHIr16>;
3102 def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
3103 def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
3104 CLGTHIr16, CEQHIr16>;
3105 def : Pat<(setule R16C:$rA, R16C:$rB),
3106 (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3107 def : Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
3108 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3110 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
3111 def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
3112 ORr32, CLGTIr32, CEQIr32>;
3113 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
3114 def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
3115 def : Pat<(setule R32C:$rA, R32C:$rB),
3116 (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3117 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
3118 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3120 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3121 // select conditional patterns:
3122 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3124 class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3125 SPUInstr selinstr, SPUInstr cmpare>:
3126 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3127 rclass:$rTrue, rclass:$rFalse),
3128 (selinstr rclass:$rTrue, rclass:$rFalse,
3129 (cmpare rclass:$rA, rclass:$rB))>;
3131 class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3132 PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
3133 Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
3134 rclass:$rTrue, rclass:$rFalse),
3135 (selinstr rclass:$rTrue, rclass:$rFalse,
3136 (cmpare rclass:$rA, immpred:$imm))>;
3138 def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
3139 def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
3140 def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
3141 def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
3142 def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
3143 def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
3145 def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
3146 def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
3147 def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
3148 def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
3149 def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
3150 def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
3152 def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
3153 def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
3154 def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
3155 def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
3156 def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
3157 def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
3159 class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3160 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3162 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3163 rclass:$rFalse, rclass:$rTrue),
3164 (selinstr rclass:$rTrue, rclass:$rFalse,
3165 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3166 (cmpOp2 rclass:$rA, rclass:$rB)))>;
3168 class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3170 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3172 Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
3173 rclass:$rTrue, rclass:$rFalse),
3174 (selinstr rclass:$rFalse, rclass:$rTrue,
3175 (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
3176 (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
3178 def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
3179 def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
3180 SELBr8, ORr8, CGTBIr8, CEQBIr8>;
3182 def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
3183 def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
3184 SELBr16, ORr16, CGTHIr16, CEQHIr16>;
3186 def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
3187 def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
3188 SELBr32, ORr32, CGTIr32, CEQIr32>;
3190 def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
3191 def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
3192 SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
3194 def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
3195 def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
3196 SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
3198 def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
3199 def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
3200 SELBr32, ORr32, CLGTIr32, CEQIr32>;
3202 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3205 // All calls clobber the non-callee-saved registers:
3206 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
3207 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
3208 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
3209 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
3210 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
3211 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
3212 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
3213 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
3214 // All of these instructions use $lr (aka $0)
3216 // Branch relative and set link: Used if we actually know that the target
3217 // is within [-32768, 32767] bytes of the target
3219 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
3220 "brsl\t$$lr, $func",
3221 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
3223 // Branch absolute and set link: Used if we actually know that the target
3224 // is an absolute address
3226 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
3227 "brasl\t$$lr, $func",
3228 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
3230 // Branch indirect and set link if external data. These instructions are not
3231 // actually generated, matched by an intrinsic:
3232 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
3233 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
3234 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
3235 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
3237 // Branch indirect and set link. This is the "X-form" address version of a
3240 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
3243 // Unconditional branches:
3244 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
3246 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3250 // Unconditional, absolute address branch
3252 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3254 [/* no pattern */]>;
3258 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3260 // Various branches:
3262 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
3263 "brnz\t$rCond,$dest",
3265 [(brcond R32C:$rCond, bb:$dest)]>;
3268 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
3271 [/* no pattern */]>;
3274 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
3275 "brhnz\t$rCond,$dest",
3277 [(brcond R16C:$rCond, bb:$dest)]>;
3280 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
3283 [/* no pattern */]>;
3287 BICondForm<0b10010100100, "binz\t$rA, $func",
3288 [(SPUbinz R32C:$rA, R32C:$func)]>;
3291 BICondForm<0b00010100100, "biz\t$rA, $func",
3292 [(SPUbiz R32C:$rA, R32C:$func)]>;
3296 //===----------------------------------------------------------------------===//
3297 // setcc and brcond patterns:
3298 //===----------------------------------------------------------------------===//
3300 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3301 (BRHZ R16C:$rA, bb:$dest)>;
3302 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3303 (BRHNZ R16C:$rA, bb:$dest)>;
3305 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3306 (BRZ R32C:$rA, bb:$dest)>;
3307 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3308 (BRNZ R32C:$rA, bb:$dest)>;
3310 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3312 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3313 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3315 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3316 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3318 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3319 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3321 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3322 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3325 defm BRCONDeq : BranchCondEQ<seteq, BRHZ, BRZ>;
3326 defm BRCONDne : BranchCondEQ<setne, BRHNZ, BRNZ>;
3328 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3330 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3331 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3333 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3334 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3336 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3337 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3339 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3340 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3343 defm BRCONDugt : BranchCondLGT<setugt, BRHNZ, BRNZ>;
3344 defm BRCONDule : BranchCondLGT<setule, BRHZ, BRZ>;
3346 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3347 SPUInstr orinst32, SPUInstr brinst32>
3349 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3350 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3351 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3354 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3355 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3356 (CEQHr16 R16C:$rA, R16:$rB)),
3359 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3360 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3361 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3364 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3365 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3366 (CEQr32 R32C:$rA, R32C:$rB)),
3370 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZ, ORr32, BRNZ>;
3371 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZ, ORr32, BRZ>;
3373 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3375 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3376 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3378 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3379 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3381 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3382 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3384 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3385 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3388 defm BRCONDgt : BranchCondGT<setgt, BRHNZ, BRNZ>;
3389 defm BRCONDle : BranchCondGT<setle, BRHZ, BRZ>;
3391 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3392 SPUInstr orinst32, SPUInstr brinst32>
3394 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3395 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3396 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3399 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3400 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3401 (CEQHr16 R16C:$rA, R16:$rB)),
3404 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3405 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3406 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3409 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3410 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3411 (CEQr32 R32C:$rA, R32C:$rB)),
3415 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZ, ORr32, BRNZ>;
3416 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZ, ORr32, BRZ>;
3418 let isTerminator = 1, isBarrier = 1 in {
3419 let isReturn = 1 in {
3421 RETForm<"bi\t$$lr", [(retflag)]>;
3425 //===----------------------------------------------------------------------===//
3426 // Single precision floating point instructions
3427 //===----------------------------------------------------------------------===//
3430 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3431 "fa\t$rT, $rA, $rB", SPrecFP,
3432 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3435 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3436 "fa\t$rT, $rA, $rB", SPrecFP,
3437 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3440 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3441 "fs\t$rT, $rA, $rB", SPrecFP,
3442 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3445 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3446 "fs\t$rT, $rA, $rB", SPrecFP,
3447 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3449 // Floating point reciprocal estimate
3451 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
3452 "frest\t$rT, $rA", SPrecFP,
3453 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
3456 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
3457 "frest\t$rT, $rA", SPrecFP,
3458 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
3460 // Floating point interpolate (used in conjunction with reciprocal estimate)
3462 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3463 "fi\t$rT, $rA, $rB", SPrecFP,
3464 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
3465 (v4f32 VECREG:$rB)))]>;
3468 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3469 "fi\t$rT, $rA, $rB", SPrecFP,
3470 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
3472 //--------------------------------------------------------------------------
3473 // Basic single precision floating point comparisons:
3475 // Note: There is no support on SPU for single precision NaN. Consequently,
3476 // ordered and unordered comparisons are the same.
3477 //--------------------------------------------------------------------------
3480 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3481 "fceq\t$rT, $rA, $rB", SPrecFP,
3482 [(set R32C:$rT, (setueq R32FP:$rA, R32FP:$rB))]>;
3484 def : Pat<(setoeq R32FP:$rA, R32FP:$rB),
3485 (FCEQf32 R32FP:$rA, R32FP:$rB)>;
3488 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3489 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3490 [(set R32C:$rT, (setueq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3492 def : Pat<(setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)),
3493 (FCMEQf32 R32FP:$rA, R32FP:$rB)>;
3496 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3497 "fcgt\t$rT, $rA, $rB", SPrecFP,
3498 [(set R32C:$rT, (setugt R32FP:$rA, R32FP:$rB))]>;
3500 def : Pat<(setugt R32FP:$rA, R32FP:$rB),
3501 (FCGTf32 R32FP:$rA, R32FP:$rB)>;
3504 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3505 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3506 [(set R32C:$rT, (setugt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3508 def : Pat<(setugt (fabs R32FP:$rA), (fabs R32FP:$rB)),
3509 (FCMGTf32 R32FP:$rA, R32FP:$rB)>;
3511 //--------------------------------------------------------------------------
3512 // Single precision floating point comparisons and SETCC equivalents:
3513 //--------------------------------------------------------------------------
3515 def : SETCCNegCondReg<setune, R32FP, i32, XORIr32, FCEQf32>;
3516 def : SETCCNegCondReg<setone, R32FP, i32, XORIr32, FCEQf32>;
3518 def : SETCCBinOpReg<setuge, R32FP, ORr32, FCGTf32, FCEQf32>;
3519 def : SETCCBinOpReg<setoge, R32FP, ORr32, FCGTf32, FCEQf32>;
3521 def : SETCCBinOpReg<setult, R32FP, NORr32, FCGTf32, FCEQf32>;
3522 def : SETCCBinOpReg<setolt, R32FP, NORr32, FCGTf32, FCEQf32>;
3524 def : Pat<(setule R32FP:$rA, R32FP:$rB),
3525 (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
3526 def : Pat<(setole R32FP:$rA, R32FP:$rB),
3527 (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
3529 // FP Status and Control Register Write
3530 // Why isn't rT a don't care in the ISA?
3531 // Should we create a special RRForm_3 for this guy and zero out the rT?
3533 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3534 "fscrwr\t$rA", SPrecFP,
3535 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3537 // FP Status and Control Register Read
3539 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3540 "fscrrd\t$rT", SPrecFP,
3541 [/* This instruction requires an intrinsic */]>;
3543 // llvm instruction space
3544 // How do these map onto cell instructions?
3546 // frest rC rB # c = 1/b (both lines)
3548 // fm rD rA rC # d = a * 1/b
3549 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3550 // fma rB rB rC rD # b = b * c + d
3551 // = -(d *b -a) * c + d
3552 // = a * c - c ( a *b *c - a)
3557 // These llvm instructions will actually map to library calls.
3558 // All that's needed, then, is to check that the appropriate library is
3559 // imported and do a brsl to the proper function name.
3560 // frem # fmod(x, y): x - (x/y) * y
3561 // (Note: fmod(double, double), fmodf(float,float)
3565 // Unimplemented SPU instruction space
3566 // floating reciprocal absolute square root estimate (frsqest)
3568 // The following are probably just intrinsics
3569 // status and control register write
3570 // status and control register read
3572 //--------------------------------------
3573 // Floating point multiply instructions
3574 //--------------------------------------
3577 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3578 "fm\t$rT, $rA, $rB", SPrecFP,
3579 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
3580 (v4f32 VECREG:$rB)))]>;
3583 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3584 "fm\t$rT, $rA, $rB", SPrecFP,
3585 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
3587 // Floating point multiply and add
3588 // e.g. d = c + (a * b)
3590 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3591 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3592 [(set (v4f32 VECREG:$rT),
3593 (fadd (v4f32 VECREG:$rC),
3594 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
3597 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3598 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3599 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3601 // FP multiply and subtract
3602 // Subtracts value in rC from product
3605 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3606 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3607 [(set (v4f32 VECREG:$rT),
3608 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
3609 (v4f32 VECREG:$rC)))]>;
3612 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3613 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3615 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
3617 // Floating Negative Mulitply and Subtract
3618 // Subtracts product from value in rC
3619 // res = fneg(fms a b c)
3622 // NOTE: subtraction order
3626 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3627 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3628 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3631 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3632 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3633 [(set (v4f32 VECREG:$rT),
3634 (fsub (v4f32 VECREG:$rC),
3635 (fmul (v4f32 VECREG:$rA),
3636 (v4f32 VECREG:$rB))))]>;
3638 //--------------------------------------
3639 // Floating Point Conversions
3640 // Signed conversions:
3642 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3643 "csflt\t$rT, $rA, 0", SPrecFP,
3644 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
3646 // Convert signed integer to floating point
3648 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
3649 "csflt\t$rT, $rA, 0", SPrecFP,
3650 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
3652 // Convert unsigned into to float
3654 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3655 "cuflt\t$rT, $rA, 0", SPrecFP,
3656 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
3659 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
3660 "cuflt\t$rT, $rA, 0", SPrecFP,
3661 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
3663 // Convert float to unsigned int
3664 // Assume that scale = 0
3667 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3668 "cfltu\t$rT, $rA, 0", SPrecFP,
3669 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
3672 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3673 "cfltu\t$rT, $rA, 0", SPrecFP,
3674 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
3676 // Convert float to signed int
3677 // Assume that scale = 0
3680 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3681 "cflts\t$rT, $rA, 0", SPrecFP,
3682 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
3685 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3686 "cflts\t$rT, $rA, 0", SPrecFP,
3687 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
3689 //===----------------------------------------------------------------------==//
3690 // Single<->Double precision conversions
3691 //===----------------------------------------------------------------------==//
3693 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
3694 // v4f32, output is v2f64--which goes in the name?)
3696 // Floating point extend single to double
3697 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
3698 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
3701 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3702 "fesd\t$rT, $rA", SPrecFP,
3703 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
3706 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
3707 "fesd\t$rT, $rA", SPrecFP,
3708 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
3710 // Floating point round double to single
3712 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3713 // "frds\t$rT, $rA,", SPrecFP,
3714 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
3717 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
3718 "frds\t$rT, $rA", SPrecFP,
3719 [(set R32FP:$rT, (fround R64FP:$rA))]>;
3721 //ToDo include anyextend?
3723 //===----------------------------------------------------------------------==//
3724 // Double precision floating point instructions
3725 //===----------------------------------------------------------------------==//
3727 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3728 "dfa\t$rT, $rA, $rB", DPrecFP,
3729 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
3732 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3733 "dfa\t$rT, $rA, $rB", DPrecFP,
3734 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3737 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3738 "dfs\t$rT, $rA, $rB", DPrecFP,
3739 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
3742 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3743 "dfs\t$rT, $rA, $rB", DPrecFP,
3744 [(set (v2f64 VECREG:$rT),
3745 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3748 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3749 "dfm\t$rT, $rA, $rB", DPrecFP,
3750 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
3753 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3754 "dfm\t$rT, $rA, $rB", DPrecFP,
3755 [(set (v2f64 VECREG:$rT),
3756 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3759 RRForm<0b00111010110, (outs R64FP:$rT),
3760 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3761 "dfma\t$rT, $rA, $rB", DPrecFP,
3762 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3763 RegConstraint<"$rC = $rT">,
3767 RRForm<0b00111010110, (outs VECREG:$rT),
3768 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3769 "dfma\t$rT, $rA, $rB", DPrecFP,
3770 [(set (v2f64 VECREG:$rT),
3771 (fadd (v2f64 VECREG:$rC),
3772 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
3773 RegConstraint<"$rC = $rT">,
3777 RRForm<0b10111010110, (outs R64FP:$rT),
3778 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3779 "dfms\t$rT, $rA, $rB", DPrecFP,
3780 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
3781 RegConstraint<"$rC = $rT">,
3785 RRForm<0b10111010110, (outs VECREG:$rT),
3786 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3787 "dfms\t$rT, $rA, $rB", DPrecFP,
3788 [(set (v2f64 VECREG:$rT),
3789 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3790 (v2f64 VECREG:$rC)))]>;
3792 // FNMS: - (a * b - c)
3793 // - (a * b) + c => c - (a * b)
3795 RRForm<0b01111010110, (outs R64FP:$rT),
3796 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3797 "dfnms\t$rT, $rA, $rB", DPrecFP,
3798 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3799 RegConstraint<"$rC = $rT">,
3802 def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
3803 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
3806 RRForm<0b01111010110, (outs VECREG:$rT),
3807 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3808 "dfnms\t$rT, $rA, $rB", DPrecFP,
3809 [(set (v2f64 VECREG:$rT),
3810 (fsub (v2f64 VECREG:$rC),
3811 (fmul (v2f64 VECREG:$rA),
3812 (v2f64 VECREG:$rB))))]>,
3813 RegConstraint<"$rC = $rT">,
3816 def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3817 (v2f64 VECREG:$rC))),
3818 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
3823 RRForm<0b11111010110, (outs R64FP:$rT),
3824 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3825 "dfnma\t$rT, $rA, $rB", DPrecFP,
3826 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
3827 RegConstraint<"$rC = $rT">,
3831 RRForm<0b11111010110, (outs VECREG:$rT),
3832 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3833 "dfnma\t$rT, $rA, $rB", DPrecFP,
3834 [(set (v2f64 VECREG:$rT),
3835 (fneg (fadd (v2f64 VECREG:$rC),
3836 (fmul (v2f64 VECREG:$rA),
3837 (v2f64 VECREG:$rB)))))]>,
3838 RegConstraint<"$rC = $rT">,
3841 //===----------------------------------------------------------------------==//
3842 // Floating point negation and absolute value
3843 //===----------------------------------------------------------------------==//
3845 def : Pat<(fneg (v4f32 VECREG:$rA)),
3846 (XORfnegvec (v4f32 VECREG:$rA),
3847 (v4f32 (ILHUv4i32 0x8000)))>;
3849 def : Pat<(fneg R32FP:$rA),
3850 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
3852 def : Pat<(fneg (v2f64 VECREG:$rA)),
3853 (XORfnegvec (v2f64 VECREG:$rA),
3854 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
3856 def : Pat<(fneg R64FP:$rA),
3857 (XORfneg64 R64FP:$rA,
3858 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
3860 // Floating point absolute value
3862 def : Pat<(fabs R32FP:$rA),
3863 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
3865 def : Pat<(fabs (v4f32 VECREG:$rA)),
3866 (ANDfabsvec (v4f32 VECREG:$rA),
3867 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3869 def : Pat<(fabs R64FP:$rA),
3870 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
3872 def : Pat<(fabs (v2f64 VECREG:$rA)),
3873 (ANDfabsvec (v2f64 VECREG:$rA),
3874 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3876 //===----------------------------------------------------------------------===//
3877 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
3878 // in the odd pipeline)
3879 //===----------------------------------------------------------------------===//
3881 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
3884 let Inst{0-10} = 0b10000000010;
3885 let Inst{11-17} = 0;
3886 let Inst{18-24} = 0;
3887 let Inst{25-31} = 0;
3890 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
3893 let Inst{0-10} = 0b10000000000;
3894 let Inst{11-17} = 0;
3895 let Inst{18-24} = 0;
3896 let Inst{25-31} = 0;
3899 //===----------------------------------------------------------------------===//
3900 // Bit conversions (type conversions between vector/packed types)
3901 // NOTE: Promotions are handled using the XS* instructions. Truncation
3903 //===----------------------------------------------------------------------===//
3904 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3905 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3906 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3907 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3908 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3910 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3911 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3912 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3913 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3914 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3916 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3917 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3918 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3919 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3920 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3922 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3923 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3924 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3925 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3926 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3928 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3929 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3930 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3931 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3932 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3934 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3935 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3936 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3937 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3938 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3940 def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3941 def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
3943 //===----------------------------------------------------------------------===//
3944 // Instruction patterns:
3945 //===----------------------------------------------------------------------===//
3947 // General 32-bit constants:
3948 def : Pat<(i32 imm:$imm),
3949 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3951 // Single precision float constants:
3952 def : Pat<(f32 fpimm:$imm),
3953 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3955 // General constant 32-bit vectors
3956 def : Pat<(v4i32 v4i32Imm:$imm),
3957 (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
3958 (LO16_vec v4i32Imm:$imm))>;
3961 def : Pat<(i8 imm:$imm),
3964 //===----------------------------------------------------------------------===//
3965 // Call instruction patterns:
3966 //===----------------------------------------------------------------------===//
3971 //===----------------------------------------------------------------------===//
3972 // Zero/Any/Sign extensions
3973 //===----------------------------------------------------------------------===//
3975 // zext 1->32: Zero extend i1 to i32
3976 def : Pat<(SPUextract_i1_zext R32C:$rSrc),
3977 (ANDIr32 R32C:$rSrc, 0x1)>;
3979 // sext 8->32: Sign extend bytes to words
3980 def : Pat<(sext_inreg R32C:$rSrc, i8),
3981 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
3983 def : Pat<(i32 (sext R8C:$rSrc)),
3984 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
3986 def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
3987 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
3988 (v4i32 VECREG:$rSrc))))>;
3990 // zext 8->16: Zero extend bytes to halfwords
3991 def : Pat<(i16 (zext R8C:$rSrc)),
3992 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
3994 // zext 8->32 from preferred slot in load/store
3995 def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
3996 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
3999 // zext 8->32: Zero extend bytes to words
4000 def : Pat<(i32 (zext R8C:$rSrc)),
4001 (ANDIi8i32 R8C:$rSrc, 0xff)>;
4003 // anyext 8->16: Extend 8->16 bits, irrespective of sign
4004 def : Pat<(i16 (anyext R8C:$rSrc)),
4005 (ORHIi8i16 R8C:$rSrc, 0)>;
4007 // anyext 8->32: Extend 8->32 bits, irrespective of sign
4008 def : Pat<(i32 (anyext R8C:$rSrc)),
4009 (ORIi8i32 R8C:$rSrc, 0)>;
4011 // zext 16->32: Zero extend halfwords to words
4012 def : Pat<(i32 (zext R16C:$rSrc)),
4013 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
4015 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
4016 (ANDIi16i32 R16C:$rSrc, 0xf)>;
4018 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
4019 (ANDIi16i32 R16C:$rSrc, 0xff)>;
4021 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
4022 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
4024 // anyext 16->32: Extend 16->32 bits, irrespective of sign
4025 def : Pat<(i32 (anyext R16C:$rSrc)),
4026 (ORIi16i32 R16C:$rSrc, 0)>;
4028 //===----------------------------------------------------------------------===//
4029 // Address generation: SPU, like PPC, has to split addresses into high and
4030 // low parts in order to load them into a register.
4031 //===----------------------------------------------------------------------===//
4033 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
4034 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
4035 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
4036 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
4038 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
4039 (SPUlo tglobaladdr:$in, 0)),
4040 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4042 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
4043 (SPUlo texternalsym:$in, 0)),
4044 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4046 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
4047 (SPUlo tjumptable:$in, 0)),
4048 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4050 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
4051 (SPUlo tconstpool:$in, 0)),
4052 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4054 def : Pat<(SPUindirect R32C:$sp, i32ImmSExt10:$imm),
4055 (AIr32 R32C:$sp, i32ImmSExt10:$imm)>;
4057 def : Pat<(SPUindirect R32C:$sp, imm:$imm),
4059 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm)))>;
4061 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
4062 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4064 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
4065 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4067 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
4068 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4070 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
4071 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4074 include "CellSDKIntrinsics.td"