1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start imm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end imm:$amt)]>;
33 //===----------------------------------------------------------------------===//
34 // DWARF debugging Pseudo Instructions
35 //===----------------------------------------------------------------------===//
37 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
38 "${:comment} .loc $file, $line, $col",
39 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
42 //===----------------------------------------------------------------------===//
44 // NB: The ordering is actually important, since the instruction selection
45 // will try each of the instructions in sequence, i.e., the D-form first with
46 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
47 // finally the X-form with the register-register.
48 //===----------------------------------------------------------------------===//
50 let isSimpleLoad = 1 in {
51 class LoadDFormVec<ValueType vectype>
52 : RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
55 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
58 class LoadDForm<RegisterClass rclass>
59 : RI10Form<0b00101100, (outs rclass:$rT), (ins memri10:$src),
62 [(set rclass:$rT, (load dform_addr:$src))]>
67 def v16i8: LoadDFormVec<v16i8>;
68 def v8i16: LoadDFormVec<v8i16>;
69 def v4i32: LoadDFormVec<v4i32>;
70 def v2i64: LoadDFormVec<v2i64>;
71 def v4f32: LoadDFormVec<v4f32>;
72 def v2f64: LoadDFormVec<v2f64>;
74 def r128: LoadDForm<GPRC>;
75 def r64: LoadDForm<R64C>;
76 def r32: LoadDForm<R32C>;
77 def f32: LoadDForm<R32FP>;
78 def f64: LoadDForm<R64FP>;
79 def r16: LoadDForm<R16C>;
80 def r8: LoadDForm<R8C>;
83 class LoadAFormVec<ValueType vectype>
84 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
87 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
90 class LoadAForm<RegisterClass rclass>
91 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
94 [(set rclass:$rT, (load aform_addr:$src))]>
99 def v16i8: LoadAFormVec<v16i8>;
100 def v8i16: LoadAFormVec<v8i16>;
101 def v4i32: LoadAFormVec<v4i32>;
102 def v2i64: LoadAFormVec<v2i64>;
103 def v4f32: LoadAFormVec<v4f32>;
104 def v2f64: LoadAFormVec<v2f64>;
106 def r128: LoadAForm<GPRC>;
107 def r64: LoadAForm<R64C>;
108 def r32: LoadAForm<R32C>;
109 def f32: LoadAForm<R32FP>;
110 def f64: LoadAForm<R64FP>;
111 def r16: LoadAForm<R16C>;
112 def r8: LoadAForm<R8C>;
115 class LoadXFormVec<ValueType vectype>
116 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
119 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
122 class LoadXForm<RegisterClass rclass>
123 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
126 [(set rclass:$rT, (load xform_addr:$src))]>
129 multiclass LoadXForms
131 def v16i8: LoadXFormVec<v16i8>;
132 def v8i16: LoadXFormVec<v8i16>;
133 def v4i32: LoadXFormVec<v4i32>;
134 def v2i64: LoadXFormVec<v2i64>;
135 def v4f32: LoadXFormVec<v4f32>;
136 def v2f64: LoadXFormVec<v2f64>;
138 def r128: LoadXForm<GPRC>;
139 def r64: LoadXForm<R64C>;
140 def r32: LoadXForm<R32C>;
141 def f32: LoadXForm<R32FP>;
142 def f64: LoadXForm<R64FP>;
143 def r16: LoadXForm<R16C>;
144 def r8: LoadXForm<R8C>;
147 defm LQA : LoadAForms;
148 defm LQD : LoadDForms;
149 defm LQX : LoadXForms;
151 /* Load quadword, PC relative: Not much use at this point in time.
152 Might be of use later for relocatable code. It's effectively the
153 same as LQA, but uses PC-relative addressing.
154 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
155 "lqr\t$rT, $disp", LoadStore,
156 [(set VECREG:$rT, (load iaddr:$disp))]>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
163 class StoreDFormVec<ValueType vectype>
164 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
167 [(store (vectype VECREG:$rT), dform_addr:$src)]>
170 class StoreDForm<RegisterClass rclass>
171 : RI10Form<0b00100100, (outs), (ins rclass:$rT, memri10:$src),
174 [(store rclass:$rT, dform_addr:$src)]>
177 multiclass StoreDForms
179 def v16i8: StoreDFormVec<v16i8>;
180 def v8i16: StoreDFormVec<v8i16>;
181 def v4i32: StoreDFormVec<v4i32>;
182 def v2i64: StoreDFormVec<v2i64>;
183 def v4f32: StoreDFormVec<v4f32>;
184 def v2f64: StoreDFormVec<v2f64>;
186 def r128: StoreDForm<GPRC>;
187 def r64: StoreDForm<R64C>;
188 def r32: StoreDForm<R32C>;
189 def f32: StoreDForm<R32FP>;
190 def f64: StoreDForm<R64FP>;
191 def r16: StoreDForm<R16C>;
192 def r8: StoreDForm<R8C>;
195 class StoreAFormVec<ValueType vectype>
196 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
199 [(store (vectype VECREG:$rT), aform_addr:$src)]>;
201 class StoreAForm<RegisterClass rclass>
202 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
205 [(store rclass:$rT, aform_addr:$src)]>;
207 multiclass StoreAForms
209 def v16i8: StoreAFormVec<v16i8>;
210 def v8i16: StoreAFormVec<v8i16>;
211 def v4i32: StoreAFormVec<v4i32>;
212 def v2i64: StoreAFormVec<v2i64>;
213 def v4f32: StoreAFormVec<v4f32>;
214 def v2f64: StoreAFormVec<v2f64>;
216 def r128: StoreAForm<GPRC>;
217 def r64: StoreAForm<R64C>;
218 def r32: StoreAForm<R32C>;
219 def f32: StoreAForm<R32FP>;
220 def f64: StoreAForm<R64FP>;
221 def r16: StoreAForm<R16C>;
222 def r8: StoreAForm<R8C>;
225 class StoreXFormVec<ValueType vectype>
226 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
229 [(store (vectype VECREG:$rT), xform_addr:$src)]>
232 class StoreXForm<RegisterClass rclass>
233 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
236 [(store rclass:$rT, xform_addr:$src)]>
239 multiclass StoreXForms
241 def v16i8: StoreXFormVec<v16i8>;
242 def v8i16: StoreXFormVec<v8i16>;
243 def v4i32: StoreXFormVec<v4i32>;
244 def v2i64: StoreXFormVec<v2i64>;
245 def v4f32: StoreXFormVec<v4f32>;
246 def v2f64: StoreXFormVec<v2f64>;
248 def r128: StoreXForm<GPRC>;
249 def r64: StoreXForm<R64C>;
250 def r32: StoreXForm<R32C>;
251 def f32: StoreXForm<R32FP>;
252 def f64: StoreXForm<R64FP>;
253 def r16: StoreXForm<R16C>;
254 def r8: StoreXForm<R8C>;
257 defm STQD : StoreDForms;
258 defm STQA : StoreAForms;
259 defm STQX : StoreXForms;
261 /* Store quadword, PC relative: Not much use at this point in time. Might
262 be useful for relocatable code.
263 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
264 "stqr\t$rT, $disp", LoadStore,
265 [(store VECREG:$rT, iaddr:$disp)]>;
268 //===----------------------------------------------------------------------===//
269 // Generate Controls for Insertion:
270 //===----------------------------------------------------------------------===//
273 RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
274 "cbd\t$rT, $src", ShuffleOp,
275 [(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
277 def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
278 "cbx\t$rT, $src", ShuffleOp,
279 [(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
281 def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
282 "chd\t$rT, $src", ShuffleOp,
283 [(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
285 def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
286 "chx\t$rT, $src", ShuffleOp,
287 [(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
289 def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
290 "cwd\t$rT, $src", ShuffleOp,
291 [(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
293 def CWDf32 : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
294 "cwd\t$rT, $src", ShuffleOp,
295 [(set (v4f32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
297 def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
298 "cwx\t$rT, $src", ShuffleOp,
299 [(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
301 def CWXf32 : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
302 "cwx\t$rT, $src", ShuffleOp,
303 [(set (v4f32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
305 def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
306 "cdd\t$rT, $src", ShuffleOp,
307 [(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
309 def CDDf64 : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
310 "cdd\t$rT, $src", ShuffleOp,
311 [(set (v2f64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
313 def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
314 "cdx\t$rT, $src", ShuffleOp,
315 [(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
317 def CDXf64 : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
318 "cdx\t$rT, $src", ShuffleOp,
319 [(set (v2f64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
321 //===----------------------------------------------------------------------===//
322 // Constant formation:
323 //===----------------------------------------------------------------------===//
326 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
327 "ilh\t$rT, $val", ImmLoad,
328 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
331 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
332 "ilh\t$rT, $val", ImmLoad,
333 [(set R16C:$rT, immSExt16:$val)]>;
335 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
336 // the right constant")
338 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
339 "ilh\t$rT, $val", ImmLoad,
340 [(set R8C:$rT, immSExt8:$val)]>;
342 // IL does sign extension!
344 class ILInst<dag OOL, dag IOL, list<dag> pattern>:
345 RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val",
348 class ILVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
349 ILInst<(outs VECREG:$rT), (ins immtype:$val),
350 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
352 class ILRegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
353 ILInst<(outs rclass:$rT), (ins immtype:$val),
354 [(set rclass:$rT, xform:$val)]>;
356 multiclass ImmediateLoad
358 def v2i64: ILVecInst<v2i64, s16imm_i64, v2i64SExt16Imm>;
359 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
361 // TODO: Need v2f64, v4f32
363 def r64: ILRegInst<R64C, s16imm_i64, immSExt16>;
364 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
365 def f32: ILRegInst<R32FP, s16imm_f32, fpimmSExt16>;
366 def f64: ILRegInst<R64FP, s16imm_f64, fpimmSExt16>;
369 defm IL : ImmediateLoad;
371 class ILHUInst<dag OOL, dag IOL, list<dag> pattern>:
372 RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val",
375 class ILHUVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
376 ILHUInst<(outs VECREG:$rT), (ins immtype:$val),
377 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
379 class ILHURegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
380 ILHUInst<(outs rclass:$rT), (ins immtype:$val),
381 [(set rclass:$rT, xform:$val)]>;
383 multiclass ImmLoadHalfwordUpper
385 def v2i64: ILHUVecInst<v2i64, u16imm_i64, immILHUvec_i64>;
386 def v4i32: ILHUVecInst<v4i32, u16imm_i32, immILHUvec>;
388 def r64: ILHURegInst<R64C, u16imm_i64, hi16>;
389 def r32: ILHURegInst<R32C, u16imm_i32, hi16>;
391 // Loads the high portion of an address
392 def hi: ILHURegInst<R32C, symbolHi, hi16>;
394 // Used in custom lowering constant SFP loads:
395 def f32: ILHURegInst<R32FP, f16imm, hi16_f32>;
398 defm ILHU : ImmLoadHalfwordUpper;
400 // Immediate load address (can also be used to load 18-bit unsigned constants,
401 // see the zext 16->32 pattern)
403 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
404 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
407 class ILAVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
408 ILAInst<(outs VECREG:$rT), (ins immtype:$val),
409 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
411 class ILARegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
412 ILAInst<(outs rclass:$rT), (ins immtype:$val),
413 [(set rclass:$rT, xform:$val)]>;
415 multiclass ImmLoadAddress
417 def v2i64: ILAVecInst<v2i64, u18imm, v2i64Uns18Imm>;
418 def v4i32: ILAVecInst<v4i32, u18imm, v4i32Uns18Imm>;
420 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
421 def r32: ILARegInst<R32C, u18imm, imm18>;
422 def f32: ILARegInst<R32FP, f18imm, fpimm18>;
423 def f64: ILARegInst<R64FP, f18imm_f64, fpimm18>;
425 def lo: ILARegInst<R32C, symbolLo, imm18>;
427 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
431 defm ILA : ImmLoadAddress;
433 // Immediate OR, Halfword Lower: The "other" part of loading large constants
434 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
435 // Note that these are really two operand instructions, but they're encoded
436 // as three operands with the first two arguments tied-to each other.
438 class IOHLInst<dag OOL, dag IOL, list<dag> pattern>:
439 RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val",
441 RegConstraint<"$rS = $rT">,
444 class IOHLVecInst<ValueType vectype, Operand immtype /* , PatLeaf xform */>:
445 IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val),
448 class IOHLRegInst<RegisterClass rclass, Operand immtype /* , PatLeaf xform */>:
449 IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val),
452 multiclass ImmOrHalfwordLower
454 def v2i64: IOHLVecInst<v2i64, u16imm_i64>;
455 def v4i32: IOHLVecInst<v4i32, u16imm_i32>;
457 def r32: IOHLRegInst<R32C, i32imm>;
458 def f32: IOHLRegInst<R32FP, f32imm>;
460 def lo: IOHLRegInst<R32C, symbolLo>;
463 defm IOHL: ImmOrHalfwordLower;
465 // Form select mask for bytes using immediate, used in conjunction with the
468 class FSMBIVec<ValueType vectype>:
469 RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
472 [(set (vectype VECREG:$rT), (SPUfsmbi (i16 immU16:$val)))]>;
474 multiclass FormSelectMaskBytesImm
476 def v16i8: FSMBIVec<v16i8>;
477 def v8i16: FSMBIVec<v8i16>;
478 def v4i32: FSMBIVec<v4i32>;
479 def v2i64: FSMBIVec<v2i64>;
482 defm FSMBI : FormSelectMaskBytesImm;
484 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
486 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
487 "fsmb\t$rT, $rA", SelectOp,
488 [(set (v16i8 VECREG:$rT), (SPUfsmbi R16C:$rA))]>;
490 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
491 // only 8-bits wide (even though it's input as 16-bits here)
493 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
494 "fsmh\t$rT, $rA", SelectOp,
495 [(set (v8i16 VECREG:$rT), (SPUfsmbi R16C:$rA))]>;
497 // fsm: Form select mask for words. Like the other fsm* instructions,
498 // only the lower 4 bits of $rA are significant.
500 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA),
501 "fsm\t$rT, $rA", SelectOp,
502 [(set (v4i32 VECREG:$rT), (SPUfsmbi R16C:$rA))]>;
504 //===----------------------------------------------------------------------===//
505 // Integer and Logical Operations:
506 //===----------------------------------------------------------------------===//
509 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
510 "ah\t$rT, $rA, $rB", IntegerOp,
511 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
513 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
514 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
517 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
518 "ah\t$rT, $rA, $rB", IntegerOp,
519 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
522 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
523 "ahi\t$rT, $rA, $val", IntegerOp,
524 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
525 v8i16SExt10Imm:$val))]>;
528 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
529 "ahi\t$rT, $rA, $val", IntegerOp,
530 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
533 RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
534 "a\t$rT, $rA, $rB", IntegerOp,
535 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
537 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
538 (Avec VECREG:$rA, VECREG:$rB)>;
541 RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
542 "a\t$rT, $rA, $rB", IntegerOp,
543 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
546 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
547 "a\t$rT, $rA, $rB", IntegerOp,
548 [(set R8C:$rT, (add R8C:$rA, R8C:$rB))]>;
551 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
552 "ai\t$rT, $rA, $val", IntegerOp,
553 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
554 v4i32SExt10Imm:$val))]>;
557 RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
558 "ai\t$rT, $rA, $val", IntegerOp,
559 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
562 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
563 "sfh\t$rT, $rA, $rB", IntegerOp,
564 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
565 (v8i16 VECREG:$rB)))]>;
568 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
569 "sfh\t$rT, $rA, $rB", IntegerOp,
570 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
573 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
574 "sfhi\t$rT, $rA, $val", IntegerOp,
575 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
576 (v8i16 VECREG:$rA)))]>;
578 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
579 "sfhi\t$rT, $rA, $val", IntegerOp,
580 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
582 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
583 (ins VECREG:$rA, VECREG:$rB),
584 "sf\t$rT, $rA, $rB", IntegerOp,
585 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
587 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
588 "sf\t$rT, $rA, $rB", IntegerOp,
589 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
592 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
593 "sfi\t$rT, $rA, $val", IntegerOp,
594 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
595 (v4i32 VECREG:$rA)))]>;
597 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
598 (ins R32C:$rA, s10imm_i32:$val),
599 "sfi\t$rT, $rA, $val", IntegerOp,
600 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
602 // ADDX: only available in vector form, doesn't match a pattern.
604 RRForm<0b00000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
606 "addx\t$rT, $rA, $rB", IntegerOp,
608 RegConstraint<"$rCarry = $rT">,
611 // CG: only available in vector form, doesn't match a pattern.
613 RRForm<0b01000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
615 "cg\t$rT, $rA, $rB", IntegerOp,
617 RegConstraint<"$rCarry = $rT">,
620 // SFX: only available in vector form, doesn't match a pattern
622 RRForm<0b10000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
624 "sfx\t$rT, $rA, $rB", IntegerOp,
626 RegConstraint<"$rCarry = $rT">,
629 // BG: only available in vector form, doesn't match a pattern.
631 RRForm<0b01000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
633 "bg\t$rT, $rA, $rB", IntegerOp,
635 RegConstraint<"$rCarry = $rT">,
638 // BGX: only available in vector form, doesn't match a pattern.
640 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
642 "bgx\t$rT, $rA, $rB", IntegerOp,
644 RegConstraint<"$rCarry = $rT">,
647 // Halfword multiply variants:
648 // N.B: These can be used to build up larger quantities (16x16 -> 32)
651 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
652 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
653 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
654 (v8i16 VECREG:$rB)))]>;
657 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
658 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
659 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
662 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
663 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
664 [(set (v4i32 VECREG:$rT),
665 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
668 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
669 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
670 [(set R32C:$rT, (mul (zext R16C:$rA),
674 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
675 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
676 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
678 // mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
679 // this only produces the lower 16 bits)
681 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
682 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
683 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
686 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
687 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
688 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
690 // mpyui: same issues as other multiplies, plus, this doesn't match a
691 // pattern... but may be used during target DAG selection or lowering
693 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
694 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
698 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
699 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
702 // mpya: 16 x 16 + 16 -> 32 bit result
704 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
705 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
706 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
707 (v8i16 VECREG:$rB)))),
708 (v4i32 VECREG:$rC)))]>;
711 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
712 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
713 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
716 def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
717 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
719 def MPYAr32_sextinreg:
720 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
721 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
722 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
723 (sext_inreg R32C:$rB, i16)),
727 // RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
728 // "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
729 // [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
732 // mpyh: multiply high, used to synthesize 32-bit multiplies
734 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
735 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
736 [(set (v4i32 VECREG:$rT),
737 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
740 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
741 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
742 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
744 // mpys: multiply high and shift right (returns the top half of
745 // a 16-bit multiply, sign extended to 32 bits.)
747 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
748 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
752 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
753 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
756 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
757 // the top 16 bits of the $rA, $rB)
759 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
760 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
761 [(set (v8i16 VECREG:$rT),
762 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
765 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
766 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
769 // mpyhha: Multiply high-high, add to $rT:
771 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
772 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
776 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
777 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
780 // mpyhhu: Multiply high-high, unsigned
782 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
783 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
787 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
788 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
791 // mpyhhau: Multiply high-high, unsigned
793 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
794 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
798 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
799 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
802 // clz: Count leading zeroes
804 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
805 "clz\t$rT, $rA", IntegerOp,
809 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
810 "clz\t$rT, $rA", IntegerOp,
811 [(set R32C:$rT, (ctlz R32C:$rA))]>;
813 // cntb: Count ones in bytes (aka "population count")
814 // NOTE: This instruction is really a vector instruction, but the custom
815 // lowering code uses it in unorthodox ways to support CTPOP for other
818 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
819 "cntb\t$rT, $rA", IntegerOp,
820 [(set (v16i8 VECREG:$rT), (SPUcntb_v16i8 (v16i8 VECREG:$rA)))]>;
823 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
824 "cntb\t$rT, $rA", IntegerOp,
825 [(set (v8i16 VECREG:$rT), (SPUcntb_v8i16 (v8i16 VECREG:$rA)))]>;
828 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
829 "cntb\t$rT, $rA", IntegerOp,
830 [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>;
832 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
833 // quantity stored into $rT
835 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
836 "gbb\t$rT, $rA", GatherOp,
839 // gbh: Gather all low order bits from each halfword in $rA into a single
840 // 8-bit quantity stored in $rT
842 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
843 "gbh\t$rT, $rA", GatherOp,
846 // gb: Gather all low order bits from each word in $rA into a single
847 // 4-bit quantity stored in $rT
849 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
850 "gb\t$rT, $rA", GatherOp,
853 // avgb: average bytes
855 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
856 "avgb\t$rT, $rA, $rB", ByteOp,
859 // absdb: absolute difference of bytes
861 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
862 "absdb\t$rT, $rA, $rB", ByteOp,
865 // sumb: sum bytes into halfwords
867 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
868 "sumb\t$rT, $rA, $rB", ByteOp,
871 // Sign extension operations:
873 RRForm_1<0b01101101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
874 "xsbh\t$rDst, $rSrc", IntegerOp,
875 [(set (v8i16 VECREG:$rDst), (sext (v16i8 VECREG:$rSrc)))]>;
877 // Ordinary form for XSBH
879 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R16C:$rSrc),
880 "xsbh\t$rDst, $rSrc", IntegerOp,
881 [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>;
884 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R8C:$rSrc),
885 "xsbh\t$rDst, $rSrc", IntegerOp,
886 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
888 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
889 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
890 // pattern below). Intentionally doesn't match a pattern because we want the
891 // sext 8->32 pattern to do the work for us, namely because we need the extra
894 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
895 "xsbh\t$rDst, $rSrc", IntegerOp,
896 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i8))]>;
898 // Sign extend halfwords to words:
900 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
901 "xshw\t$rDest, $rSrc", IntegerOp,
902 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
905 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
906 "xshw\t$rDst, $rSrc", IntegerOp,
907 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
910 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
911 "xshw\t$rDst, $rSrc", IntegerOp,
912 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
915 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
916 "xswd\t$rDst, $rSrc", IntegerOp,
917 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
920 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
921 "xswd\t$rDst, $rSrc", IntegerOp,
922 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
925 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
926 "xswd\t$rDst, $rSrc", IntegerOp,
927 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
929 def : Pat<(sext R32C:$inp),
930 (XSWDr32 R32C:$inp)>;
934 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
935 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
938 class ANDVecInst<ValueType vectype>:
939 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
940 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
941 (vectype VECREG:$rB)))]>;
943 class ANDRegInst<RegisterClass rclass>:
944 ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
945 [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>;
947 multiclass BitwiseAnd
949 def v16i8: ANDVecInst<v16i8>;
950 def v8i16: ANDVecInst<v8i16>;
951 def v4i32: ANDVecInst<v4i32>;
952 def v2i64: ANDVecInst<v2i64>;
954 def r128: ANDRegInst<GPRC>;
955 def r64: ANDRegInst<R64C>;
956 def r32: ANDRegInst<R32C>;
957 def r16: ANDRegInst<R16C>;
958 def r8: ANDRegInst<R8C>;
960 //===---------------------------------------------
961 // Special instructions to perform the fabs instruction
962 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
963 [/* Intentionally does not match a pattern */]>;
965 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
966 [/* Intentionally does not match a pattern */]>;
968 // Could use v4i32, but won't for clarity
969 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
970 [/* Intentionally does not match a pattern */]>;
972 //===---------------------------------------------
974 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
975 // quantities -- see 16->32 zext pattern.
977 // This pattern is somewhat artificial, since it might match some
978 // compiler generated pattern but it is unlikely to do so.
980 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
981 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
984 defm AND : BitwiseAnd;
986 // N.B.: vnot_conv is one of those special target selection pattern fragments,
987 // in which we expect there to be a bit_convert on the constant. Bear in mind
988 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
989 // constant -1 vector.)
991 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
992 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
995 class ANDCVecInst<ValueType vectype>:
996 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
997 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
998 (vnot (vectype VECREG:$rB))))]>;
1000 class ANDCRegInst<RegisterClass rclass>:
1001 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1002 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
1004 multiclass AndComplement
1006 def v16i8: ANDCVecInst<v16i8>;
1007 def v8i16: ANDCVecInst<v8i16>;
1008 def v4i32: ANDCVecInst<v4i32>;
1009 def v2i64: ANDCVecInst<v2i64>;
1011 def r128: ANDCRegInst<GPRC>;
1012 def r64: ANDCRegInst<R64C>;
1013 def r32: ANDCRegInst<R32C>;
1014 def r16: ANDCRegInst<R16C>;
1015 def r8: ANDCRegInst<R8C>;
1018 defm ANDC : AndComplement;
1020 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1021 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1022 IntegerOp, pattern>;
1024 multiclass AndByteImm
1026 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1027 [(set (v16i8 VECREG:$rT),
1028 (and (v16i8 VECREG:$rA),
1029 (v16i8 v16i8U8Imm:$val)))]>;
1031 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1032 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1035 defm ANDBI : AndByteImm;
1037 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1038 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1039 IntegerOp, pattern>;
1041 multiclass AndHalfwordImm
1043 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1044 [(set (v8i16 VECREG:$rT),
1045 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1047 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1048 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1050 // Zero-extend i8 to i16:
1051 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1052 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1055 defm ANDHI : AndHalfwordImm;
1057 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1058 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1059 IntegerOp, pattern>;
1061 multiclass AndWordImm
1063 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1064 [(set (v4i32 VECREG:$rT),
1065 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1067 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1068 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1070 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1072 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1074 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1076 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1077 // zext 16->32 pattern below.
1079 // Note that this pattern is somewhat artificial, since it might match
1080 // something the compiler generates but is unlikely to occur in practice.
1081 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1083 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1086 defm ANDI : AndWordImm;
1088 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1089 // Bitwise OR group:
1090 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1092 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1093 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1094 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1095 IntegerOp, pattern>;
1097 class ORVecInst<ValueType vectype>:
1098 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1099 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1100 (vectype VECREG:$rB)))]>;
1102 class ORRegInst<RegisterClass rclass>:
1103 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1104 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1106 class ORPromoteScalar<RegisterClass rclass>:
1107 ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB),
1108 [/* no pattern */]>;
1110 class ORExtractElt<RegisterClass rclass>:
1111 ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB),
1112 [/* no pattern */]>;
1114 multiclass BitwiseOr
1116 def v16i8: ORVecInst<v16i8>;
1117 def v8i16: ORVecInst<v8i16>;
1118 def v4i32: ORVecInst<v4i32>;
1119 def v2i64: ORVecInst<v2i64>;
1121 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1122 [(set (v4f32 VECREG:$rT),
1123 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1124 (v4i32 VECREG:$rB)))))]>;
1126 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1127 [(set (v2f64 VECREG:$rT),
1128 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1129 (v2i64 VECREG:$rB)))))]>;
1131 def r64: ORRegInst<R64C>;
1132 def r32: ORRegInst<R32C>;
1133 def r16: ORRegInst<R16C>;
1134 def r8: ORRegInst<R8C>;
1136 // OR instructions used to copy f32 and f64 registers.
1137 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1138 [/* no pattern */]>;
1140 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1141 [/* no pattern */]>;
1143 // scalar->vector promotion:
1144 def v16i8_i8: ORPromoteScalar<R8C>;
1145 def v8i16_i16: ORPromoteScalar<R16C>;
1146 def v4i32_i32: ORPromoteScalar<R32C>;
1147 def v2i64_i64: ORPromoteScalar<R64C>;
1148 def v4f32_f32: ORPromoteScalar<R32FP>;
1149 def v2f64_f64: ORPromoteScalar<R64FP>;
1151 // extract element 0:
1152 def i8_v16i8: ORExtractElt<R8C>;
1153 def i16_v8i16: ORExtractElt<R16C>;
1154 def i32_v4i32: ORExtractElt<R32C>;
1155 def i64_v2i64: ORExtractElt<R64C>;
1156 def f32_v4f32: ORExtractElt<R32FP>;
1157 def f64_v2f64: ORExtractElt<R64FP>;
1160 defm OR : BitwiseOr;
1162 // scalar->vector promotion patterns:
1163 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
1164 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
1166 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1167 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1169 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1170 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1172 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1173 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1175 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1176 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1178 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1179 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1181 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1183 def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)),
1184 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1186 def : Pat<(SPUextract_elt0_chained (v16i8 VECREG:$rA)),
1187 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1189 def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
1190 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1192 def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
1193 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1195 def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
1196 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1198 def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
1199 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1201 def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
1202 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1204 def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
1205 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1207 def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
1208 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1210 def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
1211 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1213 def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
1214 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1216 def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
1217 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1219 // ORC: Bitwise "or" with complement (c = a | ~b)
1221 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1222 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1223 IntegerOp, pattern>;
1225 class ORCVecInst<ValueType vectype>:
1226 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1227 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1228 (vnot (vectype VECREG:$rB))))]>;
1230 class ORCRegInst<RegisterClass rclass>:
1231 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1232 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1234 multiclass BitwiseOrComplement
1236 def v16i8: ORCVecInst<v16i8>;
1237 def v8i16: ORCVecInst<v8i16>;
1238 def v4i32: ORCVecInst<v4i32>;
1239 def v2i64: ORCVecInst<v2i64>;
1241 def r64: ORCRegInst<R64C>;
1242 def r32: ORCRegInst<R32C>;
1243 def r16: ORCRegInst<R16C>;
1244 def r8: ORCRegInst<R8C>;
1247 defm ORC : BitwiseOrComplement;
1249 // OR byte immediate
1250 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1251 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1252 IntegerOp, pattern>;
1254 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1255 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1256 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1257 (vectype immpred:$val)))]>;
1259 multiclass BitwiseOrByteImm
1261 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1263 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1264 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1267 defm ORBI : BitwiseOrByteImm;
1269 // OR halfword immediate
1270 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1271 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1272 IntegerOp, pattern>;
1274 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1275 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1276 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1279 multiclass BitwiseOrHalfwordImm
1281 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1283 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1284 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1286 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1287 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1288 [(set R16C:$rT, (or (anyext R8C:$rA),
1289 i16ImmSExt10:$val))]>;
1292 defm ORHI : BitwiseOrHalfwordImm;
1294 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1295 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1296 IntegerOp, pattern>;
1298 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1299 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1300 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1303 // Bitwise "or" with immediate
1304 multiclass BitwiseOrImm
1306 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1308 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1309 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1311 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1312 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1313 // infra "anyext 16->32" pattern.)
1314 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1315 [(set R32C:$rT, (or (anyext R16C:$rA),
1316 i32ImmSExt10:$val))]>;
1318 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1319 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1320 // infra "anyext 16->32" pattern.)
1321 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1322 [(set R32C:$rT, (or (anyext R8C:$rA),
1323 i32ImmSExt10:$val))]>;
1326 defm ORI : BitwiseOrImm;
1328 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1329 // $rT[0], slots 1-3 are zeroed.
1331 // FIXME: Needs to match an intrinsic pattern.
1333 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1334 "orx\t$rT, $rA, $rB", IntegerOp,
1339 class XORInst<dag OOL, dag IOL, list<dag> pattern> :
1340 RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB",
1341 IntegerOp, pattern>;
1343 class XORVecInst<ValueType vectype>:
1344 XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1345 [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA),
1346 (vectype VECREG:$rB)))]>;
1348 class XORRegInst<RegisterClass rclass>:
1349 XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1350 [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>;
1352 multiclass BitwiseExclusiveOr
1354 def v16i8: XORVecInst<v16i8>;
1355 def v8i16: XORVecInst<v8i16>;
1356 def v4i32: XORVecInst<v4i32>;
1357 def v2i64: XORVecInst<v2i64>;
1359 def r128: XORRegInst<GPRC>;
1360 def r64: XORRegInst<R64C>;
1361 def r32: XORRegInst<R32C>;
1362 def r16: XORRegInst<R16C>;
1363 def r8: XORRegInst<R8C>;
1365 // Special forms for floating point instructions.
1366 // fneg and fabs require bitwise logical ops to manipulate the sign bit.
1368 def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1369 [/* no pattern */]>;
1371 def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1372 [/* no pattern */]>;
1374 def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1375 [/* no pattern, see fneg{32,64} */]>;
1378 defm XOR : BitwiseExclusiveOr;
1380 //==----------------------------------------------------------
1382 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1383 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1384 IntegerOp, pattern>;
1386 multiclass XorByteImm
1389 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1390 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1393 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1394 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1397 defm XORBI : XorByteImm;
1400 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1401 "xorhi\t$rT, $rA, $val", IntegerOp,
1402 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1403 v8i16SExt10Imm:$val))]>;
1406 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1407 "xorhi\t$rT, $rA, $val", IntegerOp,
1408 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1411 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
1412 "xori\t$rT, $rA, $val", IntegerOp,
1413 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1414 v4i32SExt10Imm:$val))]>;
1417 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1418 "xori\t$rT, $rA, $val", IntegerOp,
1419 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1423 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1424 "nand\t$rT, $rA, $rB", IntegerOp,
1425 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1426 (v16i8 VECREG:$rB))))]>;
1429 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1430 "nand\t$rT, $rA, $rB", IntegerOp,
1431 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1432 (v8i16 VECREG:$rB))))]>;
1435 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1436 "nand\t$rT, $rA, $rB", IntegerOp,
1437 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1438 (v4i32 VECREG:$rB))))]>;
1441 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1442 "nand\t$rT, $rA, $rB", IntegerOp,
1443 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1446 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1447 "nand\t$rT, $rA, $rB", IntegerOp,
1448 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1451 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1452 "nand\t$rT, $rA, $rB", IntegerOp,
1453 [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
1457 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1458 "nor\t$rT, $rA, $rB", IntegerOp,
1459 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1460 (v16i8 VECREG:$rB))))]>;
1463 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1464 "nor\t$rT, $rA, $rB", IntegerOp,
1465 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1466 (v8i16 VECREG:$rB))))]>;
1469 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1470 "nor\t$rT, $rA, $rB", IntegerOp,
1471 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1472 (v4i32 VECREG:$rB))))]>;
1475 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1476 "nor\t$rT, $rA, $rB", IntegerOp,
1477 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1480 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1481 "nor\t$rT, $rA, $rB", IntegerOp,
1482 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1485 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1486 "nor\t$rT, $rA, $rB", IntegerOp,
1487 [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
1490 class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
1491 RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC",
1492 IntegerOp, pattern>;
1494 class SELBVecInst<ValueType vectype>:
1495 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1496 [(set (vectype VECREG:$rT),
1497 (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)),
1498 (and (vnot (vectype VECREG:$rC)),
1499 (vectype VECREG:$rA))))]>;
1501 class SELBRegInst<RegisterClass rclass>:
1502 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
1504 (or (and rclass:$rA, rclass:$rC),
1505 (and rclass:$rB, (not rclass:$rC))))]>;
1507 multiclass SelectBits
1509 def v16i8: SELBVecInst<v16i8>;
1510 def v8i16: SELBVecInst<v8i16>;
1511 def v4i32: SELBVecInst<v4i32>;
1512 def v2i64: SELBVecInst<v2i64>;
1514 def r128: SELBRegInst<GPRC>;
1515 def r64: SELBRegInst<R64C>;
1516 def r32: SELBRegInst<R32C>;
1517 def r16: SELBRegInst<R16C>;
1518 def r8: SELBRegInst<R8C>;
1521 defm SELB : SelectBits;
1523 class SPUselbPat<ValueType vectype, SPUInstr inst>:
1524 Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)),
1525 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1527 def : SPUselbPat<v16i8, SELBv16i8>;
1528 def : SPUselbPat<v8i16, SELBv8i16>;
1529 def : SPUselbPat<v4i32, SELBv4i32>;
1530 def : SPUselbPat<v2i64, SELBv2i64>;
1532 class SelectConditional<RegisterClass rclass, SPUInstr inst>:
1533 Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse),
1534 (inst rclass:$rFalse, rclass:$rTrue, rclass:$rCond)>;
1536 def : SelectConditional<R32C, SELBr32>;
1537 def : SelectConditional<R16C, SELBr16>;
1538 def : SelectConditional<R8C, SELBr8>;
1540 // EQV: Equivalence (1 for each same bit, otherwise 0)
1542 // Note: There are a lot of ways to match this bit operator and these patterns
1543 // attempt to be as exhaustive as possible.
1545 class EQVInst<dag OOL, dag IOL, list<dag> pattern>:
1546 RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB",
1547 IntegerOp, pattern>;
1549 class EQVVecInst<ValueType vectype>:
1550 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1551 [(set (vectype VECREG:$rT),
1552 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1553 (and (vnot (vectype VECREG:$rA)),
1554 (vnot (vectype VECREG:$rB)))))]>;
1556 class EQVRegInst<RegisterClass rclass>:
1557 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1558 [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB),
1559 (and (not rclass:$rA), (not rclass:$rB))))]>;
1561 class EQVVecPattern1<ValueType vectype>:
1562 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1563 [(set (vectype VECREG:$rT),
1564 (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>;
1566 class EQVRegPattern1<RegisterClass rclass>:
1567 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1568 [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>;
1570 class EQVVecPattern2<ValueType vectype>:
1571 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1572 [(set (vectype VECREG:$rT),
1573 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1574 (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>;
1576 class EQVRegPattern2<RegisterClass rclass>:
1577 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1579 (or (and rclass:$rA, rclass:$rB),
1580 (not (or rclass:$rA, rclass:$rB))))]>;
1582 class EQVVecPattern3<ValueType vectype>:
1583 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1584 [(set (vectype VECREG:$rT),
1585 (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>;
1587 class EQVRegPattern3<RegisterClass rclass>:
1588 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1589 [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>;
1591 multiclass BitEquivalence
1593 def v16i8: EQVVecInst<v16i8>;
1594 def v8i16: EQVVecInst<v8i16>;
1595 def v4i32: EQVVecInst<v4i32>;
1596 def v2i64: EQVVecInst<v2i64>;
1598 def v16i8_1: EQVVecPattern1<v16i8>;
1599 def v8i16_1: EQVVecPattern1<v8i16>;
1600 def v4i32_1: EQVVecPattern1<v4i32>;
1601 def v2i64_1: EQVVecPattern1<v2i64>;
1603 def v16i8_2: EQVVecPattern2<v16i8>;
1604 def v8i16_2: EQVVecPattern2<v8i16>;
1605 def v4i32_2: EQVVecPattern2<v4i32>;
1606 def v2i64_2: EQVVecPattern2<v2i64>;
1608 def v16i8_3: EQVVecPattern3<v16i8>;
1609 def v8i16_3: EQVVecPattern3<v8i16>;
1610 def v4i32_3: EQVVecPattern3<v4i32>;
1611 def v2i64_3: EQVVecPattern3<v2i64>;
1613 def r128: EQVRegInst<GPRC>;
1614 def r64: EQVRegInst<R64C>;
1615 def r32: EQVRegInst<R32C>;
1616 def r16: EQVRegInst<R16C>;
1617 def r8: EQVRegInst<R8C>;
1619 def r128_1: EQVRegPattern1<GPRC>;
1620 def r64_1: EQVRegPattern1<R64C>;
1621 def r32_1: EQVRegPattern1<R32C>;
1622 def r16_1: EQVRegPattern1<R16C>;
1623 def r8_1: EQVRegPattern1<R8C>;
1625 def r128_2: EQVRegPattern2<GPRC>;
1626 def r64_2: EQVRegPattern2<R64C>;
1627 def r32_2: EQVRegPattern2<R32C>;
1628 def r16_2: EQVRegPattern2<R16C>;
1629 def r8_2: EQVRegPattern2<R8C>;
1631 def r128_3: EQVRegPattern3<GPRC>;
1632 def r64_3: EQVRegPattern3<R64C>;
1633 def r32_3: EQVRegPattern3<R32C>;
1634 def r16_3: EQVRegPattern3<R16C>;
1635 def r8_3: EQVRegPattern3<R8C>;
1638 defm EQV: BitEquivalence;
1640 //===----------------------------------------------------------------------===//
1641 // Vector shuffle...
1642 //===----------------------------------------------------------------------===//
1643 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
1644 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
1645 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
1646 // the SPUISD::SHUFB opcode.
1647 //===----------------------------------------------------------------------===//
1649 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
1650 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
1651 IntegerOp, pattern>;
1653 class SHUFBVecInst<ValueType vectype>:
1654 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1655 [(set (vectype VECREG:$rT), (SPUshuffle (vectype VECREG:$rA),
1656 (vectype VECREG:$rB),
1657 (vectype VECREG:$rC)))]>;
1659 // It's this pattern that's probably the most useful, since SPUISelLowering
1660 // methods create a v16i8 vector for $rC:
1661 class SHUFBVecPat1<ValueType vectype, SPUInstr inst>:
1662 Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB),
1663 (v16i8 VECREG:$rC)),
1664 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1666 multiclass ShuffleBytes
1668 def v16i8 : SHUFBVecInst<v16i8>;
1669 def v8i16 : SHUFBVecInst<v8i16>;
1670 def v4i32 : SHUFBVecInst<v4i32>;
1671 def v2i64 : SHUFBVecInst<v2i64>;
1673 def v4f32 : SHUFBVecInst<v4f32>;
1674 def v2f64 : SHUFBVecInst<v2f64>;
1677 defm SHUFB : ShuffleBytes;
1679 def : SHUFBVecPat1<v8i16, SHUFBv16i8>;
1680 def : SHUFBVecPat1<v4i32, SHUFBv16i8>;
1681 def : SHUFBVecPat1<v2i64, SHUFBv16i8>;
1682 def : SHUFBVecPat1<v4f32, SHUFBv16i8>;
1683 def : SHUFBVecPat1<v2f64, SHUFBv16i8>;
1685 //===----------------------------------------------------------------------===//
1686 // Shift and rotate group:
1687 //===----------------------------------------------------------------------===//
1689 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
1690 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
1691 RotateShift, pattern>;
1693 class SHLHVecInst<ValueType vectype>:
1694 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1695 [(set (vectype VECREG:$rT),
1696 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
1698 // $rB gets promoted to 32-bit register type when confronted with
1699 // this llvm assembly code:
1701 // define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
1702 // %A = shl i16 %arg1, %arg2
1706 multiclass ShiftLeftHalfword
1708 def v8i16: SHLHVecInst<v8i16>;
1709 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1710 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1711 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1712 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1715 defm SHLH : ShiftLeftHalfword;
1717 //===----------------------------------------------------------------------===//
1719 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
1720 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
1721 RotateShift, pattern>;
1723 class SHLHIVecInst<ValueType vectype>:
1724 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1725 [(set (vectype VECREG:$rT),
1726 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
1728 multiclass ShiftLeftHalfwordImm
1730 def v8i16: SHLHIVecInst<v8i16>;
1731 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
1732 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
1735 defm SHLHI : ShiftLeftHalfwordImm;
1737 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
1738 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
1740 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
1741 (SHLHIr16 R16C:$rA, uimm7:$val)>;
1743 //===----------------------------------------------------------------------===//
1745 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
1746 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
1747 RotateShift, pattern>;
1749 multiclass ShiftLeftWord
1752 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1753 [(set (v4i32 VECREG:$rT),
1754 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
1756 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1757 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
1760 defm SHL: ShiftLeftWord;
1762 //===----------------------------------------------------------------------===//
1764 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
1765 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
1766 RotateShift, pattern>;
1768 multiclass ShiftLeftWordImm
1771 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1772 [(set (v4i32 VECREG:$rT),
1773 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
1776 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
1777 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
1780 defm SHLI : ShiftLeftWordImm;
1782 //===----------------------------------------------------------------------===//
1783 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
1784 // register) to the left. Vector form is here to ensure type correctness.
1786 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
1787 // of 7 bits is actually possible.
1789 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
1790 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
1791 // bytes with SHLQBY.
1793 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
1794 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
1795 RotateShift, pattern>;
1797 class SHLQBIVecInst<ValueType vectype>:
1798 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1799 [(set (vectype VECREG:$rT),
1800 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
1802 multiclass ShiftLeftQuadByBits
1804 def v16i8: SHLQBIVecInst<v16i8>;
1805 def v8i16: SHLQBIVecInst<v8i16>;
1806 def v4i32: SHLQBIVecInst<v4i32>;
1807 def v2i64: SHLQBIVecInst<v2i64>;
1810 defm SHLQBI : ShiftLeftQuadByBits;
1812 // See note above on SHLQBI. In this case, the predicate actually does then
1813 // enforcement, whereas with SHLQBI, we have to "take it on faith."
1814 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
1815 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
1816 RotateShift, pattern>;
1818 class SHLQBIIVecInst<ValueType vectype>:
1819 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1820 [(set (vectype VECREG:$rT),
1821 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
1823 multiclass ShiftLeftQuadByBitsImm
1825 def v16i8 : SHLQBIIVecInst<v16i8>;
1826 def v8i16 : SHLQBIIVecInst<v8i16>;
1827 def v4i32 : SHLQBIIVecInst<v4i32>;
1828 def v2i64 : SHLQBIIVecInst<v2i64>;
1831 defm SHLQBII : ShiftLeftQuadByBitsImm;
1833 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
1834 // not by bits. See notes above on SHLQBI.
1836 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
1837 RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB",
1838 RotateShift, pattern>;
1840 class SHLQBYVecInst<ValueType vectype>:
1841 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1842 [(set (vectype VECREG:$rT),
1843 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
1845 multiclass ShiftLeftQuadBytes
1847 def v16i8: SHLQBYVecInst<v16i8>;
1848 def v8i16: SHLQBYVecInst<v8i16>;
1849 def v4i32: SHLQBYVecInst<v4i32>;
1850 def v2i64: SHLQBYVecInst<v2i64>;
1851 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
1852 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
1855 defm SHLQBY: ShiftLeftQuadBytes;
1857 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
1858 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
1859 RotateShift, pattern>;
1861 class SHLQBYIVecInst<ValueType vectype>:
1862 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1863 [(set (vectype VECREG:$rT),
1864 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
1866 multiclass ShiftLeftQuadBytesImm
1868 def v16i8: SHLQBYIVecInst<v16i8>;
1869 def v8i16: SHLQBYIVecInst<v8i16>;
1870 def v4i32: SHLQBYIVecInst<v4i32>;
1871 def v2i64: SHLQBYIVecInst<v2i64>;
1872 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
1874 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
1877 defm SHLQBYI : ShiftLeftQuadBytesImm;
1879 // Special form for truncating i64 to i32:
1880 def SHLQBYItrunc64: SHLQBYIInst<(outs R32C:$rT), (ins R64C:$rA, u7imm_i32:$val),
1881 [/* no pattern, see below */]>;
1883 def : Pat<(trunc R64C:$rSrc),
1884 (SHLQBYItrunc64 R64C:$rSrc, 4)>;
1886 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1888 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1889 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
1890 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
1891 RotateShift, pattern>;
1893 class ROTHVecInst<ValueType vectype>:
1894 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1895 [(set (vectype VECREG:$rT),
1896 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
1898 class ROTHRegInst<RegisterClass rclass>:
1899 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1900 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
1902 multiclass RotateLeftHalfword
1904 def v8i16: ROTHVecInst<v8i16>;
1905 def r16: ROTHRegInst<R16C>;
1908 defm ROTH: RotateLeftHalfword;
1910 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1911 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
1913 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1914 // Rotate halfword, immediate:
1915 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1916 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
1917 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
1918 RotateShift, pattern>;
1920 class ROTHIVecInst<ValueType vectype>:
1921 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1922 [(set (vectype VECREG:$rT),
1923 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
1925 multiclass RotateLeftHalfwordImm
1927 def v8i16: ROTHIVecInst<v8i16>;
1928 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
1929 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
1930 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
1931 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
1934 defm ROTHI: RotateLeftHalfwordImm;
1936 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
1937 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
1939 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1941 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1943 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
1944 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
1945 RotateShift, pattern>;
1947 class ROTVecInst<ValueType vectype>:
1948 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1949 [(set (vectype VECREG:$rT),
1950 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
1952 class ROTRegInst<RegisterClass rclass>:
1953 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
1955 (rotl rclass:$rA, R32C:$rB))]>;
1957 multiclass RotateLeftWord
1959 def v4i32: ROTVecInst<v4i32>;
1960 def r32: ROTRegInst<R32C>;
1963 defm ROT: RotateLeftWord;
1965 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
1967 def ROTr32_r16_anyext:
1968 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
1969 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
1971 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
1972 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
1974 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
1975 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
1977 def ROTr32_r8_anyext:
1978 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
1979 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
1981 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
1982 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
1984 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
1985 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
1987 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1988 // Rotate word, immediate
1989 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1991 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
1992 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
1993 RotateShift, pattern>;
1995 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
1996 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
1997 [(set (vectype VECREG:$rT),
1998 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2000 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2001 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2002 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2004 multiclass RotateLeftWordImm
2006 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2007 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
2008 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
2010 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
2011 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
2012 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
2015 defm ROTI : RotateLeftWordImm;
2017 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2018 // Rotate quad by byte (count)
2019 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2021 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2022 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2023 RotateShift, pattern>;
2025 class ROTQBYVecInst<ValueType vectype>:
2026 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2027 [(set (vectype VECREG:$rT),
2028 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2030 multiclass RotateQuadLeftByBytes
2032 def v16i8: ROTQBYVecInst<v16i8>;
2033 def v8i16: ROTQBYVecInst<v8i16>;
2034 def v4i32: ROTQBYVecInst<v4i32>;
2035 def v2i64: ROTQBYVecInst<v2i64>;
2038 defm ROTQBY: RotateQuadLeftByBytes;
2040 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
2041 (ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
2042 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
2043 (ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
2044 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
2045 (ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
2046 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
2047 (ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
2049 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2050 // Rotate quad by byte (count), immediate
2051 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2053 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2054 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2055 RotateShift, pattern>;
2057 class ROTQBYIVecInst<ValueType vectype>:
2058 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2059 [(set (vectype VECREG:$rT),
2060 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2062 multiclass RotateQuadByBytesImm
2064 def v16i8: ROTQBYIVecInst<v16i8>;
2065 def v8i16: ROTQBYIVecInst<v8i16>;
2066 def v4i32: ROTQBYIVecInst<v4i32>;
2067 def v2i64: ROTQBYIVecInst<v2i64>;
2070 defm ROTQBYI: RotateQuadByBytesImm;
2072 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2073 (ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
2074 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2075 (ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
2076 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2077 (ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
2078 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
2079 (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
2081 // See ROTQBY note above.
2083 RI7Form<0b00110011100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2084 "rotqbybi\t$rT, $rA, $val", RotateShift,
2087 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2088 // See ROTQBY note above.
2090 // Assume that the user of this instruction knows to shift the rotate count
2092 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2094 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2095 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2096 RotateShift, pattern>;
2098 class ROTQBIVecInst<ValueType vectype>:
2099 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2100 [/* no pattern yet */]>;
2102 class ROTQBIRegInst<RegisterClass rclass>:
2103 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2104 [/* no pattern yet */]>;
2106 multiclass RotateQuadByBitCount
2108 def v16i8: ROTQBIVecInst<v16i8>;
2109 def v8i16: ROTQBIVecInst<v8i16>;
2110 def v4i32: ROTQBIVecInst<v4i32>;
2111 def v2i64: ROTQBIVecInst<v2i64>;
2113 def r128: ROTQBIRegInst<GPRC>;
2114 def r64: ROTQBIRegInst<R64C>;
2117 defm ROTQBI: RotateQuadByBitCount;
2119 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2120 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2121 RotateShift, pattern>;
2123 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2125 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2126 [/* no pattern yet */]>;
2128 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2130 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2131 [/* no pattern yet */]>;
2133 multiclass RotateQuadByBitCountImm
2135 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2136 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2137 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2138 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2140 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2141 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2144 defm ROTQBII : RotateQuadByBitCountImm;
2146 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2147 // ROTHM v8i16 form:
2148 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2149 // so this only matches a synthetically generated/lowered code
2151 // NOTE(2): $rB must be negated before the right rotate!
2152 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2154 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2155 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2156 RotateShift, pattern>;
2159 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2160 [/* see patterns below - $rB must be negated */]>;
2162 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2163 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2165 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2166 (ROTHMv8i16 VECREG:$rA,
2167 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2169 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2170 (ROTHMv8i16 VECREG:$rA,
2171 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2173 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2174 // Note: This instruction doesn't match a pattern because rB must be negated
2175 // for the instruction to work. Thus, the pattern below the instruction!
2178 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2179 [/* see patterns below - $rB must be negated! */]>;
2181 def : Pat<(srl R16C:$rA, R32C:$rB),
2182 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2184 def : Pat<(srl R16C:$rA, R16C:$rB),
2186 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2188 def : Pat<(srl R16C:$rA, R8C:$rB),
2190 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2192 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2193 // that the immediate can be complemented, so that the user doesn't have to
2196 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2197 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2198 RotateShift, pattern>;
2201 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2202 [/* no pattern */]>;
2204 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2205 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2207 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2208 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2210 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2211 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2214 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2215 [/* no pattern */]>;
2217 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2218 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2220 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2221 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2223 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2224 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2226 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2227 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2228 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2229 RotateShift, pattern>;
2232 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2233 [/* see patterns below - $rB must be negated */]>;
2235 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
2236 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2238 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
2239 (ROTMv4i32 VECREG:$rA,
2240 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2242 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
2243 (ROTMv4i32 VECREG:$rA,
2244 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2247 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2248 [/* see patterns below - $rB must be negated */]>;
2250 def : Pat<(srl R32C:$rA, R32C:$rB),
2251 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2253 def : Pat<(srl R32C:$rA, R16C:$rB),
2255 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2257 def : Pat<(srl R32C:$rA, R8C:$rB),
2259 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2261 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2263 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2264 "rotmi\t$rT, $rA, $val", RotateShift,
2265 [(set (v4i32 VECREG:$rT),
2266 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2268 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
2269 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2271 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
2272 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2274 // ROTMI r32 form: know how to complement the immediate value.
2276 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2277 "rotmi\t$rT, $rA, $val", RotateShift,
2278 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2280 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2281 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2283 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2284 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2286 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2287 // ROTQMBYvec: This is a vector form merely so that when used in an
2288 // instruction pattern, type checking will succeed. This instruction assumes
2289 // that the user knew to negate $rB.
2291 // Using the SPUrotquad_rz_bytes target-specific DAG node, the patterns
2292 // ensure that $rB is negated.
2293 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2295 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2296 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2297 RotateShift, pattern>;
2299 class ROTQMBYVecInst<ValueType vectype>:
2300 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2301 [/* no pattern, $rB must be negated */]>;
2303 class ROTQMBYRegInst<RegisterClass rclass>:
2304 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2306 (SPUrotquad_rz_bytes rclass:$rA, R32C:$rB))]>;
2308 multiclass RotateQuadBytes
2310 def v16i8: ROTQMBYVecInst<v16i8>;
2311 def v8i16: ROTQMBYVecInst<v8i16>;
2312 def v4i32: ROTQMBYVecInst<v4i32>;
2313 def v2i64: ROTQMBYVecInst<v2i64>;
2315 def r128: ROTQMBYRegInst<GPRC>;
2316 def r64: ROTQMBYRegInst<R64C>;
2319 defm ROTQMBY : RotateQuadBytes;
2321 def : Pat<(SPUrotquad_rz_bytes (v16i8 VECREG:$rA), R32C:$rB),
2322 (ROTQMBYv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2323 def : Pat<(SPUrotquad_rz_bytes (v8i16 VECREG:$rA), R32C:$rB),
2324 (ROTQMBYv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2325 def : Pat<(SPUrotquad_rz_bytes (v4i32 VECREG:$rA), R32C:$rB),
2326 (ROTQMBYv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2327 def : Pat<(SPUrotquad_rz_bytes (v2i64 VECREG:$rA), R32C:$rB),
2328 (ROTQMBYv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2329 def : Pat<(SPUrotquad_rz_bytes GPRC:$rA, R32C:$rB),
2330 (ROTQMBYr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2331 def : Pat<(SPUrotquad_rz_bytes R64C:$rA, R32C:$rB),
2332 (ROTQMBYr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2334 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2335 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2336 RotateShift, pattern>;
2338 class ROTQMBYIVecInst<ValueType vectype>:
2339 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2340 [(set (vectype VECREG:$rT),
2341 (SPUrotquad_rz_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2343 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2344 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2346 (SPUrotquad_rz_bytes rclass:$rA, (inttype pred:$val)))]>;
2348 multiclass RotateQuadBytesImm
2350 def v16i8: ROTQMBYIVecInst<v16i8>;
2351 def v8i16: ROTQMBYIVecInst<v8i16>;
2352 def v4i32: ROTQMBYIVecInst<v4i32>;
2353 def v2i64: ROTQMBYIVecInst<v2i64>;
2355 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2356 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2359 defm ROTQMBYI : RotateQuadBytesImm;
2362 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2363 // Rotate right and mask by bit count
2364 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2366 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2367 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2368 RotateShift, pattern>;
2370 class ROTQMBYBIVecInst<ValueType vectype>:
2371 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2372 [/* no pattern, intrinsic? */]>;
2374 multiclass RotateMaskQuadByBitCount
2376 def v16i8: ROTQMBYBIVecInst<v16i8>;
2377 def v8i16: ROTQMBYBIVecInst<v8i16>;
2378 def v4i32: ROTQMBYBIVecInst<v4i32>;
2379 def v2i64: ROTQMBYBIVecInst<v2i64>;
2382 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2384 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2385 // Rotate quad and mask by bits
2386 // Note that the rotate amount has to be negated
2387 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2389 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2390 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2391 RotateShift, pattern>;
2393 class ROTQMBIVecInst<ValueType vectype>:
2394 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2395 [/* no pattern */]>;
2397 class ROTQMBIRegInst<RegisterClass rclass>:
2398 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2399 [/* no pattern */]>;
2401 multiclass RotateMaskQuadByBits
2403 def v16i8: ROTQMBIVecInst<v16i8>;
2404 def v8i16: ROTQMBIVecInst<v8i16>;
2405 def v4i32: ROTQMBIVecInst<v4i32>;
2406 def v2i64: ROTQMBIVecInst<v2i64>;
2408 def r128: ROTQMBIRegInst<GPRC>;
2409 def r64: ROTQMBIRegInst<R64C>;
2412 defm ROTQMBI: RotateMaskQuadByBits;
2414 def : Pat<(SPUrotquad_rz_bits (v16i8 VECREG:$rA), R32C:$rB),
2415 (ROTQMBIv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2416 def : Pat<(SPUrotquad_rz_bits (v8i16 VECREG:$rA), R32C:$rB),
2417 (ROTQMBIv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2418 def : Pat<(SPUrotquad_rz_bits (v4i32 VECREG:$rA), R32C:$rB),
2419 (ROTQMBIv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2420 def : Pat<(SPUrotquad_rz_bits (v2i64 VECREG:$rA), R32C:$rB),
2421 (ROTQMBIv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2422 def : Pat<(SPUrotquad_rz_bits GPRC:$rA, R32C:$rB),
2423 (ROTQMBIr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2424 def : Pat<(SPUrotquad_rz_bits R64C:$rA, R32C:$rB),
2425 (ROTQMBIr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2427 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2428 // Rotate quad and mask by bits, immediate
2429 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2431 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2432 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2433 RotateShift, pattern>;
2435 class ROTQMBIIVecInst<ValueType vectype>:
2436 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2437 [(set (vectype VECREG:$rT),
2438 (SPUrotquad_rz_bits (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2440 class ROTQMBIIRegInst<RegisterClass rclass>:
2441 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2443 (SPUrotquad_rz_bits rclass:$rA, (i32 uimm7:$val)))]>;
2445 multiclass RotateMaskQuadByBitsImm
2447 def v16i8: ROTQMBIIVecInst<v16i8>;
2448 def v8i16: ROTQMBIIVecInst<v8i16>;
2449 def v4i32: ROTQMBIIVecInst<v4i32>;
2450 def v2i64: ROTQMBIIVecInst<v2i64>;
2452 def r128: ROTQMBIIRegInst<GPRC>;
2453 def r64: ROTQMBIIRegInst<R64C>;
2456 defm ROTQMBII: RotateMaskQuadByBitsImm;
2458 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2459 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2462 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2463 "rotmah\t$rT, $rA, $rB", RotateShift,
2464 [/* see patterns below - $rB must be negated */]>;
2466 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2467 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2469 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2470 (ROTMAHv8i16 VECREG:$rA,
2471 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2473 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2474 (ROTMAHv8i16 VECREG:$rA,
2475 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2478 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2479 "rotmah\t$rT, $rA, $rB", RotateShift,
2480 [/* see patterns below - $rB must be negated */]>;
2482 def : Pat<(sra R16C:$rA, R32C:$rB),
2483 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2485 def : Pat<(sra R16C:$rA, R16C:$rB),
2486 (ROTMAHr16 R16C:$rA,
2487 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2489 def : Pat<(sra R16C:$rA, R8C:$rB),
2490 (ROTMAHr16 R16C:$rA,
2491 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2494 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2495 "rotmahi\t$rT, $rA, $val", RotateShift,
2496 [(set (v8i16 VECREG:$rT),
2497 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2499 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2500 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2502 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2503 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2506 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2507 "rotmahi\t$rT, $rA, $val", RotateShift,
2508 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2510 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2511 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2513 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2514 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2517 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2518 "rotma\t$rT, $rA, $rB", RotateShift,
2519 [/* see patterns below - $rB must be negated */]>;
2521 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2522 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2524 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2525 (ROTMAv4i32 (v4i32 VECREG:$rA),
2526 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2528 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2529 (ROTMAv4i32 (v4i32 VECREG:$rA),
2530 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2533 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2534 "rotma\t$rT, $rA, $rB", RotateShift,
2535 [/* see patterns below - $rB must be negated */]>;
2537 def : Pat<(sra R32C:$rA, R32C:$rB),
2538 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2540 def : Pat<(sra R32C:$rA, R16C:$rB),
2542 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2544 def : Pat<(sra R32C:$rA, R8C:$rB),
2546 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2549 RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2550 "rotmai\t$rT, $rA, $val", RotateShift,
2551 [(set (v4i32 VECREG:$rT),
2552 (SPUvec_sra VECREG:$rA, (i32 uimm7:$val)))]>;
2554 def : Pat<(SPUvec_sra VECREG:$rA, (i16 uimm7:$val)),
2555 (ROTMAIv4i32 VECREG:$rA, uimm7:$val)>;
2558 RRForm<0b01011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2559 "rotmai\t$rT, $rA, $val", RotateShift,
2560 [(set R32C:$rT, (sra R32C:$rA, (i32 uimm7:$val)))]>;
2562 def : Pat<(sra R32C:$rA, (i16 uimm7:$val)),
2563 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2565 def : Pat<(sra R32C:$rA, (i8 uimm7:$val)),
2566 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2568 //===----------------------------------------------------------------------===//
2569 // Branch and conditionals:
2570 //===----------------------------------------------------------------------===//
2572 let isTerminator = 1, isBarrier = 1 in {
2573 // Halt If Equal (r32 preferred slot only, no vector form)
2575 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2576 "heq\t$rA, $rB", BranchResolv,
2577 [/* no pattern to match */]>;
2580 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2581 "heqi\t$rA, $val", BranchResolv,
2582 [/* no pattern to match */]>;
2584 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2585 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2587 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2588 "hgt\t$rA, $rB", BranchResolv,
2589 [/* no pattern to match */]>;
2592 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2593 "hgti\t$rA, $val", BranchResolv,
2594 [/* no pattern to match */]>;
2597 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2598 "hlgt\t$rA, $rB", BranchResolv,
2599 [/* no pattern to match */]>;
2602 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2603 "hlgti\t$rA, $val", BranchResolv,
2604 [/* no pattern to match */]>;
2607 //------------------------------------------------------------------------
2608 // Comparison operators:
2609 //------------------------------------------------------------------------
2611 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
2612 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
2615 multiclass CmpEqualByte
2618 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2619 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2620 (v8i16 VECREG:$rB)))]>;
2623 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2624 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
2627 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
2628 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
2631 multiclass CmpEqualByteImm
2634 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2635 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
2636 v16i8SExt8Imm:$val))]>;
2638 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2639 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
2642 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
2643 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
2646 multiclass CmpEqualHalfword
2648 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2649 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2650 (v8i16 VECREG:$rB)))]>;
2652 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2653 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
2656 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
2657 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
2660 multiclass CmpEqualHalfwordImm
2662 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2663 [(set (v8i16 VECREG:$rT),
2664 (seteq (v8i16 VECREG:$rA),
2665 (v8i16 v8i16SExt10Imm:$val)))]>;
2666 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2667 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
2670 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
2671 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
2674 multiclass CmpEqualWord
2676 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2677 [(set (v4i32 VECREG:$rT),
2678 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2680 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2681 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2684 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
2685 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
2688 multiclass CmpEqualWordImm
2690 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2691 [(set (v4i32 VECREG:$rT),
2692 (seteq (v4i32 VECREG:$rA),
2693 (v4i32 v4i32SExt16Imm:$val)))]>;
2695 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2696 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2699 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2700 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
2703 multiclass CmpGtrByte
2706 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2707 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2708 (v8i16 VECREG:$rB)))]>;
2711 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2712 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
2715 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2716 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
2719 multiclass CmpGtrByteImm
2722 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2723 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
2724 v16i8SExt8Imm:$val))]>;
2726 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2727 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
2730 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2731 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
2734 multiclass CmpGtrHalfword
2736 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2737 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2738 (v8i16 VECREG:$rB)))]>;
2740 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2741 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
2744 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2745 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
2748 multiclass CmpGtrHalfwordImm
2750 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2751 [(set (v8i16 VECREG:$rT),
2752 (setgt (v8i16 VECREG:$rA),
2753 (v8i16 v8i16SExt10Imm:$val)))]>;
2754 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2755 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
2758 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
2759 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
2762 multiclass CmpGtrWord
2764 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2765 [(set (v4i32 VECREG:$rT),
2766 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2768 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2769 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
2772 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2773 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
2776 multiclass CmpGtrWordImm
2778 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2779 [(set (v4i32 VECREG:$rT),
2780 (setgt (v4i32 VECREG:$rA),
2781 (v4i32 v4i32SExt16Imm:$val)))]>;
2783 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2784 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
2787 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2788 RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB",
2791 multiclass CmpLGtrByte
2794 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2795 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2796 (v8i16 VECREG:$rB)))]>;
2799 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2800 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
2803 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2804 RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val",
2807 multiclass CmpLGtrByteImm
2810 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2811 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
2812 v16i8SExt8Imm:$val))]>;
2814 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2815 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
2818 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2819 RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB",
2822 multiclass CmpLGtrHalfword
2824 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2825 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2826 (v8i16 VECREG:$rB)))]>;
2828 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2829 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
2832 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2833 RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val",
2836 multiclass CmpLGtrHalfwordImm
2838 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2839 [(set (v8i16 VECREG:$rT),
2840 (setugt (v8i16 VECREG:$rA),
2841 (v8i16 v8i16SExt10Imm:$val)))]>;
2842 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2843 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
2846 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
2847 RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB",
2850 multiclass CmpLGtrWord
2852 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2853 [(set (v4i32 VECREG:$rT),
2854 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2856 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2857 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
2860 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2861 RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val",
2864 multiclass CmpLGtrWordImm
2866 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2867 [(set (v4i32 VECREG:$rT),
2868 (setugt (v4i32 VECREG:$rA),
2869 (v4i32 v4i32SExt16Imm:$val)))]>;
2871 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2872 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
2875 defm CEQB : CmpEqualByte;
2876 defm CEQBI : CmpEqualByteImm;
2877 defm CEQH : CmpEqualHalfword;
2878 defm CEQHI : CmpEqualHalfwordImm;
2879 defm CEQ : CmpEqualWord;
2880 defm CEQI : CmpEqualWordImm;
2881 defm CGTB : CmpGtrByte;
2882 defm CGTBI : CmpGtrByteImm;
2883 defm CGTH : CmpGtrHalfword;
2884 defm CGTHI : CmpGtrHalfwordImm;
2885 defm CGT : CmpGtrWord;
2886 defm CGTI : CmpGtrWordImm;
2887 defm CLGTB : CmpLGtrByte;
2888 defm CLGTBI : CmpLGtrByteImm;
2889 defm CLGTH : CmpLGtrHalfword;
2890 defm CLGTHI : CmpLGtrHalfwordImm;
2891 defm CLGT : CmpLGtrWord;
2892 defm CLGTI : CmpLGtrWordImm;
2894 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2895 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
2896 // define a pattern to generate the right code, as a binary operator
2897 // (in a manner of speaking.)
2899 // N.B.: This only matches the setcc set of conditionals. Special pattern
2900 // matching is used for select conditionals.
2901 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2903 class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
2904 SPUInstr xorinst, SPUInstr cmpare>:
2905 Pat<(cond rclass:$rA, rclass:$rB),
2906 (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
2908 class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
2909 PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
2910 Pat<(cond rclass:$rA, (inttype immpred:$imm)),
2911 (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
2913 def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
2914 def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
2916 def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
2917 def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
2919 def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
2920 def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
2922 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
2923 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
2924 Pat<(cond rclass:$rA, rclass:$rB),
2925 (binop (cmpOp1 rclass:$rA, rclass:$rB),
2926 (cmpOp2 rclass:$rA, rclass:$rB))>;
2928 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
2930 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
2931 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
2932 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
2933 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
2935 def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
2936 def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
2937 def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
2938 def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
2939 def : Pat<(setle R8C:$rA, R8C:$rB),
2940 (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
2941 def : Pat<(setle R8C:$rA, immU8:$imm),
2942 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
2944 def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
2945 def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
2946 ORr16, CGTHIr16, CEQHIr16>;
2947 def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
2948 def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
2949 def : Pat<(setle R16C:$rA, R16C:$rB),
2950 (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
2951 def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
2952 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
2954 def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
2955 def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
2956 ORr32, CGTIr32, CEQIr32>;
2957 def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
2958 def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
2959 def : Pat<(setle R32C:$rA, R32C:$rB),
2960 (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
2961 def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
2962 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
2964 def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
2965 def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
2966 def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
2967 def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
2968 def : Pat<(setule R8C:$rA, R8C:$rB),
2969 (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
2970 def : Pat<(setule R8C:$rA, immU8:$imm),
2971 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
2973 def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
2974 def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
2975 ORr16, CLGTHIr16, CEQHIr16>;
2976 def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
2977 def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
2978 CLGTHIr16, CEQHIr16>;
2979 def : Pat<(setule R16C:$rA, R16C:$rB),
2980 (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
2981 def : Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
2982 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
2984 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
2985 def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
2986 ORr32, CLGTIr32, CEQIr32>;
2987 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
2988 def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
2989 def : Pat<(setule R32C:$rA, R32C:$rB),
2990 (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
2991 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
2992 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
2994 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2995 // select conditional patterns:
2996 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2998 class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
2999 SPUInstr selinstr, SPUInstr cmpare>:
3000 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3001 rclass:$rTrue, rclass:$rFalse),
3002 (selinstr rclass:$rTrue, rclass:$rFalse,
3003 (cmpare rclass:$rA, rclass:$rB))>;
3005 class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3006 PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
3007 Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
3008 rclass:$rTrue, rclass:$rFalse),
3009 (selinstr rclass:$rTrue, rclass:$rFalse,
3010 (cmpare rclass:$rA, immpred:$imm))>;
3012 def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
3013 def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
3014 def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
3015 def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
3016 def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
3017 def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
3019 def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
3020 def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
3021 def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
3022 def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
3023 def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
3024 def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
3026 def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
3027 def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
3028 def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
3029 def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
3030 def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
3031 def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
3033 class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3034 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3036 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3037 rclass:$rFalse, rclass:$rTrue),
3038 (selinstr rclass:$rTrue, rclass:$rFalse,
3039 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3040 (cmpOp2 rclass:$rA, rclass:$rB)))>;
3042 class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3044 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3046 Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
3047 rclass:$rTrue, rclass:$rFalse),
3048 (selinstr rclass:$rFalse, rclass:$rTrue,
3049 (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
3050 (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
3052 def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
3053 def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
3054 SELBr8, ORr8, CGTBIr8, CEQBIr8>;
3056 def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
3057 def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
3058 SELBr16, ORr16, CGTHIr16, CEQHIr16>;
3060 def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
3061 def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
3062 SELBr32, ORr32, CGTIr32, CEQIr32>;
3064 def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
3065 def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
3066 SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
3068 def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
3069 def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
3070 SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
3072 def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
3073 def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
3074 SELBr32, ORr32, CLGTIr32, CEQIr32>;
3076 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3079 // All calls clobber the non-callee-saved registers:
3080 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
3081 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
3082 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
3083 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
3084 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
3085 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
3086 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
3087 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
3088 // All of these instructions use $lr (aka $0)
3090 // Branch relative and set link: Used if we actually know that the target
3091 // is within [-32768, 32767] bytes of the target
3093 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
3094 "brsl\t$$lr, $func",
3095 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
3097 // Branch absolute and set link: Used if we actually know that the target
3098 // is an absolute address
3100 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
3101 "brasl\t$$lr, $func",
3102 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
3104 // Branch indirect and set link if external data. These instructions are not
3105 // actually generated, matched by an intrinsic:
3106 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
3107 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
3108 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
3109 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
3111 // Branch indirect and set link. This is the "X-form" address version of a
3114 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
3117 // Unconditional branches:
3118 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
3120 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3124 // Unconditional, absolute address branch
3126 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3128 [/* no pattern */]>;
3132 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3134 // Various branches:
3136 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
3137 "brnz\t$rCond,$dest",
3139 [(brcond R32C:$rCond, bb:$dest)]>;
3142 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
3145 [/* no pattern */]>;
3148 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
3149 "brhnz\t$rCond,$dest",
3151 [(brcond R16C:$rCond, bb:$dest)]>;
3154 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
3157 [/* no pattern */]>;
3161 BICondForm<0b10010100100, "binz\t$rA, $func",
3162 [(SPUbinz R32C:$rA, R32C:$func)]>;
3165 BICondForm<0b00010100100, "biz\t$rA, $func",
3166 [(SPUbiz R32C:$rA, R32C:$func)]>;
3170 //===----------------------------------------------------------------------===//
3171 // setcc and brcond patterns:
3172 //===----------------------------------------------------------------------===//
3174 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3175 (BRHZ R16C:$rA, bb:$dest)>;
3176 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3177 (BRHNZ R16C:$rA, bb:$dest)>;
3179 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3180 (BRZ R32C:$rA, bb:$dest)>;
3181 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3182 (BRNZ R32C:$rA, bb:$dest)>;
3184 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3186 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3187 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3189 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3190 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3192 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3193 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3195 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3196 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3199 defm BRCONDeq : BranchCondEQ<seteq, BRHZ, BRZ>;
3200 defm BRCONDne : BranchCondEQ<setne, BRHNZ, BRNZ>;
3202 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3204 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3205 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3207 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3208 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3210 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3211 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3213 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3214 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3217 defm BRCONDugt : BranchCondLGT<setugt, BRHNZ, BRNZ>;
3218 defm BRCONDule : BranchCondLGT<setule, BRHZ, BRZ>;
3220 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3221 SPUInstr orinst32, SPUInstr brinst32>
3223 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3224 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3225 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3228 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3229 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3230 (CEQHr16 R16C:$rA, R16:$rB)),
3233 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3234 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3235 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3238 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3239 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3240 (CEQr32 R32C:$rA, R32C:$rB)),
3244 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZ, ORr32, BRNZ>;
3245 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZ, ORr32, BRZ>;
3247 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3249 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3250 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3252 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3253 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3255 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3256 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3258 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3259 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3262 defm BRCONDgt : BranchCondGT<setgt, BRHNZ, BRNZ>;
3263 defm BRCONDle : BranchCondGT<setle, BRHZ, BRZ>;
3265 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3266 SPUInstr orinst32, SPUInstr brinst32>
3268 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3269 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3270 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3273 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3274 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3275 (CEQHr16 R16C:$rA, R16:$rB)),
3278 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3279 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3280 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3283 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3284 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3285 (CEQr32 R32C:$rA, R32C:$rB)),
3289 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZ, ORr32, BRNZ>;
3290 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZ, ORr32, BRZ>;
3292 let isTerminator = 1, isBarrier = 1 in {
3293 let isReturn = 1 in {
3295 RETForm<"bi\t$$lr", [(retflag)]>;
3299 //===----------------------------------------------------------------------===//
3300 // Single precision floating point instructions
3301 //===----------------------------------------------------------------------===//
3304 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3305 "fa\t$rT, $rA, $rB", SPrecFP,
3306 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3309 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3310 "fa\t$rT, $rA, $rB", SPrecFP,
3311 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3314 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3315 "fs\t$rT, $rA, $rB", SPrecFP,
3316 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3319 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3320 "fs\t$rT, $rA, $rB", SPrecFP,
3321 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3323 // Floating point reciprocal estimate
3325 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
3326 "frest\t$rT, $rA", SPrecFP,
3327 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
3330 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
3331 "frest\t$rT, $rA", SPrecFP,
3332 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
3334 // Floating point interpolate (used in conjunction with reciprocal estimate)
3336 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3337 "fi\t$rT, $rA, $rB", SPrecFP,
3338 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
3339 (v4f32 VECREG:$rB)))]>;
3342 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3343 "fi\t$rT, $rA, $rB", SPrecFP,
3344 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
3346 // Floating Compare Equal
3348 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3349 "fceq\t$rT, $rA, $rB", SPrecFP,
3350 [(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
3353 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3354 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3355 [(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3358 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3359 "fcgt\t$rT, $rA, $rB", SPrecFP,
3360 [(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
3363 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3364 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3365 [(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3367 // FP Status and Control Register Write
3368 // Why isn't rT a don't care in the ISA?
3369 // Should we create a special RRForm_3 for this guy and zero out the rT?
3371 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3372 "fscrwr\t$rA", SPrecFP,
3373 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3375 // FP Status and Control Register Read
3377 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3378 "fscrrd\t$rT", SPrecFP,
3379 [/* This instruction requires an intrinsic */]>;
3381 // llvm instruction space
3382 // How do these map onto cell instructions?
3384 // frest rC rB # c = 1/b (both lines)
3386 // fm rD rA rC # d = a * 1/b
3387 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3388 // fma rB rB rC rD # b = b * c + d
3389 // = -(d *b -a) * c + d
3390 // = a * c - c ( a *b *c - a)
3395 // These llvm instructions will actually map to library calls.
3396 // All that's needed, then, is to check that the appropriate library is
3397 // imported and do a brsl to the proper function name.
3398 // frem # fmod(x, y): x - (x/y) * y
3399 // (Note: fmod(double, double), fmodf(float,float)
3403 // Unimplemented SPU instruction space
3404 // floating reciprocal absolute square root estimate (frsqest)
3406 // The following are probably just intrinsics
3407 // status and control register write
3408 // status and control register read
3410 //--------------------------------------
3411 // Floating point multiply instructions
3412 //--------------------------------------
3415 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3416 "fm\t$rT, $rA, $rB", SPrecFP,
3417 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
3418 (v4f32 VECREG:$rB)))]>;
3421 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3422 "fm\t$rT, $rA, $rB", SPrecFP,
3423 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
3425 // Floating point multiply and add
3426 // e.g. d = c + (a * b)
3428 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3429 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3430 [(set (v4f32 VECREG:$rT),
3431 (fadd (v4f32 VECREG:$rC),
3432 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
3435 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3436 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3437 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3439 // FP multiply and subtract
3440 // Subtracts value in rC from product
3443 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3444 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3445 [(set (v4f32 VECREG:$rT),
3446 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
3447 (v4f32 VECREG:$rC)))]>;
3450 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3451 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3453 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
3455 // Floating Negative Mulitply and Subtract
3456 // Subtracts product from value in rC
3457 // res = fneg(fms a b c)
3460 // NOTE: subtraction order
3464 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3465 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3466 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3469 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3470 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3471 [(set (v4f32 VECREG:$rT),
3472 (fsub (v4f32 VECREG:$rC),
3473 (fmul (v4f32 VECREG:$rA),
3474 (v4f32 VECREG:$rB))))]>;
3476 //--------------------------------------
3477 // Floating Point Conversions
3478 // Signed conversions:
3480 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3481 "csflt\t$rT, $rA, 0", SPrecFP,
3482 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
3484 // Convert signed integer to floating point
3486 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
3487 "csflt\t$rT, $rA, 0", SPrecFP,
3488 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
3490 // Convert unsigned into to float
3492 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3493 "cuflt\t$rT, $rA, 0", SPrecFP,
3494 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
3497 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
3498 "cuflt\t$rT, $rA, 0", SPrecFP,
3499 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
3501 // Convert float to unsigned int
3502 // Assume that scale = 0
3505 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3506 "cfltu\t$rT, $rA, 0", SPrecFP,
3507 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
3510 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3511 "cfltu\t$rT, $rA, 0", SPrecFP,
3512 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
3514 // Convert float to signed int
3515 // Assume that scale = 0
3518 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3519 "cflts\t$rT, $rA, 0", SPrecFP,
3520 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
3523 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3524 "cflts\t$rT, $rA, 0", SPrecFP,
3525 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
3527 //===----------------------------------------------------------------------==//
3528 // Single<->Double precision conversions
3529 //===----------------------------------------------------------------------==//
3531 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
3532 // v4f32, output is v2f64--which goes in the name?)
3534 // Floating point extend single to double
3535 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
3536 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
3539 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3540 "fesd\t$rT, $rA", SPrecFP,
3541 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
3544 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
3545 "fesd\t$rT, $rA", SPrecFP,
3546 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
3548 // Floating point round double to single
3550 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3551 // "frds\t$rT, $rA,", SPrecFP,
3552 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
3555 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
3556 "frds\t$rT, $rA", SPrecFP,
3557 [(set R32FP:$rT, (fround R64FP:$rA))]>;
3559 //ToDo include anyextend?
3561 //===----------------------------------------------------------------------==//
3562 // Double precision floating point instructions
3563 //===----------------------------------------------------------------------==//
3565 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3566 "dfa\t$rT, $rA, $rB", DPrecFP,
3567 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
3570 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3571 "dfa\t$rT, $rA, $rB", DPrecFP,
3572 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3575 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3576 "dfs\t$rT, $rA, $rB", DPrecFP,
3577 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
3580 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3581 "dfs\t$rT, $rA, $rB", DPrecFP,
3582 [(set (v2f64 VECREG:$rT),
3583 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3586 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3587 "dfm\t$rT, $rA, $rB", DPrecFP,
3588 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
3591 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3592 "dfm\t$rT, $rA, $rB", DPrecFP,
3593 [(set (v2f64 VECREG:$rT),
3594 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3597 RRForm<0b00111010110, (outs R64FP:$rT),
3598 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3599 "dfma\t$rT, $rA, $rB", DPrecFP,
3600 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3601 RegConstraint<"$rC = $rT">,
3605 RRForm<0b00111010110, (outs VECREG:$rT),
3606 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3607 "dfma\t$rT, $rA, $rB", DPrecFP,
3608 [(set (v2f64 VECREG:$rT),
3609 (fadd (v2f64 VECREG:$rC),
3610 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
3611 RegConstraint<"$rC = $rT">,
3615 RRForm<0b10111010110, (outs R64FP:$rT),
3616 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3617 "dfms\t$rT, $rA, $rB", DPrecFP,
3618 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
3619 RegConstraint<"$rC = $rT">,
3623 RRForm<0b10111010110, (outs VECREG:$rT),
3624 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3625 "dfms\t$rT, $rA, $rB", DPrecFP,
3626 [(set (v2f64 VECREG:$rT),
3627 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3628 (v2f64 VECREG:$rC)))]>;
3630 // FNMS: - (a * b - c)
3631 // - (a * b) + c => c - (a * b)
3633 RRForm<0b01111010110, (outs R64FP:$rT),
3634 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3635 "dfnms\t$rT, $rA, $rB", DPrecFP,
3636 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3637 RegConstraint<"$rC = $rT">,
3640 def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
3641 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
3644 RRForm<0b01111010110, (outs VECREG:$rT),
3645 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3646 "dfnms\t$rT, $rA, $rB", DPrecFP,
3647 [(set (v2f64 VECREG:$rT),
3648 (fsub (v2f64 VECREG:$rC),
3649 (fmul (v2f64 VECREG:$rA),
3650 (v2f64 VECREG:$rB))))]>,
3651 RegConstraint<"$rC = $rT">,
3654 def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3655 (v2f64 VECREG:$rC))),
3656 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
3661 RRForm<0b11111010110, (outs R64FP:$rT),
3662 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3663 "dfnma\t$rT, $rA, $rB", DPrecFP,
3664 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
3665 RegConstraint<"$rC = $rT">,
3669 RRForm<0b11111010110, (outs VECREG:$rT),
3670 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3671 "dfnma\t$rT, $rA, $rB", DPrecFP,
3672 [(set (v2f64 VECREG:$rT),
3673 (fneg (fadd (v2f64 VECREG:$rC),
3674 (fmul (v2f64 VECREG:$rA),
3675 (v2f64 VECREG:$rB)))))]>,
3676 RegConstraint<"$rC = $rT">,
3679 //===----------------------------------------------------------------------==//
3680 // Floating point negation and absolute value
3681 //===----------------------------------------------------------------------==//
3683 def : Pat<(fneg (v4f32 VECREG:$rA)),
3684 (XORfnegvec (v4f32 VECREG:$rA),
3685 (v4f32 (ILHUv4i32 0x8000)))>;
3687 def : Pat<(fneg R32FP:$rA),
3688 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
3690 def : Pat<(fneg (v2f64 VECREG:$rA)),
3691 (XORfnegvec (v2f64 VECREG:$rA),
3692 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
3694 def : Pat<(fneg R64FP:$rA),
3695 (XORfneg64 R64FP:$rA,
3696 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
3698 // Floating point absolute value
3700 def : Pat<(fabs R32FP:$rA),
3701 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
3703 def : Pat<(fabs (v4f32 VECREG:$rA)),
3704 (ANDfabsvec (v4f32 VECREG:$rA),
3705 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3707 def : Pat<(fabs R64FP:$rA),
3708 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
3710 def : Pat<(fabs (v2f64 VECREG:$rA)),
3711 (ANDfabsvec (v2f64 VECREG:$rA),
3712 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3714 //===----------------------------------------------------------------------===//
3715 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
3716 // in the odd pipeline)
3717 //===----------------------------------------------------------------------===//
3719 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
3722 let Inst{0-10} = 0b10000000010;
3723 let Inst{11-17} = 0;
3724 let Inst{18-24} = 0;
3725 let Inst{25-31} = 0;
3728 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
3731 let Inst{0-10} = 0b10000000000;
3732 let Inst{11-17} = 0;
3733 let Inst{18-24} = 0;
3734 let Inst{25-31} = 0;
3737 //===----------------------------------------------------------------------===//
3738 // Bit conversions (type conversions between vector/packed types)
3739 // NOTE: Promotions are handled using the XS* instructions. Truncation
3741 //===----------------------------------------------------------------------===//
3742 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3743 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3744 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3745 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3746 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3748 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3749 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3750 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3751 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3752 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3754 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3755 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3756 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3757 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3758 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3760 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3761 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3762 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3763 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3764 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3766 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3767 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3768 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3769 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3770 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3772 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3773 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3774 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3775 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3776 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3778 def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3779 def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
3781 //===----------------------------------------------------------------------===//
3782 // Instruction patterns:
3783 //===----------------------------------------------------------------------===//
3785 // General 32-bit constants:
3786 def : Pat<(i32 imm:$imm),
3787 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3789 // Single precision float constants:
3790 def : Pat<(f32 fpimm:$imm),
3791 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3793 // General constant 32-bit vectors
3794 def : Pat<(v4i32 v4i32Imm:$imm),
3795 (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
3796 (LO16_vec v4i32Imm:$imm))>;
3799 def : Pat<(i8 imm:$imm),
3802 //===----------------------------------------------------------------------===//
3803 // Call instruction patterns:
3804 //===----------------------------------------------------------------------===//
3809 //===----------------------------------------------------------------------===//
3810 // Zero/Any/Sign extensions
3811 //===----------------------------------------------------------------------===//
3813 // zext 1->32: Zero extend i1 to i32
3814 def : Pat<(SPUextract_i1_zext R32C:$rSrc),
3815 (ANDIr32 R32C:$rSrc, 0x1)>;
3817 // sext 8->32: Sign extend bytes to words
3818 def : Pat<(sext_inreg R32C:$rSrc, i8),
3819 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
3821 def : Pat<(i32 (sext R8C:$rSrc)),
3822 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
3824 def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
3825 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
3826 (v4i32 VECREG:$rSrc))))>;
3828 // zext 8->16: Zero extend bytes to halfwords
3829 def : Pat<(i16 (zext R8C:$rSrc)),
3830 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
3832 // zext 8->32 from preferred slot in load/store
3833 def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
3834 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
3837 // zext 8->32: Zero extend bytes to words
3838 def : Pat<(i32 (zext R8C:$rSrc)),
3839 (ANDIi8i32 R8C:$rSrc, 0xff)>;
3841 // anyext 8->16: Extend 8->16 bits, irrespective of sign
3842 def : Pat<(i16 (anyext R8C:$rSrc)),
3843 (ORHIi8i16 R8C:$rSrc, 0)>;
3845 // anyext 8->32: Extend 8->32 bits, irrespective of sign
3846 def : Pat<(i32 (anyext R8C:$rSrc)),
3847 (ORIi8i32 R8C:$rSrc, 0)>;
3849 // zext 16->32: Zero extend halfwords to words
3850 def : Pat<(i32 (zext R16C:$rSrc)),
3851 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
3853 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
3854 (ANDIi16i32 R16C:$rSrc, 0xf)>;
3856 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
3857 (ANDIi16i32 R16C:$rSrc, 0xff)>;
3859 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
3860 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
3862 // anyext 16->32: Extend 16->32 bits, irrespective of sign
3863 def : Pat<(i32 (anyext R16C:$rSrc)),
3864 (ORIi16i32 R16C:$rSrc, 0)>;
3866 //===----------------------------------------------------------------------===//
3867 // Address generation: SPU, like PPC, has to split addresses into high and
3868 // low parts in order to load them into a register.
3869 //===----------------------------------------------------------------------===//
3871 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
3872 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
3873 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
3874 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
3876 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
3877 (SPUlo tglobaladdr:$in, 0)),
3878 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
3880 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
3881 (SPUlo texternalsym:$in, 0)),
3882 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
3884 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
3885 (SPUlo tjumptable:$in, 0)),
3886 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
3888 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
3889 (SPUlo tconstpool:$in, 0)),
3890 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
3892 def : Pat<(SPUindirect R32C:$sp, i32ImmSExt10:$imm),
3893 (AIr32 R32C:$sp, i32ImmSExt10:$imm)>;
3895 def : Pat<(SPUindirect R32C:$sp, imm:$imm),
3897 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm)))>;
3899 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
3900 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
3902 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
3903 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
3905 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
3906 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
3908 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
3909 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
3912 include "CellSDKIntrinsics.td"