1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start timm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end timm:$amt)]>;
33 //===----------------------------------------------------------------------===//
35 // NB: The ordering is actually important, since the instruction selection
36 // will try each of the instructions in sequence, i.e., the D-form first with
37 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
38 // finally the X-form with the register-register.
39 //===----------------------------------------------------------------------===//
41 let canFoldAsLoad = 1 in {
42 class LoadDFormVec<ValueType vectype>
43 : RI10Form<0b00101100, (outs VECREG:$rT), (ins dformaddr:$src),
46 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
49 class LoadDForm<RegisterClass rclass>
50 : RI10Form<0b00101100, (outs rclass:$rT), (ins dformaddr:$src),
53 [(set rclass:$rT, (load dform_addr:$src))]>
58 def v16i8: LoadDFormVec<v16i8>;
59 def v8i16: LoadDFormVec<v8i16>;
60 def v4i32: LoadDFormVec<v4i32>;
61 def v2i64: LoadDFormVec<v2i64>;
62 def v4f32: LoadDFormVec<v4f32>;
63 def v2f64: LoadDFormVec<v2f64>;
65 def v2i32: LoadDFormVec<v2i32>;
67 def r128: LoadDForm<GPRC>;
68 def r64: LoadDForm<R64C>;
69 def r32: LoadDForm<R32C>;
70 def f32: LoadDForm<R32FP>;
71 def f64: LoadDForm<R64FP>;
72 def r16: LoadDForm<R16C>;
73 def r8: LoadDForm<R8C>;
76 class LoadAFormVec<ValueType vectype>
77 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
80 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
83 class LoadAForm<RegisterClass rclass>
84 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
87 [(set rclass:$rT, (load aform_addr:$src))]>
92 def v16i8: LoadAFormVec<v16i8>;
93 def v8i16: LoadAFormVec<v8i16>;
94 def v4i32: LoadAFormVec<v4i32>;
95 def v2i64: LoadAFormVec<v2i64>;
96 def v4f32: LoadAFormVec<v4f32>;
97 def v2f64: LoadAFormVec<v2f64>;
99 def v2i32: LoadAFormVec<v2i32>;
101 def r128: LoadAForm<GPRC>;
102 def r64: LoadAForm<R64C>;
103 def r32: LoadAForm<R32C>;
104 def f32: LoadAForm<R32FP>;
105 def f64: LoadAForm<R64FP>;
106 def r16: LoadAForm<R16C>;
107 def r8: LoadAForm<R8C>;
110 class LoadXFormVec<ValueType vectype>
111 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
114 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
117 class LoadXForm<RegisterClass rclass>
118 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
121 [(set rclass:$rT, (load xform_addr:$src))]>
124 multiclass LoadXForms
126 def v16i8: LoadXFormVec<v16i8>;
127 def v8i16: LoadXFormVec<v8i16>;
128 def v4i32: LoadXFormVec<v4i32>;
129 def v2i64: LoadXFormVec<v2i64>;
130 def v4f32: LoadXFormVec<v4f32>;
131 def v2f64: LoadXFormVec<v2f64>;
133 def v2i32: LoadXFormVec<v2i32>;
135 def r128: LoadXForm<GPRC>;
136 def r64: LoadXForm<R64C>;
137 def r32: LoadXForm<R32C>;
138 def f32: LoadXForm<R32FP>;
139 def f64: LoadXForm<R64FP>;
140 def r16: LoadXForm<R16C>;
141 def r8: LoadXForm<R8C>;
144 defm LQA : LoadAForms;
145 defm LQD : LoadDForms;
146 defm LQX : LoadXForms;
148 /* Load quadword, PC relative: Not much use at this point in time.
149 Might be of use later for relocatable code. It's effectively the
150 same as LQA, but uses PC-relative addressing.
151 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
152 "lqr\t$rT, $disp", LoadStore,
153 [(set VECREG:$rT, (load iaddr:$disp))]>;
157 //===----------------------------------------------------------------------===//
159 //===----------------------------------------------------------------------===//
160 class StoreDFormVec<ValueType vectype>
161 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, dformaddr:$src),
164 [(store (vectype VECREG:$rT), dform_addr:$src)]>
167 class StoreDForm<RegisterClass rclass>
168 : RI10Form<0b00100100, (outs), (ins rclass:$rT, dformaddr:$src),
171 [(store rclass:$rT, dform_addr:$src)]>
174 multiclass StoreDForms
176 def v16i8: StoreDFormVec<v16i8>;
177 def v8i16: StoreDFormVec<v8i16>;
178 def v4i32: StoreDFormVec<v4i32>;
179 def v2i64: StoreDFormVec<v2i64>;
180 def v4f32: StoreDFormVec<v4f32>;
181 def v2f64: StoreDFormVec<v2f64>;
183 def v2i32: StoreDFormVec<v2i32>;
185 def r128: StoreDForm<GPRC>;
186 def r64: StoreDForm<R64C>;
187 def r32: StoreDForm<R32C>;
188 def f32: StoreDForm<R32FP>;
189 def f64: StoreDForm<R64FP>;
190 def r16: StoreDForm<R16C>;
191 def r8: StoreDForm<R8C>;
194 class StoreAFormVec<ValueType vectype>
195 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
198 [(store (vectype VECREG:$rT), aform_addr:$src)]>;
200 class StoreAForm<RegisterClass rclass>
201 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
204 [(store rclass:$rT, aform_addr:$src)]>;
206 multiclass StoreAForms
208 def v16i8: StoreAFormVec<v16i8>;
209 def v8i16: StoreAFormVec<v8i16>;
210 def v4i32: StoreAFormVec<v4i32>;
211 def v2i64: StoreAFormVec<v2i64>;
212 def v4f32: StoreAFormVec<v4f32>;
213 def v2f64: StoreAFormVec<v2f64>;
215 def v2i32: StoreAFormVec<v2i32>;
217 def r128: StoreAForm<GPRC>;
218 def r64: StoreAForm<R64C>;
219 def r32: StoreAForm<R32C>;
220 def f32: StoreAForm<R32FP>;
221 def f64: StoreAForm<R64FP>;
222 def r16: StoreAForm<R16C>;
223 def r8: StoreAForm<R8C>;
226 class StoreXFormVec<ValueType vectype>
227 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
230 [(store (vectype VECREG:$rT), xform_addr:$src)]>
233 class StoreXForm<RegisterClass rclass>
234 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
237 [(store rclass:$rT, xform_addr:$src)]>
240 multiclass StoreXForms
242 def v16i8: StoreXFormVec<v16i8>;
243 def v8i16: StoreXFormVec<v8i16>;
244 def v4i32: StoreXFormVec<v4i32>;
245 def v2i64: StoreXFormVec<v2i64>;
246 def v4f32: StoreXFormVec<v4f32>;
247 def v2f64: StoreXFormVec<v2f64>;
249 def v2i32: StoreXFormVec<v2i32>;
251 def r128: StoreXForm<GPRC>;
252 def r64: StoreXForm<R64C>;
253 def r32: StoreXForm<R32C>;
254 def f32: StoreXForm<R32FP>;
255 def f64: StoreXForm<R64FP>;
256 def r16: StoreXForm<R16C>;
257 def r8: StoreXForm<R8C>;
260 defm STQD : StoreDForms;
261 defm STQA : StoreAForms;
262 defm STQX : StoreXForms;
264 /* Store quadword, PC relative: Not much use at this point in time. Might
265 be useful for relocatable code.
266 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
267 "stqr\t$rT, $disp", LoadStore,
268 [(store VECREG:$rT, iaddr:$disp)]>;
271 //===----------------------------------------------------------------------===//
272 // Generate Controls for Insertion:
273 //===----------------------------------------------------------------------===//
275 def CBD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins shufaddr:$src),
276 "cbd\t$rT, $src", ShuffleOp,
277 [(set (v16i8 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
279 def CBX: RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
280 "cbx\t$rT, $src", ShuffleOp,
281 [(set (v16i8 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
283 def CHD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins shufaddr:$src),
284 "chd\t$rT, $src", ShuffleOp,
285 [(set (v8i16 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
287 def CHX: RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
288 "chx\t$rT, $src", ShuffleOp,
289 [(set (v8i16 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
291 def CWD: RI7Form<0b01101111100, (outs VECREG:$rT), (ins shufaddr:$src),
292 "cwd\t$rT, $src", ShuffleOp,
293 [(set (v4i32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
295 def CWX: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
296 "cwx\t$rT, $src", ShuffleOp,
297 [(set (v4i32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
299 def CWDf32: RI7Form<0b01101111100, (outs VECREG:$rT), (ins shufaddr:$src),
300 "cwd\t$rT, $src", ShuffleOp,
301 [(set (v4f32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
303 def CWXf32: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
304 "cwx\t$rT, $src", ShuffleOp,
305 [(set (v4f32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
307 def CDD: RI7Form<0b11101111100, (outs VECREG:$rT), (ins shufaddr:$src),
308 "cdd\t$rT, $src", ShuffleOp,
309 [(set (v2i64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
311 def CDX: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
312 "cdx\t$rT, $src", ShuffleOp,
313 [(set (v2i64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
315 def CDDf64: RI7Form<0b11101111100, (outs VECREG:$rT), (ins shufaddr:$src),
316 "cdd\t$rT, $src", ShuffleOp,
317 [(set (v2f64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
319 def CDXf64: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
320 "cdx\t$rT, $src", ShuffleOp,
321 [(set (v2f64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
323 //===----------------------------------------------------------------------===//
324 // Constant formation:
325 //===----------------------------------------------------------------------===//
328 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
329 "ilh\t$rT, $val", ImmLoad,
330 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
333 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
334 "ilh\t$rT, $val", ImmLoad,
335 [(set R16C:$rT, immSExt16:$val)]>;
337 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
338 // the right constant")
340 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
341 "ilh\t$rT, $val", ImmLoad,
342 [(set R8C:$rT, immSExt8:$val)]>;
344 // IL does sign extension!
346 class ILInst<dag OOL, dag IOL, list<dag> pattern>:
347 RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val",
350 class ILVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
351 ILInst<(outs VECREG:$rT), (ins immtype:$val),
352 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
354 class ILRegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
355 ILInst<(outs rclass:$rT), (ins immtype:$val),
356 [(set rclass:$rT, xform:$val)]>;
358 multiclass ImmediateLoad
360 def v2i64: ILVecInst<v2i64, s16imm_i64, v2i64SExt16Imm>;
361 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
363 // TODO: Need v2f64, v4f32
365 def r64: ILRegInst<R64C, s16imm_i64, immSExt16>;
366 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
367 def f32: ILRegInst<R32FP, s16imm_f32, fpimmSExt16>;
368 def f64: ILRegInst<R64FP, s16imm_f64, fpimmSExt16>;
371 defm IL : ImmediateLoad;
373 class ILHUInst<dag OOL, dag IOL, list<dag> pattern>:
374 RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val",
377 class ILHUVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
378 ILHUInst<(outs VECREG:$rT), (ins immtype:$val),
379 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
381 class ILHURegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
382 ILHUInst<(outs rclass:$rT), (ins immtype:$val),
383 [(set rclass:$rT, xform:$val)]>;
385 multiclass ImmLoadHalfwordUpper
387 def v2i64: ILHUVecInst<v2i64, u16imm_i64, immILHUvec_i64>;
388 def v4i32: ILHUVecInst<v4i32, u16imm_i32, immILHUvec>;
390 def r64: ILHURegInst<R64C, u16imm_i64, hi16>;
391 def r32: ILHURegInst<R32C, u16imm_i32, hi16>;
393 // Loads the high portion of an address
394 def hi: ILHURegInst<R32C, symbolHi, hi16>;
396 // Used in custom lowering constant SFP loads:
397 def f32: ILHURegInst<R32FP, f16imm, hi16_f32>;
400 defm ILHU : ImmLoadHalfwordUpper;
402 // Immediate load address (can also be used to load 18-bit unsigned constants,
403 // see the zext 16->32 pattern)
405 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
406 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
409 class ILAVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
410 ILAInst<(outs VECREG:$rT), (ins immtype:$val),
411 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
413 class ILARegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
414 ILAInst<(outs rclass:$rT), (ins immtype:$val),
415 [(set rclass:$rT, xform:$val)]>;
417 multiclass ImmLoadAddress
419 def v2i64: ILAVecInst<v2i64, u18imm, v2i64Uns18Imm>;
420 def v4i32: ILAVecInst<v4i32, u18imm, v4i32Uns18Imm>;
422 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
423 def r32: ILARegInst<R32C, u18imm, imm18>;
424 def f32: ILARegInst<R32FP, f18imm, fpimm18>;
425 def f64: ILARegInst<R64FP, f18imm_f64, fpimm18>;
427 def hi: ILARegInst<R32C, symbolHi, imm18>;
428 def lo: ILARegInst<R32C, symbolLo, imm18>;
430 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
434 defm ILA : ImmLoadAddress;
436 // Immediate OR, Halfword Lower: The "other" part of loading large constants
437 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
438 // Note that these are really two operand instructions, but they're encoded
439 // as three operands with the first two arguments tied-to each other.
441 class IOHLInst<dag OOL, dag IOL, list<dag> pattern>:
442 RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val",
444 RegConstraint<"$rS = $rT">,
447 class IOHLVecInst<ValueType vectype, Operand immtype /* , PatLeaf xform */>:
448 IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val),
451 class IOHLRegInst<RegisterClass rclass, Operand immtype /* , PatLeaf xform */>:
452 IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val),
455 multiclass ImmOrHalfwordLower
457 def v2i64: IOHLVecInst<v2i64, u16imm_i64>;
458 def v4i32: IOHLVecInst<v4i32, u16imm_i32>;
460 def r32: IOHLRegInst<R32C, i32imm>;
461 def f32: IOHLRegInst<R32FP, f32imm>;
463 def lo: IOHLRegInst<R32C, symbolLo>;
466 defm IOHL: ImmOrHalfwordLower;
468 // Form select mask for bytes using immediate, used in conjunction with the
471 class FSMBIVec<ValueType vectype>:
472 RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
475 [(set (vectype VECREG:$rT), (SPUselmask (i16 immU16:$val)))]>;
477 multiclass FormSelectMaskBytesImm
479 def v16i8: FSMBIVec<v16i8>;
480 def v8i16: FSMBIVec<v8i16>;
481 def v4i32: FSMBIVec<v4i32>;
482 def v2i64: FSMBIVec<v2i64>;
485 defm FSMBI : FormSelectMaskBytesImm;
487 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
488 class FSMBInst<dag OOL, dag IOL, list<dag> pattern>:
489 RRForm_1<0b01101101100, OOL, IOL, "fsmb\t$rT, $rA", SelectOp,
492 class FSMBRegInst<RegisterClass rclass, ValueType vectype>:
493 FSMBInst<(outs VECREG:$rT), (ins rclass:$rA),
494 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
496 class FSMBVecInst<ValueType vectype>:
497 FSMBInst<(outs VECREG:$rT), (ins VECREG:$rA),
498 [(set (vectype VECREG:$rT),
499 (SPUselmask (vectype VECREG:$rA)))]>;
501 multiclass FormSelectMaskBits {
502 def v16i8_r16: FSMBRegInst<R16C, v16i8>;
503 def v16i8: FSMBVecInst<v16i8>;
506 defm FSMB: FormSelectMaskBits;
508 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
509 // only 8-bits wide (even though it's input as 16-bits here)
511 class FSMHInst<dag OOL, dag IOL, list<dag> pattern>:
512 RRForm_1<0b10101101100, OOL, IOL, "fsmh\t$rT, $rA", SelectOp,
515 class FSMHRegInst<RegisterClass rclass, ValueType vectype>:
516 FSMHInst<(outs VECREG:$rT), (ins rclass:$rA),
517 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
519 class FSMHVecInst<ValueType vectype>:
520 FSMHInst<(outs VECREG:$rT), (ins VECREG:$rA),
521 [(set (vectype VECREG:$rT),
522 (SPUselmask (vectype VECREG:$rA)))]>;
524 multiclass FormSelectMaskHalfword {
525 def v8i16_r16: FSMHRegInst<R16C, v8i16>;
526 def v8i16: FSMHVecInst<v8i16>;
529 defm FSMH: FormSelectMaskHalfword;
531 // fsm: Form select mask for words. Like the other fsm* instructions,
532 // only the lower 4 bits of $rA are significant.
534 class FSMInst<dag OOL, dag IOL, list<dag> pattern>:
535 RRForm_1<0b00101101100, OOL, IOL, "fsm\t$rT, $rA", SelectOp,
538 class FSMRegInst<ValueType vectype, RegisterClass rclass>:
539 FSMInst<(outs VECREG:$rT), (ins rclass:$rA),
540 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
542 class FSMVecInst<ValueType vectype>:
543 FSMInst<(outs VECREG:$rT), (ins VECREG:$rA),
544 [(set (vectype VECREG:$rT), (SPUselmask (vectype VECREG:$rA)))]>;
546 multiclass FormSelectMaskWord {
547 def v4i32: FSMVecInst<v4i32>;
549 def r32 : FSMRegInst<v4i32, R32C>;
550 def r16 : FSMRegInst<v4i32, R16C>;
553 defm FSM : FormSelectMaskWord;
555 // Special case when used for i64 math operations
556 multiclass FormSelectMaskWord64 {
557 def r32 : FSMRegInst<v2i64, R32C>;
558 def r16 : FSMRegInst<v2i64, R16C>;
561 defm FSM64 : FormSelectMaskWord64;
563 //===----------------------------------------------------------------------===//
564 // Integer and Logical Operations:
565 //===----------------------------------------------------------------------===//
568 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
569 "ah\t$rT, $rA, $rB", IntegerOp,
570 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
572 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
573 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
576 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
577 "ah\t$rT, $rA, $rB", IntegerOp,
578 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
581 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
582 "ahi\t$rT, $rA, $val", IntegerOp,
583 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
584 v8i16SExt10Imm:$val))]>;
587 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
588 "ahi\t$rT, $rA, $val", IntegerOp,
589 [(set R16C:$rT, (add R16C:$rA, i16ImmSExt10:$val))]>;
591 // v4i32, i32 add instruction:
593 class AInst<dag OOL, dag IOL, list<dag> pattern>:
594 RRForm<0b00000011000, OOL, IOL,
595 "a\t$rT, $rA, $rB", IntegerOp,
598 class AVecInst<ValueType vectype>:
599 AInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
600 [(set (vectype VECREG:$rT), (add (vectype VECREG:$rA),
601 (vectype VECREG:$rB)))]>;
603 class ARegInst<RegisterClass rclass>:
604 AInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
605 [(set rclass:$rT, (add rclass:$rA, rclass:$rB))]>;
607 multiclass AddInstruction {
608 def v4i32: AVecInst<v4i32>;
609 def v16i8: AVecInst<v16i8>;
611 def r32: ARegInst<R32C>;
614 defm A : AddInstruction;
616 class AIInst<dag OOL, dag IOL, list<dag> pattern>:
617 RI10Form<0b00111000, OOL, IOL,
618 "ai\t$rT, $rA, $val", IntegerOp,
621 class AIVecInst<ValueType vectype, PatLeaf immpred>:
622 AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
623 [(set (vectype VECREG:$rT), (add (vectype VECREG:$rA), immpred:$val))]>;
625 class AIFPVecInst<ValueType vectype, PatLeaf immpred>:
626 AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
629 class AIRegInst<RegisterClass rclass, PatLeaf immpred>:
630 AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val),
631 [(set rclass:$rT, (add rclass:$rA, immpred:$val))]>;
633 // This is used to add epsilons to floating point numbers in the f32 fdiv code:
634 class AIFPInst<RegisterClass rclass, PatLeaf immpred>:
635 AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val),
638 multiclass AddImmediate {
639 def v4i32: AIVecInst<v4i32, v4i32SExt10Imm>;
641 def r32: AIRegInst<R32C, i32ImmSExt10>;
643 def v4f32: AIFPVecInst<v4f32, v4i32SExt10Imm>;
644 def f32: AIFPInst<R32FP, i32ImmSExt10>;
647 defm AI : AddImmediate;
650 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
651 "sfh\t$rT, $rA, $rB", IntegerOp,
652 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
653 (v8i16 VECREG:$rB)))]>;
656 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
657 "sfh\t$rT, $rA, $rB", IntegerOp,
658 [(set R16C:$rT, (sub R16C:$rB, R16C:$rA))]>;
661 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
662 "sfhi\t$rT, $rA, $val", IntegerOp,
663 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
664 (v8i16 VECREG:$rA)))]>;
666 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
667 "sfhi\t$rT, $rA, $val", IntegerOp,
668 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
670 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
671 (ins VECREG:$rA, VECREG:$rB),
672 "sf\t$rT, $rA, $rB", IntegerOp,
673 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rB), (v4i32 VECREG:$rA)))]>;
675 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
676 "sf\t$rT, $rA, $rB", IntegerOp,
677 [(set R32C:$rT, (sub R32C:$rB, R32C:$rA))]>;
680 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
681 "sfi\t$rT, $rA, $val", IntegerOp,
682 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
683 (v4i32 VECREG:$rA)))]>;
685 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
686 (ins R32C:$rA, s10imm_i32:$val),
687 "sfi\t$rT, $rA, $val", IntegerOp,
688 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
690 // ADDX: only available in vector form, doesn't match a pattern.
691 class ADDXInst<dag OOL, dag IOL, list<dag> pattern>:
692 RRForm<0b00000010110, OOL, IOL,
693 "addx\t$rT, $rA, $rB",
696 class ADDXVecInst<ValueType vectype>:
697 ADDXInst<(outs VECREG:$rT),
698 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
700 RegConstraint<"$rCarry = $rT">,
703 class ADDXRegInst<RegisterClass rclass>:
704 ADDXInst<(outs rclass:$rT),
705 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
707 RegConstraint<"$rCarry = $rT">,
710 multiclass AddExtended {
711 def v2i64 : ADDXVecInst<v2i64>;
712 def v4i32 : ADDXVecInst<v4i32>;
713 def r64 : ADDXRegInst<R64C>;
714 def r32 : ADDXRegInst<R32C>;
717 defm ADDX : AddExtended;
719 // CG: Generate carry for add
720 class CGInst<dag OOL, dag IOL, list<dag> pattern>:
721 RRForm<0b01000011000, OOL, IOL,
725 class CGVecInst<ValueType vectype>:
726 CGInst<(outs VECREG:$rT),
727 (ins VECREG:$rA, VECREG:$rB),
730 class CGRegInst<RegisterClass rclass>:
731 CGInst<(outs rclass:$rT),
732 (ins rclass:$rA, rclass:$rB),
735 multiclass CarryGenerate {
736 def v2i64 : CGVecInst<v2i64>;
737 def v4i32 : CGVecInst<v4i32>;
738 def r64 : CGRegInst<R64C>;
739 def r32 : CGRegInst<R32C>;
742 defm CG : CarryGenerate;
744 // SFX: Subract from, extended. This is used in conjunction with BG to subtract
745 // with carry (borrow, in this case)
746 class SFXInst<dag OOL, dag IOL, list<dag> pattern>:
747 RRForm<0b10000010110, OOL, IOL,
748 "sfx\t$rT, $rA, $rB",
751 class SFXVecInst<ValueType vectype>:
752 SFXInst<(outs VECREG:$rT),
753 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
755 RegConstraint<"$rCarry = $rT">,
758 class SFXRegInst<RegisterClass rclass>:
759 SFXInst<(outs rclass:$rT),
760 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
762 RegConstraint<"$rCarry = $rT">,
765 multiclass SubtractExtended {
766 def v2i64 : SFXVecInst<v2i64>;
767 def v4i32 : SFXVecInst<v4i32>;
768 def r64 : SFXRegInst<R64C>;
769 def r32 : SFXRegInst<R32C>;
772 defm SFX : SubtractExtended;
774 // BG: only available in vector form, doesn't match a pattern.
775 class BGInst<dag OOL, dag IOL, list<dag> pattern>:
776 RRForm<0b01000010000, OOL, IOL,
780 class BGVecInst<ValueType vectype>:
781 BGInst<(outs VECREG:$rT),
782 (ins VECREG:$rA, VECREG:$rB),
785 class BGRegInst<RegisterClass rclass>:
786 BGInst<(outs rclass:$rT),
787 (ins rclass:$rA, rclass:$rB),
790 multiclass BorrowGenerate {
791 def v4i32 : BGVecInst<v4i32>;
792 def v2i64 : BGVecInst<v2i64>;
793 def r64 : BGRegInst<R64C>;
794 def r32 : BGRegInst<R32C>;
797 defm BG : BorrowGenerate;
799 // BGX: Borrow generate, extended.
801 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
803 "bgx\t$rT, $rA, $rB", IntegerOp,
805 RegConstraint<"$rCarry = $rT">,
808 // Halfword multiply variants:
809 // N.B: These can be used to build up larger quantities (16x16 -> 32)
812 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
813 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
817 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
818 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
819 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
821 // Unsigned 16-bit multiply:
823 class MPYUInst<dag OOL, dag IOL, list<dag> pattern>:
824 RRForm<0b00110011110, OOL, IOL,
825 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
829 MPYUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
833 MPYUInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
834 [(set R32C:$rT, (mul (zext R16C:$rA), (zext R16C:$rB)))]>;
837 MPYUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
840 // mpyi: multiply 16 x s10imm -> 32 result.
842 class MPYIInst<dag OOL, dag IOL, list<dag> pattern>:
843 RI10Form<0b00101110, OOL, IOL,
844 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
848 MPYIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
849 [(set (v8i16 VECREG:$rT),
850 (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
853 MPYIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
854 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
856 // mpyui: same issues as other multiplies, plus, this doesn't match a
857 // pattern... but may be used during target DAG selection or lowering
859 class MPYUIInst<dag OOL, dag IOL, list<dag> pattern>:
860 RI10Form<0b10101110, OOL, IOL,
861 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
865 MPYUIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
869 MPYUIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
872 // mpya: 16 x 16 + 16 -> 32 bit result
873 class MPYAInst<dag OOL, dag IOL, list<dag> pattern>:
874 RRRForm<0b0011, OOL, IOL,
875 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
879 MPYAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
880 [(set (v4i32 VECREG:$rT),
881 (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
882 (v8i16 VECREG:$rB)))),
883 (v4i32 VECREG:$rC)))]>;
886 MPYAInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
887 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
891 MPYAInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
892 [(set R32C:$rT, (add (mul (sext R16C:$rA), (sext R16C:$rB)),
895 def MPYAr32_sextinreg:
896 MPYAInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
897 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
898 (sext_inreg R32C:$rB, i16)),
901 // mpyh: multiply high, used to synthesize 32-bit multiplies
902 class MPYHInst<dag OOL, dag IOL, list<dag> pattern>:
903 RRForm<0b10100011110, OOL, IOL,
904 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
908 MPYHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
912 MPYHInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
915 // mpys: multiply high and shift right (returns the top half of
916 // a 16-bit multiply, sign extended to 32 bits.)
918 class MPYSInst<dag OOL, dag IOL>:
919 RRForm<0b11100011110, OOL, IOL,
920 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
924 MPYSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
927 MPYSInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB)>;
929 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
930 // the top 16 bits of the $rA, $rB)
932 class MPYHHInst<dag OOL, dag IOL>:
933 RRForm<0b01100011110, OOL, IOL,
934 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
938 MPYHHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
941 MPYHHInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>;
943 // mpyhha: Multiply high-high, add to $rT:
945 class MPYHHAInst<dag OOL, dag IOL>:
946 RRForm<0b01100010110, OOL, IOL,
947 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
951 MPYHHAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
954 MPYHHAInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>;
956 // mpyhhu: Multiply high-high, unsigned, e.g.:
958 // +-------+-------+ +-------+-------+ +---------+
959 // | a0 . a1 | x | b0 . b1 | = | a0 x b0 |
960 // +-------+-------+ +-------+-------+ +---------+
962 // where a0, b0 are the upper 16 bits of the 32-bit word
964 class MPYHHUInst<dag OOL, dag IOL>:
965 RRForm<0b01110011110, OOL, IOL,
966 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
970 MPYHHUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
973 MPYHHUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>;
975 // mpyhhau: Multiply high-high, unsigned
977 class MPYHHAUInst<dag OOL, dag IOL>:
978 RRForm<0b01110010110, OOL, IOL,
979 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
983 MPYHHAUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
986 MPYHHAUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>;
988 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
989 // clz: Count leading zeroes
990 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
991 class CLZInst<dag OOL, dag IOL, list<dag> pattern>:
992 RRForm_1<0b10100101010, OOL, IOL, "clz\t$rT, $rA",
995 class CLZRegInst<RegisterClass rclass>:
996 CLZInst<(outs rclass:$rT), (ins rclass:$rA),
997 [(set rclass:$rT, (ctlz rclass:$rA))]>;
999 class CLZVecInst<ValueType vectype>:
1000 CLZInst<(outs VECREG:$rT), (ins VECREG:$rA),
1001 [(set (vectype VECREG:$rT), (ctlz (vectype VECREG:$rA)))]>;
1003 multiclass CountLeadingZeroes {
1004 def v4i32 : CLZVecInst<v4i32>;
1005 def r32 : CLZRegInst<R32C>;
1008 defm CLZ : CountLeadingZeroes;
1010 // cntb: Count ones in bytes (aka "population count")
1012 // NOTE: This instruction is really a vector instruction, but the custom
1013 // lowering code uses it in unorthodox ways to support CTPOP for other
1017 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
1018 "cntb\t$rT, $rA", IntegerOp,
1019 [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>;
1022 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
1023 "cntb\t$rT, $rA", IntegerOp,
1024 [(set (v8i16 VECREG:$rT), (SPUcntb (v8i16 VECREG:$rA)))]>;
1027 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
1028 "cntb\t$rT, $rA", IntegerOp,
1029 [(set (v4i32 VECREG:$rT), (SPUcntb (v4i32 VECREG:$rA)))]>;
1031 // gbb: Gather the low order bits from each byte in $rA into a single 16-bit
1032 // quantity stored into $rT's slot 0, upper 16 bits are zeroed, as are
1035 // Note: This instruction "pairs" with the fsmb instruction for all of the
1036 // various types defined here.
1038 // Note 2: The "VecInst" and "RegInst" forms refer to the result being either
1039 // a vector or register.
1041 class GBBInst<dag OOL, dag IOL, list<dag> pattern>:
1042 RRForm_1<0b01001101100, OOL, IOL, "gbb\t$rT, $rA", GatherOp, pattern>;
1044 class GBBRegInst<RegisterClass rclass, ValueType vectype>:
1045 GBBInst<(outs rclass:$rT), (ins VECREG:$rA),
1046 [/* no pattern */]>;
1048 class GBBVecInst<ValueType vectype>:
1049 GBBInst<(outs VECREG:$rT), (ins VECREG:$rA),
1050 [/* no pattern */]>;
1052 multiclass GatherBitsFromBytes {
1053 def v16i8_r32: GBBRegInst<R32C, v16i8>;
1054 def v16i8_r16: GBBRegInst<R16C, v16i8>;
1055 def v16i8: GBBVecInst<v16i8>;
1058 defm GBB: GatherBitsFromBytes;
1060 // gbh: Gather all low order bits from each halfword in $rA into a single
1061 // 8-bit quantity stored in $rT's slot 0, with the upper bits of $rT set to 0
1062 // and slots 1-3 also set to 0.
1064 // See notes for GBBInst, above.
1066 class GBHInst<dag OOL, dag IOL, list<dag> pattern>:
1067 RRForm_1<0b10001101100, OOL, IOL, "gbh\t$rT, $rA", GatherOp,
1070 class GBHRegInst<RegisterClass rclass, ValueType vectype>:
1071 GBHInst<(outs rclass:$rT), (ins VECREG:$rA),
1072 [/* no pattern */]>;
1074 class GBHVecInst<ValueType vectype>:
1075 GBHInst<(outs VECREG:$rT), (ins VECREG:$rA),
1076 [/* no pattern */]>;
1078 multiclass GatherBitsHalfword {
1079 def v8i16_r32: GBHRegInst<R32C, v8i16>;
1080 def v8i16_r16: GBHRegInst<R16C, v8i16>;
1081 def v8i16: GBHVecInst<v8i16>;
1084 defm GBH: GatherBitsHalfword;
1086 // gb: Gather all low order bits from each word in $rA into a single
1087 // 4-bit quantity stored in $rT's slot 0, upper bits in $rT set to 0,
1088 // as well as slots 1-3.
1090 // See notes for gbb, above.
1092 class GBInst<dag OOL, dag IOL, list<dag> pattern>:
1093 RRForm_1<0b00001101100, OOL, IOL, "gb\t$rT, $rA", GatherOp,
1096 class GBRegInst<RegisterClass rclass, ValueType vectype>:
1097 GBInst<(outs rclass:$rT), (ins VECREG:$rA),
1098 [/* no pattern */]>;
1100 class GBVecInst<ValueType vectype>:
1101 GBInst<(outs VECREG:$rT), (ins VECREG:$rA),
1102 [/* no pattern */]>;
1104 multiclass GatherBitsWord {
1105 def v4i32_r32: GBRegInst<R32C, v4i32>;
1106 def v4i32_r16: GBRegInst<R16C, v4i32>;
1107 def v4i32: GBVecInst<v4i32>;
1110 defm GB: GatherBitsWord;
1112 // avgb: average bytes
1114 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1115 "avgb\t$rT, $rA, $rB", ByteOp,
1118 // absdb: absolute difference of bytes
1120 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1121 "absdb\t$rT, $rA, $rB", ByteOp,
1124 // sumb: sum bytes into halfwords
1126 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1127 "sumb\t$rT, $rA, $rB", ByteOp,
1130 // Sign extension operations:
1131 class XSBHInst<dag OOL, dag IOL, list<dag> pattern>:
1132 RRForm_1<0b01101101010, OOL, IOL,
1133 "xsbh\t$rDst, $rSrc",
1134 IntegerOp, pattern>;
1136 class XSBHInRegInst<RegisterClass rclass, list<dag> pattern>:
1137 XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc),
1140 multiclass ExtendByteHalfword {
1141 def v16i8: XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
1143 /*(set (v8i16 VECREG:$rDst), (sext (v8i16 VECREG:$rSrc)))*/]>;
1144 def r8: XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc),
1145 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
1146 def r16: XSBHInRegInst<R16C,
1147 [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>;
1149 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
1150 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
1151 // pattern below). Intentionally doesn't match a pattern because we want the
1152 // sext 8->32 pattern to do the work for us, namely because we need the extra
1154 def r32: XSBHInRegInst<R32C, [/* no pattern */]>;
1156 // Same as the 32-bit version, but for i64
1157 def r64: XSBHInRegInst<R64C, [/* no pattern */]>;
1160 defm XSBH : ExtendByteHalfword;
1162 // Sign extend halfwords to words:
1164 class XSHWInst<dag OOL, dag IOL, list<dag> pattern>:
1165 RRForm_1<0b01101101010, OOL, IOL, "xshw\t$rDest, $rSrc",
1166 IntegerOp, pattern>;
1168 class XSHWVecInst<ValueType in_vectype, ValueType out_vectype>:
1169 XSHWInst<(outs VECREG:$rDest), (ins VECREG:$rSrc),
1170 [(set (out_vectype VECREG:$rDest),
1171 (sext (in_vectype VECREG:$rSrc)))]>;
1173 class XSHWInRegInst<RegisterClass rclass, list<dag> pattern>:
1174 XSHWInst<(outs rclass:$rDest), (ins rclass:$rSrc),
1177 class XSHWRegInst<RegisterClass rclass>:
1178 XSHWInst<(outs rclass:$rDest), (ins R16C:$rSrc),
1179 [(set rclass:$rDest, (sext R16C:$rSrc))]>;
1181 multiclass ExtendHalfwordWord {
1182 def v4i32: XSHWVecInst<v4i32, v8i16>;
1184 def r16: XSHWRegInst<R32C>;
1186 def r32: XSHWInRegInst<R32C,
1187 [(set R32C:$rDest, (sext_inreg R32C:$rSrc, i16))]>;
1188 def r64: XSHWInRegInst<R64C, [/* no pattern */]>;
1191 defm XSHW : ExtendHalfwordWord;
1193 // Sign-extend words to doublewords (32->64 bits)
1195 class XSWDInst<dag OOL, dag IOL, list<dag> pattern>:
1196 RRForm_1<0b01100101010, OOL, IOL, "xswd\t$rDst, $rSrc",
1197 IntegerOp, pattern>;
1199 class XSWDVecInst<ValueType in_vectype, ValueType out_vectype>:
1200 XSWDInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
1201 [/*(set (out_vectype VECREG:$rDst),
1202 (sext (out_vectype VECREG:$rSrc)))*/]>;
1204 class XSWDRegInst<RegisterClass in_rclass, RegisterClass out_rclass>:
1205 XSWDInst<(outs out_rclass:$rDst), (ins in_rclass:$rSrc),
1206 [(set out_rclass:$rDst, (sext in_rclass:$rSrc))]>;
1208 multiclass ExtendWordToDoubleWord {
1209 def v2i64: XSWDVecInst<v4i32, v2i64>;
1210 def r64: XSWDRegInst<R32C, R64C>;
1212 def r64_inreg: XSWDInst<(outs R64C:$rDst), (ins R64C:$rSrc),
1213 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
1216 defm XSWD : ExtendWordToDoubleWord;
1220 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
1221 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
1222 IntegerOp, pattern>;
1224 class ANDVecInst<ValueType vectype>:
1225 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1226 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1227 (vectype VECREG:$rB)))]>;
1229 class ANDRegInst<RegisterClass rclass>:
1230 ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1231 [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>;
1233 multiclass BitwiseAnd
1235 def v16i8: ANDVecInst<v16i8>;
1236 def v8i16: ANDVecInst<v8i16>;
1237 def v4i32: ANDVecInst<v4i32>;
1238 def v2i64: ANDVecInst<v2i64>;
1240 def r128: ANDRegInst<GPRC>;
1241 def r64: ANDRegInst<R64C>;
1242 def r32: ANDRegInst<R32C>;
1243 def r16: ANDRegInst<R16C>;
1244 def r8: ANDRegInst<R8C>;
1246 //===---------------------------------------------
1247 // Special instructions to perform the fabs instruction
1248 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1249 [/* Intentionally does not match a pattern */]>;
1251 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB),
1252 [/* Intentionally does not match a pattern */]>;
1254 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1255 [/* Intentionally does not match a pattern */]>;
1257 //===---------------------------------------------
1259 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
1260 // quantities -- see 16->32 zext pattern.
1262 // This pattern is somewhat artificial, since it might match some
1263 // compiler generated pattern but it is unlikely to do so.
1265 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
1266 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
1269 defm AND : BitwiseAnd;
1272 def vnot_cell_conv : PatFrag<(ops node:$in),
1273 (xor node:$in, (bitconvert (v4i32 immAllOnesV)))>;
1275 // N.B.: vnot_cell_conv is one of those special target selection pattern
1277 // in which we expect there to be a bit_convert on the constant. Bear in mind
1278 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
1279 // constant -1 vector.)
1281 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
1282 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
1283 IntegerOp, pattern>;
1285 class ANDCVecInst<ValueType vectype, PatFrag vnot_frag = vnot>:
1286 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1287 [(set (vectype VECREG:$rT),
1288 (and (vectype VECREG:$rA),
1289 (vnot_frag (vectype VECREG:$rB))))]>;
1291 class ANDCRegInst<RegisterClass rclass>:
1292 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1293 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
1295 multiclass AndComplement
1297 def v16i8: ANDCVecInst<v16i8>;
1298 def v8i16: ANDCVecInst<v8i16>;
1299 def v4i32: ANDCVecInst<v4i32>;
1300 def v2i64: ANDCVecInst<v2i64>;
1302 def r128: ANDCRegInst<GPRC>;
1303 def r64: ANDCRegInst<R64C>;
1304 def r32: ANDCRegInst<R32C>;
1305 def r16: ANDCRegInst<R16C>;
1306 def r8: ANDCRegInst<R8C>;
1308 // Sometimes, the xor pattern has a bitcast constant:
1309 def v16i8_conv: ANDCVecInst<v16i8, vnot_cell_conv>;
1312 defm ANDC : AndComplement;
1314 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1315 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1318 multiclass AndByteImm
1320 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1321 [(set (v16i8 VECREG:$rT),
1322 (and (v16i8 VECREG:$rA),
1323 (v16i8 v16i8U8Imm:$val)))]>;
1325 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1326 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1329 defm ANDBI : AndByteImm;
1331 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1332 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1335 multiclass AndHalfwordImm
1337 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1338 [(set (v8i16 VECREG:$rT),
1339 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1341 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1342 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1344 // Zero-extend i8 to i16:
1345 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1346 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1349 defm ANDHI : AndHalfwordImm;
1351 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1352 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1353 IntegerOp, pattern>;
1355 multiclass AndWordImm
1357 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1358 [(set (v4i32 VECREG:$rT),
1359 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1361 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1362 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1364 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1366 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1368 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1370 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1371 // zext 16->32 pattern below.
1373 // Note that this pattern is somewhat artificial, since it might match
1374 // something the compiler generates but is unlikely to occur in practice.
1375 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1377 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1380 defm ANDI : AndWordImm;
1382 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1383 // Bitwise OR group:
1384 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1386 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1387 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1388 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1389 IntegerOp, pattern>;
1391 class ORVecInst<ValueType vectype>:
1392 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1393 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1394 (vectype VECREG:$rB)))]>;
1396 class ORRegInst<RegisterClass rclass>:
1397 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1398 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1400 // ORCvtForm: OR conversion form
1402 // This is used to "convert" the preferred slot to its vector equivalent, as
1403 // well as convert a vector back to its preferred slot.
1405 // These are effectively no-ops, but need to exist for proper type conversion
1406 // and type coercion.
1408 class ORCvtForm<dag OOL, dag IOL, list<dag> pattern = [/* no pattern */]>
1409 : SPUInstr<OOL, IOL, "or\t$rT, $rA, $rA", IntegerOp> {
1413 let Pattern = pattern;
1415 let Inst{0-10} = 0b10000010000;
1416 let Inst{11-17} = RA;
1417 let Inst{18-24} = RA;
1418 let Inst{25-31} = RT;
1421 class ORPromoteScalar<RegisterClass rclass>:
1422 ORCvtForm<(outs VECREG:$rT), (ins rclass:$rA)>;
1424 class ORExtractElt<RegisterClass rclass>:
1425 ORCvtForm<(outs rclass:$rT), (ins VECREG:$rA)>;
1427 /* class ORCvtRegGPRC<RegisterClass rclass>:
1428 ORCvtForm<(outs GPRC:$rT), (ins rclass:$rA)>; */
1430 /* class ORCvtGPRCReg<RegisterClass rclass>:
1431 ORCvtForm<(outs rclass:$rT), (ins GPRC:$rA)>; */
1433 class ORCvtFormR32Reg<RegisterClass rclass, list<dag> pattern = [ ]>:
1434 ORCvtForm<(outs rclass:$rT), (ins R32C:$rA), pattern>;
1436 class ORCvtFormRegR32<RegisterClass rclass, list<dag> pattern = [ ]>:
1437 ORCvtForm<(outs R32C:$rT), (ins rclass:$rA), pattern>;
1439 class ORCvtFormR64Reg<RegisterClass rclass, list<dag> pattern = [ ]>:
1440 ORCvtForm<(outs rclass:$rT), (ins R64C:$rA), pattern>;
1442 class ORCvtFormRegR64<RegisterClass rclass, list<dag> pattern = [ ]>:
1443 ORCvtForm<(outs R64C:$rT), (ins rclass:$rA), pattern>;
1446 ORCvtForm<(outs VECREG:$rT), (ins GPRC:$rA)>;
1449 ORCvtForm<(outs GPRC:$rT), (ins VECREG:$rA)>;
1451 multiclass BitwiseOr
1453 def v16i8: ORVecInst<v16i8>;
1454 def v8i16: ORVecInst<v8i16>;
1455 def v4i32: ORVecInst<v4i32>;
1456 def v2i64: ORVecInst<v2i64>;
1458 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1459 [(set (v4f32 VECREG:$rT),
1460 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1461 (v4i32 VECREG:$rB)))))]>;
1463 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1464 [(set (v2f64 VECREG:$rT),
1465 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1466 (v2i64 VECREG:$rB)))))]>;
1468 def r128: ORRegInst<GPRC>;
1469 def r64: ORRegInst<R64C>;
1470 def r32: ORRegInst<R32C>;
1471 def r16: ORRegInst<R16C>;
1472 def r8: ORRegInst<R8C>;
1474 // OR instructions used to copy f32 and f64 registers.
1475 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1476 [/* no pattern */]>;
1478 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1479 [/* no pattern */]>;
1481 // scalar->vector promotion, prefslot2vec:
1482 def v16i8_i8: ORPromoteScalar<R8C>;
1483 def v8i16_i16: ORPromoteScalar<R16C>;
1484 def v4i32_i32: ORPromoteScalar<R32C>;
1485 def v2i64_i64: ORPromoteScalar<R64C>;
1486 def v4f32_f32: ORPromoteScalar<R32FP>;
1487 def v2f64_f64: ORPromoteScalar<R64FP>;
1489 // vector->scalar demotion, vec2prefslot:
1490 def i8_v16i8: ORExtractElt<R8C>;
1491 def i16_v8i16: ORExtractElt<R16C>;
1492 def i32_v4i32: ORExtractElt<R32C>;
1493 def i64_v2i64: ORExtractElt<R64C>;
1494 def f32_v4f32: ORExtractElt<R32FP>;
1495 def f64_v2f64: ORExtractElt<R64FP>;
1497 // Conversion from vector to GPRC
1498 def i128_vec: ORCvtVecGPRC;
1500 // Conversion from GPRC to vector
1501 def vec_i128: ORCvtGPRCVec;
1504 // Conversion from register to GPRC
1505 def i128_r64: ORCvtRegGPRC<R64C>;
1506 def i128_f64: ORCvtRegGPRC<R64FP>;
1507 def i128_r32: ORCvtRegGPRC<R32C>;
1508 def i128_f32: ORCvtRegGPRC<R32FP>;
1509 def i128_r16: ORCvtRegGPRC<R16C>;
1510 def i128_r8: ORCvtRegGPRC<R8C>;
1512 // Conversion from GPRC to register
1513 def r64_i128: ORCvtGPRCReg<R64C>;
1514 def f64_i128: ORCvtGPRCReg<R64FP>;
1515 def r32_i128: ORCvtGPRCReg<R32C>;
1516 def f32_i128: ORCvtGPRCReg<R32FP>;
1517 def r16_i128: ORCvtGPRCReg<R16C>;
1518 def r8_i128: ORCvtGPRCReg<R8C>;
1521 // Conversion from register to R32C:
1522 def r32_r16: ORCvtFormRegR32<R16C>;
1523 def r32_r8: ORCvtFormRegR32<R8C>;
1525 // Conversion from R32C to register
1526 def r32_r16: ORCvtFormR32Reg<R16C>;
1527 def r32_r8: ORCvtFormR32Reg<R8C>;
1530 // Conversion from R64C to register:
1531 def r32_r64: ORCvtFormR64Reg<R32C>;
1532 // def r16_r64: ORCvtFormR64Reg<R16C>;
1533 // def r8_r64: ORCvtFormR64Reg<R8C>;
1535 // Conversion to R64C from register:
1536 def r64_r32: ORCvtFormRegR64<R32C>;
1537 // def r64_r16: ORCvtFormRegR64<R16C>;
1538 // def r64_r8: ORCvtFormRegR64<R8C>;
1540 // bitconvert patterns:
1541 def r32_f32: ORCvtFormR32Reg<R32FP,
1542 [(set R32FP:$rT, (bitconvert R32C:$rA))]>;
1543 def f32_r32: ORCvtFormRegR32<R32FP,
1544 [(set R32C:$rT, (bitconvert R32FP:$rA))]>;
1546 def r64_f64: ORCvtFormR64Reg<R64FP,
1547 [(set R64FP:$rT, (bitconvert R64C:$rA))]>;
1548 def f64_r64: ORCvtFormRegR64<R64FP,
1549 [(set R64C:$rT, (bitconvert R64FP:$rA))]>;
1552 defm OR : BitwiseOr;
1554 // scalar->vector promotion patterns (preferred slot to vector):
1555 def : Pat<(v16i8 (SPUprefslot2vec R8C:$rA)),
1556 (ORv16i8_i8 R8C:$rA)>;
1558 def : Pat<(v8i16 (SPUprefslot2vec R16C:$rA)),
1559 (ORv8i16_i16 R16C:$rA)>;
1561 def : Pat<(v4i32 (SPUprefslot2vec R32C:$rA)),
1562 (ORv4i32_i32 R32C:$rA)>;
1564 def : Pat<(v2i64 (SPUprefslot2vec R64C:$rA)),
1565 (ORv2i64_i64 R64C:$rA)>;
1567 def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)),
1568 (ORv4f32_f32 R32FP:$rA)>;
1570 def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)),
1571 (ORv2f64_f64 R64FP:$rA)>;
1573 // ORi*_v*: Used to extract vector element 0 (the preferred slot), otherwise
1574 // known as converting the vector back to its preferred slot
1576 def : Pat<(SPUvec2prefslot (v16i8 VECREG:$rA)),
1577 (ORi8_v16i8 VECREG:$rA)>;
1579 def : Pat<(SPUvec2prefslot (v8i16 VECREG:$rA)),
1580 (ORi16_v8i16 VECREG:$rA)>;
1582 def : Pat<(SPUvec2prefslot (v4i32 VECREG:$rA)),
1583 (ORi32_v4i32 VECREG:$rA)>;
1585 def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)),
1586 (ORi64_v2i64 VECREG:$rA)>;
1588 def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)),
1589 (ORf32_v4f32 VECREG:$rA)>;
1591 def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)),
1592 (ORf64_v2f64 VECREG:$rA)>;
1594 // Load Register: This is an assembler alias for a bitwise OR of a register
1595 // against itself. It's here because it brings some clarity to assembly
1598 let hasCtrlDep = 1 in {
1599 class LRInst<dag OOL, dag IOL>
1600 : SPUInstr<OOL, IOL, "lr\t$rT, $rA", IntegerOp> {
1604 let Pattern = [/*no pattern*/];
1606 let Inst{0-10} = 0b10000010000; /* It's an OR operation */
1607 let Inst{11-17} = RA;
1608 let Inst{18-24} = RA;
1609 let Inst{25-31} = RT;
1612 class LRVecInst<ValueType vectype>:
1613 LRInst<(outs VECREG:$rT), (ins VECREG:$rA)>;
1615 class LRRegInst<RegisterClass rclass>:
1616 LRInst<(outs rclass:$rT), (ins rclass:$rA)>;
1618 multiclass LoadRegister {
1619 def v2i64: LRVecInst<v2i64>;
1620 def v2f64: LRVecInst<v2f64>;
1621 def v4i32: LRVecInst<v4i32>;
1622 def v4f32: LRVecInst<v4f32>;
1623 def v8i16: LRVecInst<v8i16>;
1624 def v16i8: LRVecInst<v16i8>;
1626 def r128: LRRegInst<GPRC>;
1627 def r64: LRRegInst<R64C>;
1628 def f64: LRRegInst<R64FP>;
1629 def r32: LRRegInst<R32C>;
1630 def f32: LRRegInst<R32FP>;
1631 def r16: LRRegInst<R16C>;
1632 def r8: LRRegInst<R8C>;
1635 defm LR: LoadRegister;
1638 // ORC: Bitwise "or" with complement (c = a | ~b)
1640 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1641 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1642 IntegerOp, pattern>;
1644 class ORCVecInst<ValueType vectype>:
1645 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1646 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1647 (vnot (vectype VECREG:$rB))))]>;
1649 class ORCRegInst<RegisterClass rclass>:
1650 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1651 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1653 multiclass BitwiseOrComplement
1655 def v16i8: ORCVecInst<v16i8>;
1656 def v8i16: ORCVecInst<v8i16>;
1657 def v4i32: ORCVecInst<v4i32>;
1658 def v2i64: ORCVecInst<v2i64>;
1660 def r128: ORCRegInst<GPRC>;
1661 def r64: ORCRegInst<R64C>;
1662 def r32: ORCRegInst<R32C>;
1663 def r16: ORCRegInst<R16C>;
1664 def r8: ORCRegInst<R8C>;
1667 defm ORC : BitwiseOrComplement;
1669 // OR byte immediate
1670 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1671 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1672 IntegerOp, pattern>;
1674 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1675 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1676 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1677 (vectype immpred:$val)))]>;
1679 multiclass BitwiseOrByteImm
1681 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1683 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1684 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1687 defm ORBI : BitwiseOrByteImm;
1689 // OR halfword immediate
1690 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1691 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1692 IntegerOp, pattern>;
1694 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1695 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1696 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1699 multiclass BitwiseOrHalfwordImm
1701 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1703 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1704 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1706 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1707 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1708 [(set R16C:$rT, (or (anyext R8C:$rA),
1709 i16ImmSExt10:$val))]>;
1712 defm ORHI : BitwiseOrHalfwordImm;
1714 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1715 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1716 IntegerOp, pattern>;
1718 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1719 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1720 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1723 // Bitwise "or" with immediate
1724 multiclass BitwiseOrImm
1726 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1728 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1729 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1731 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1732 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1733 // infra "anyext 16->32" pattern.)
1734 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1735 [(set R32C:$rT, (or (anyext R16C:$rA),
1736 i32ImmSExt10:$val))]>;
1738 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1739 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1740 // infra "anyext 16->32" pattern.)
1741 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1742 [(set R32C:$rT, (or (anyext R8C:$rA),
1743 i32ImmSExt10:$val))]>;
1746 defm ORI : BitwiseOrImm;
1748 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1749 // $rT[0], slots 1-3 are zeroed.
1751 // FIXME: Needs to match an intrinsic pattern.
1753 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1754 "orx\t$rT, $rA, $rB", IntegerOp,
1759 class XORInst<dag OOL, dag IOL, list<dag> pattern> :
1760 RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB",
1761 IntegerOp, pattern>;
1763 class XORVecInst<ValueType vectype>:
1764 XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1765 [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA),
1766 (vectype VECREG:$rB)))]>;
1768 class XORRegInst<RegisterClass rclass>:
1769 XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1770 [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>;
1772 multiclass BitwiseExclusiveOr
1774 def v16i8: XORVecInst<v16i8>;
1775 def v8i16: XORVecInst<v8i16>;
1776 def v4i32: XORVecInst<v4i32>;
1777 def v2i64: XORVecInst<v2i64>;
1779 def r128: XORRegInst<GPRC>;
1780 def r64: XORRegInst<R64C>;
1781 def r32: XORRegInst<R32C>;
1782 def r16: XORRegInst<R16C>;
1783 def r8: XORRegInst<R8C>;
1785 // XOR instructions used to negate f32 and f64 quantities.
1787 def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1788 [/* no pattern */]>;
1790 def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB),
1791 [/* no pattern */]>;
1793 def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1794 [/* no pattern, see fneg{32,64} */]>;
1797 defm XOR : BitwiseExclusiveOr;
1799 //==----------------------------------------------------------
1801 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1802 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1803 IntegerOp, pattern>;
1805 multiclass XorByteImm
1808 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1809 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1812 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1813 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1816 defm XORBI : XorByteImm;
1819 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1820 "xorhi\t$rT, $rA, $val", IntegerOp,
1821 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1822 v8i16SExt10Imm:$val))]>;
1825 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1826 "xorhi\t$rT, $rA, $val", IntegerOp,
1827 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1830 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
1831 "xori\t$rT, $rA, $val", IntegerOp,
1832 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1833 v4i32SExt10Imm:$val))]>;
1836 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1837 "xori\t$rT, $rA, $val", IntegerOp,
1838 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1842 class NANDInst<dag OOL, dag IOL, list<dag> pattern>:
1843 RRForm<0b10010011000, OOL, IOL, "nand\t$rT, $rA, $rB",
1844 IntegerOp, pattern>;
1846 class NANDVecInst<ValueType vectype>:
1847 NANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1848 [(set (vectype VECREG:$rT), (vnot (and (vectype VECREG:$rA),
1849 (vectype VECREG:$rB))))]>;
1850 class NANDRegInst<RegisterClass rclass>:
1851 NANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1852 [(set rclass:$rT, (not (and rclass:$rA, rclass:$rB)))]>;
1854 multiclass BitwiseNand
1856 def v16i8: NANDVecInst<v16i8>;
1857 def v8i16: NANDVecInst<v8i16>;
1858 def v4i32: NANDVecInst<v4i32>;
1859 def v2i64: NANDVecInst<v2i64>;
1861 def r128: NANDRegInst<GPRC>;
1862 def r64: NANDRegInst<R64C>;
1863 def r32: NANDRegInst<R32C>;
1864 def r16: NANDRegInst<R16C>;
1865 def r8: NANDRegInst<R8C>;
1868 defm NAND : BitwiseNand;
1872 class NORInst<dag OOL, dag IOL, list<dag> pattern>:
1873 RRForm<0b10010010000, OOL, IOL, "nor\t$rT, $rA, $rB",
1874 IntegerOp, pattern>;
1876 class NORVecInst<ValueType vectype>:
1877 NORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1878 [(set (vectype VECREG:$rT), (vnot (or (vectype VECREG:$rA),
1879 (vectype VECREG:$rB))))]>;
1880 class NORRegInst<RegisterClass rclass>:
1881 NORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1882 [(set rclass:$rT, (not (or rclass:$rA, rclass:$rB)))]>;
1884 multiclass BitwiseNor
1886 def v16i8: NORVecInst<v16i8>;
1887 def v8i16: NORVecInst<v8i16>;
1888 def v4i32: NORVecInst<v4i32>;
1889 def v2i64: NORVecInst<v2i64>;
1891 def r128: NORRegInst<GPRC>;
1892 def r64: NORRegInst<R64C>;
1893 def r32: NORRegInst<R32C>;
1894 def r16: NORRegInst<R16C>;
1895 def r8: NORRegInst<R8C>;
1898 defm NOR : BitwiseNor;
1901 class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
1902 RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC",
1903 IntegerOp, pattern>;
1905 class SELBVecInst<ValueType vectype, PatFrag vnot_frag = vnot>:
1906 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1907 [(set (vectype VECREG:$rT),
1908 (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)),
1909 (and (vnot_frag (vectype VECREG:$rC)),
1910 (vectype VECREG:$rA))))]>;
1912 class SELBVecVCondInst<ValueType vectype>:
1913 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1914 [(set (vectype VECREG:$rT),
1915 (select (vectype VECREG:$rC),
1916 (vectype VECREG:$rB),
1917 (vectype VECREG:$rA)))]>;
1919 class SELBVecCondInst<ValueType vectype>:
1920 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, R32C:$rC),
1921 [(set (vectype VECREG:$rT),
1923 (vectype VECREG:$rB),
1924 (vectype VECREG:$rA)))]>;
1926 class SELBRegInst<RegisterClass rclass>:
1927 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
1929 (or (and rclass:$rB, rclass:$rC),
1930 (and rclass:$rA, (not rclass:$rC))))]>;
1932 class SELBRegCondInst<RegisterClass rcond, RegisterClass rclass>:
1933 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rcond:$rC),
1935 (select rcond:$rC, rclass:$rB, rclass:$rA))]>;
1937 multiclass SelectBits
1939 def v16i8: SELBVecInst<v16i8>;
1940 def v8i16: SELBVecInst<v8i16>;
1941 def v4i32: SELBVecInst<v4i32>;
1942 def v2i64: SELBVecInst<v2i64, vnot_cell_conv>;
1944 def r128: SELBRegInst<GPRC>;
1945 def r64: SELBRegInst<R64C>;
1946 def r32: SELBRegInst<R32C>;
1947 def r16: SELBRegInst<R16C>;
1948 def r8: SELBRegInst<R8C>;
1950 def v16i8_cond: SELBVecCondInst<v16i8>;
1951 def v8i16_cond: SELBVecCondInst<v8i16>;
1952 def v4i32_cond: SELBVecCondInst<v4i32>;
1953 def v2i64_cond: SELBVecCondInst<v2i64>;
1955 def v16i8_vcond: SELBVecCondInst<v16i8>;
1956 def v8i16_vcond: SELBVecCondInst<v8i16>;
1957 def v4i32_vcond: SELBVecCondInst<v4i32>;
1958 def v2i64_vcond: SELBVecCondInst<v2i64>;
1961 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1962 [(set (v4f32 VECREG:$rT),
1963 (select (v4i32 VECREG:$rC),
1965 (v4f32 VECREG:$rA)))]>;
1967 // SELBr64_cond is defined in SPU64InstrInfo.td
1968 def r32_cond: SELBRegCondInst<R32C, R32C>;
1969 def f32_cond: SELBRegCondInst<R32C, R32FP>;
1970 def r16_cond: SELBRegCondInst<R16C, R16C>;
1971 def r8_cond: SELBRegCondInst<R8C, R8C>;
1974 defm SELB : SelectBits;
1976 class SPUselbPatVec<ValueType vectype, SPUInstr inst>:
1977 Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)),
1978 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1980 def : SPUselbPatVec<v16i8, SELBv16i8>;
1981 def : SPUselbPatVec<v8i16, SELBv8i16>;
1982 def : SPUselbPatVec<v4i32, SELBv4i32>;
1983 def : SPUselbPatVec<v2i64, SELBv2i64>;
1985 class SPUselbPatReg<RegisterClass rclass, SPUInstr inst>:
1986 Pat<(SPUselb rclass:$rA, rclass:$rB, rclass:$rC),
1987 (inst rclass:$rA, rclass:$rB, rclass:$rC)>;
1989 def : SPUselbPatReg<R8C, SELBr8>;
1990 def : SPUselbPatReg<R16C, SELBr16>;
1991 def : SPUselbPatReg<R32C, SELBr32>;
1992 def : SPUselbPatReg<R64C, SELBr64>;
1994 // EQV: Equivalence (1 for each same bit, otherwise 0)
1996 // Note: There are a lot of ways to match this bit operator and these patterns
1997 // attempt to be as exhaustive as possible.
1999 class EQVInst<dag OOL, dag IOL, list<dag> pattern>:
2000 RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB",
2001 IntegerOp, pattern>;
2003 class EQVVecInst<ValueType vectype>:
2004 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2005 [(set (vectype VECREG:$rT),
2006 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
2007 (and (vnot (vectype VECREG:$rA)),
2008 (vnot (vectype VECREG:$rB)))))]>;
2010 class EQVRegInst<RegisterClass rclass>:
2011 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2012 [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB),
2013 (and (not rclass:$rA), (not rclass:$rB))))]>;
2015 class EQVVecPattern1<ValueType vectype>:
2016 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2017 [(set (vectype VECREG:$rT),
2018 (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>;
2020 class EQVRegPattern1<RegisterClass rclass>:
2021 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2022 [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>;
2024 class EQVVecPattern2<ValueType vectype>:
2025 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2026 [(set (vectype VECREG:$rT),
2027 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
2028 (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>;
2030 class EQVRegPattern2<RegisterClass rclass>:
2031 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2033 (or (and rclass:$rA, rclass:$rB),
2034 (not (or rclass:$rA, rclass:$rB))))]>;
2036 class EQVVecPattern3<ValueType vectype>:
2037 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2038 [(set (vectype VECREG:$rT),
2039 (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>;
2041 class EQVRegPattern3<RegisterClass rclass>:
2042 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2043 [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>;
2045 multiclass BitEquivalence
2047 def v16i8: EQVVecInst<v16i8>;
2048 def v8i16: EQVVecInst<v8i16>;
2049 def v4i32: EQVVecInst<v4i32>;
2050 def v2i64: EQVVecInst<v2i64>;
2052 def v16i8_1: EQVVecPattern1<v16i8>;
2053 def v8i16_1: EQVVecPattern1<v8i16>;
2054 def v4i32_1: EQVVecPattern1<v4i32>;
2055 def v2i64_1: EQVVecPattern1<v2i64>;
2057 def v16i8_2: EQVVecPattern2<v16i8>;
2058 def v8i16_2: EQVVecPattern2<v8i16>;
2059 def v4i32_2: EQVVecPattern2<v4i32>;
2060 def v2i64_2: EQVVecPattern2<v2i64>;
2062 def v16i8_3: EQVVecPattern3<v16i8>;
2063 def v8i16_3: EQVVecPattern3<v8i16>;
2064 def v4i32_3: EQVVecPattern3<v4i32>;
2065 def v2i64_3: EQVVecPattern3<v2i64>;
2067 def r128: EQVRegInst<GPRC>;
2068 def r64: EQVRegInst<R64C>;
2069 def r32: EQVRegInst<R32C>;
2070 def r16: EQVRegInst<R16C>;
2071 def r8: EQVRegInst<R8C>;
2073 def r128_1: EQVRegPattern1<GPRC>;
2074 def r64_1: EQVRegPattern1<R64C>;
2075 def r32_1: EQVRegPattern1<R32C>;
2076 def r16_1: EQVRegPattern1<R16C>;
2077 def r8_1: EQVRegPattern1<R8C>;
2079 def r128_2: EQVRegPattern2<GPRC>;
2080 def r64_2: EQVRegPattern2<R64C>;
2081 def r32_2: EQVRegPattern2<R32C>;
2082 def r16_2: EQVRegPattern2<R16C>;
2083 def r8_2: EQVRegPattern2<R8C>;
2085 def r128_3: EQVRegPattern3<GPRC>;
2086 def r64_3: EQVRegPattern3<R64C>;
2087 def r32_3: EQVRegPattern3<R32C>;
2088 def r16_3: EQVRegPattern3<R16C>;
2089 def r8_3: EQVRegPattern3<R8C>;
2092 defm EQV: BitEquivalence;
2094 //===----------------------------------------------------------------------===//
2095 // Vector shuffle...
2096 //===----------------------------------------------------------------------===//
2097 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
2098 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
2099 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
2100 // the SPUISD::SHUFB opcode.
2101 //===----------------------------------------------------------------------===//
2103 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
2104 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
2105 IntegerOp, pattern>;
2107 class SHUFBVecInst<ValueType resultvec, ValueType maskvec>:
2108 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2109 [(set (resultvec VECREG:$rT),
2110 (SPUshuffle (resultvec VECREG:$rA),
2111 (resultvec VECREG:$rB),
2112 (maskvec VECREG:$rC)))]>;
2114 class SHUFBGPRCInst:
2115 SHUFBInst<(outs VECREG:$rT), (ins GPRC:$rA, GPRC:$rB, VECREG:$rC),
2116 [/* no pattern */]>;
2118 multiclass ShuffleBytes
2120 def v16i8 : SHUFBVecInst<v16i8, v16i8>;
2121 def v16i8_m32 : SHUFBVecInst<v16i8, v4i32>;
2122 def v8i16 : SHUFBVecInst<v8i16, v16i8>;
2123 def v8i16_m32 : SHUFBVecInst<v8i16, v4i32>;
2124 def v4i32 : SHUFBVecInst<v4i32, v16i8>;
2125 def v4i32_m32 : SHUFBVecInst<v4i32, v4i32>;
2126 def v2i64 : SHUFBVecInst<v2i64, v16i8>;
2127 def v2i64_m32 : SHUFBVecInst<v2i64, v4i32>;
2129 def v4f32 : SHUFBVecInst<v4f32, v16i8>;
2130 def v4f32_m32 : SHUFBVecInst<v4f32, v4i32>;
2132 def v2f64 : SHUFBVecInst<v2f64, v16i8>;
2133 def v2f64_m32 : SHUFBVecInst<v2f64, v4i32>;
2135 def gprc : SHUFBGPRCInst;
2138 defm SHUFB : ShuffleBytes;
2140 //===----------------------------------------------------------------------===//
2141 // Shift and rotate group:
2142 //===----------------------------------------------------------------------===//
2144 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
2145 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
2146 RotateShift, pattern>;
2148 class SHLHVecInst<ValueType vectype>:
2149 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2150 [(set (vectype VECREG:$rT),
2151 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
2153 multiclass ShiftLeftHalfword
2155 def v8i16: SHLHVecInst<v8i16>;
2156 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2157 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
2158 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2159 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
2162 defm SHLH : ShiftLeftHalfword;
2164 //===----------------------------------------------------------------------===//
2166 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
2167 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
2168 RotateShift, pattern>;
2170 class SHLHIVecInst<ValueType vectype>:
2171 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2172 [(set (vectype VECREG:$rT),
2173 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2175 multiclass ShiftLeftHalfwordImm
2177 def v8i16: SHLHIVecInst<v8i16>;
2178 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2179 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
2182 defm SHLHI : ShiftLeftHalfwordImm;
2184 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
2185 (SHLHIv8i16 VECREG:$rA, (TO_IMM16 uimm7:$val))>;
2187 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
2188 (SHLHIr16 R16C:$rA, (TO_IMM16 uimm7:$val))>;
2190 //===----------------------------------------------------------------------===//
2192 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
2193 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
2194 RotateShift, pattern>;
2196 multiclass ShiftLeftWord
2199 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2200 [(set (v4i32 VECREG:$rT),
2201 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
2203 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2204 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
2207 defm SHL: ShiftLeftWord;
2209 //===----------------------------------------------------------------------===//
2211 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
2212 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
2213 RotateShift, pattern>;
2215 multiclass ShiftLeftWordImm
2218 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2219 [(set (v4i32 VECREG:$rT),
2220 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
2223 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2224 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
2227 defm SHLI : ShiftLeftWordImm;
2229 //===----------------------------------------------------------------------===//
2230 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
2231 // register) to the left. Vector form is here to ensure type correctness.
2233 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
2234 // of 7 bits is actually possible.
2236 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
2237 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
2238 // bytes with SHLQBY.
2240 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2241 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
2242 RotateShift, pattern>;
2244 class SHLQBIVecInst<ValueType vectype>:
2245 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2246 [(set (vectype VECREG:$rT),
2247 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
2249 class SHLQBIRegInst<RegisterClass rclass>:
2250 SHLQBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2251 [/* no pattern */]>;
2253 multiclass ShiftLeftQuadByBits
2255 def v16i8: SHLQBIVecInst<v16i8>;
2256 def v8i16: SHLQBIVecInst<v8i16>;
2257 def v4i32: SHLQBIVecInst<v4i32>;
2258 def v4f32: SHLQBIVecInst<v4f32>;
2259 def v2i64: SHLQBIVecInst<v2i64>;
2260 def v2f64: SHLQBIVecInst<v2f64>;
2262 def r128: SHLQBIRegInst<GPRC>;
2265 defm SHLQBI : ShiftLeftQuadByBits;
2267 // See note above on SHLQBI. In this case, the predicate actually does then
2268 // enforcement, whereas with SHLQBI, we have to "take it on faith."
2269 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2270 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
2271 RotateShift, pattern>;
2273 class SHLQBIIVecInst<ValueType vectype>:
2274 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2275 [(set (vectype VECREG:$rT),
2276 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
2278 multiclass ShiftLeftQuadByBitsImm
2280 def v16i8 : SHLQBIIVecInst<v16i8>;
2281 def v8i16 : SHLQBIIVecInst<v8i16>;
2282 def v4i32 : SHLQBIIVecInst<v4i32>;
2283 def v4f32 : SHLQBIIVecInst<v4f32>;
2284 def v2i64 : SHLQBIIVecInst<v2i64>;
2285 def v2f64 : SHLQBIIVecInst<v2f64>;
2288 defm SHLQBII : ShiftLeftQuadByBitsImm;
2290 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
2291 // not by bits. See notes above on SHLQBI.
2293 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2294 RI7Form<0b11111011100, OOL, IOL, "shlqby\t$rT, $rA, $rB",
2295 RotateShift, pattern>;
2297 class SHLQBYVecInst<ValueType vectype>:
2298 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2299 [(set (vectype VECREG:$rT),
2300 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
2302 multiclass ShiftLeftQuadBytes
2304 def v16i8: SHLQBYVecInst<v16i8>;
2305 def v8i16: SHLQBYVecInst<v8i16>;
2306 def v4i32: SHLQBYVecInst<v4i32>;
2307 def v4f32: SHLQBYVecInst<v4f32>;
2308 def v2i64: SHLQBYVecInst<v2i64>;
2309 def v2f64: SHLQBYVecInst<v2f64>;
2310 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
2311 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
2314 defm SHLQBY: ShiftLeftQuadBytes;
2316 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2317 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
2318 RotateShift, pattern>;
2320 class SHLQBYIVecInst<ValueType vectype>:
2321 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2322 [(set (vectype VECREG:$rT),
2323 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2325 multiclass ShiftLeftQuadBytesImm
2327 def v16i8: SHLQBYIVecInst<v16i8>;
2328 def v8i16: SHLQBYIVecInst<v8i16>;
2329 def v4i32: SHLQBYIVecInst<v4i32>;
2330 def v4f32: SHLQBYIVecInst<v4f32>;
2331 def v2i64: SHLQBYIVecInst<v2i64>;
2332 def v2f64: SHLQBYIVecInst<v2f64>;
2333 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
2335 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
2338 defm SHLQBYI : ShiftLeftQuadBytesImm;
2340 class SHLQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2341 RRForm<0b00111001111, OOL, IOL, "shlqbybi\t$rT, $rA, $rB",
2342 RotateShift, pattern>;
2344 class SHLQBYBIVecInst<ValueType vectype>:
2345 SHLQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2346 [/* no pattern */]>;
2348 class SHLQBYBIRegInst<RegisterClass rclass>:
2349 SHLQBYBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2350 [/* no pattern */]>;
2352 multiclass ShiftLeftQuadBytesBitCount
2354 def v16i8: SHLQBYBIVecInst<v16i8>;
2355 def v8i16: SHLQBYBIVecInst<v8i16>;
2356 def v4i32: SHLQBYBIVecInst<v4i32>;
2357 def v4f32: SHLQBYBIVecInst<v4f32>;
2358 def v2i64: SHLQBYBIVecInst<v2i64>;
2359 def v2f64: SHLQBYBIVecInst<v2f64>;
2361 def r128: SHLQBYBIRegInst<GPRC>;
2364 defm SHLQBYBI : ShiftLeftQuadBytesBitCount;
2366 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2368 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2369 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
2370 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
2371 RotateShift, pattern>;
2373 class ROTHVecInst<ValueType vectype>:
2374 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2375 [(set (vectype VECREG:$rT),
2376 (SPUvec_rotl VECREG:$rA, (v8i16 VECREG:$rB)))]>;
2378 class ROTHRegInst<RegisterClass rclass>:
2379 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2380 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
2382 multiclass RotateLeftHalfword
2384 def v8i16: ROTHVecInst<v8i16>;
2385 def r16: ROTHRegInst<R16C>;
2388 defm ROTH: RotateLeftHalfword;
2390 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2391 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2393 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2394 // Rotate halfword, immediate:
2395 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2396 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
2397 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
2398 RotateShift, pattern>;
2400 class ROTHIVecInst<ValueType vectype>:
2401 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2402 [(set (vectype VECREG:$rT),
2403 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
2405 multiclass RotateLeftHalfwordImm
2407 def v8i16: ROTHIVecInst<v8i16>;
2408 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2409 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2410 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2411 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2414 defm ROTHI: RotateLeftHalfwordImm;
2416 def : Pat<(SPUvec_rotl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
2417 (ROTHIv8i16 VECREG:$rA, (TO_IMM16 imm:$val))>;
2419 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2421 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2423 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
2424 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
2425 RotateShift, pattern>;
2427 class ROTVecInst<ValueType vectype>:
2428 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2429 [(set (vectype VECREG:$rT),
2430 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
2432 class ROTRegInst<RegisterClass rclass>:
2433 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2435 (rotl rclass:$rA, R32C:$rB))]>;
2437 multiclass RotateLeftWord
2439 def v4i32: ROTVecInst<v4i32>;
2440 def r32: ROTRegInst<R32C>;
2443 defm ROT: RotateLeftWord;
2445 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2447 def ROTr32_r16_anyext:
2448 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2449 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2451 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
2452 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2454 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
2455 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2457 def ROTr32_r8_anyext:
2458 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2459 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2461 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
2462 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2464 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
2465 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2467 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2468 // Rotate word, immediate
2469 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2471 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
2472 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
2473 RotateShift, pattern>;
2475 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
2476 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2477 [(set (vectype VECREG:$rT),
2478 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2480 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2481 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2482 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2484 multiclass RotateLeftWordImm
2486 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2487 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
2488 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
2490 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
2491 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
2492 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
2495 defm ROTI : RotateLeftWordImm;
2497 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2498 // Rotate quad by byte (count)
2499 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2501 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2502 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2503 RotateShift, pattern>;
2505 class ROTQBYVecInst<ValueType vectype>:
2506 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2507 [(set (vectype VECREG:$rT),
2508 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2510 multiclass RotateQuadLeftByBytes
2512 def v16i8: ROTQBYVecInst<v16i8>;
2513 def v8i16: ROTQBYVecInst<v8i16>;
2514 def v4i32: ROTQBYVecInst<v4i32>;
2515 def v4f32: ROTQBYVecInst<v4f32>;
2516 def v2i64: ROTQBYVecInst<v2i64>;
2517 def v2f64: ROTQBYVecInst<v2f64>;
2520 defm ROTQBY: RotateQuadLeftByBytes;
2522 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2523 // Rotate quad by byte (count), immediate
2524 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2526 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2527 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2528 RotateShift, pattern>;
2530 class ROTQBYIVecInst<ValueType vectype>:
2531 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2532 [(set (vectype VECREG:$rT),
2533 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2535 multiclass RotateQuadByBytesImm
2537 def v16i8: ROTQBYIVecInst<v16i8>;
2538 def v8i16: ROTQBYIVecInst<v8i16>;
2539 def v4i32: ROTQBYIVecInst<v4i32>;
2540 def v4f32: ROTQBYIVecInst<v4f32>;
2541 def v2i64: ROTQBYIVecInst<v2i64>;
2542 def vfi64: ROTQBYIVecInst<v2f64>;
2545 defm ROTQBYI: RotateQuadByBytesImm;
2547 // See ROTQBY note above.
2548 class ROTQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2549 RI7Form<0b00110011100, OOL, IOL,
2550 "rotqbybi\t$rT, $rA, $shift",
2551 RotateShift, pattern>;
2553 class ROTQBYBIVecInst<ValueType vectype, RegisterClass rclass>:
2554 ROTQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, rclass:$shift),
2555 [(set (vectype VECREG:$rT),
2556 (SPUrotbytes_left_bits (vectype VECREG:$rA), rclass:$shift))]>;
2558 multiclass RotateQuadByBytesByBitshift {
2559 def v16i8_r32: ROTQBYBIVecInst<v16i8, R32C>;
2560 def v8i16_r32: ROTQBYBIVecInst<v8i16, R32C>;
2561 def v4i32_r32: ROTQBYBIVecInst<v4i32, R32C>;
2562 def v2i64_r32: ROTQBYBIVecInst<v2i64, R32C>;
2565 defm ROTQBYBI : RotateQuadByBytesByBitshift;
2567 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2568 // See ROTQBY note above.
2570 // Assume that the user of this instruction knows to shift the rotate count
2572 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2574 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2575 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2576 RotateShift, pattern>;
2578 class ROTQBIVecInst<ValueType vectype>:
2579 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2580 [/* no pattern yet */]>;
2582 class ROTQBIRegInst<RegisterClass rclass>:
2583 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2584 [/* no pattern yet */]>;
2586 multiclass RotateQuadByBitCount
2588 def v16i8: ROTQBIVecInst<v16i8>;
2589 def v8i16: ROTQBIVecInst<v8i16>;
2590 def v4i32: ROTQBIVecInst<v4i32>;
2591 def v2i64: ROTQBIVecInst<v2i64>;
2593 def r128: ROTQBIRegInst<GPRC>;
2594 def r64: ROTQBIRegInst<R64C>;
2597 defm ROTQBI: RotateQuadByBitCount;
2599 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2600 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2601 RotateShift, pattern>;
2603 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2605 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2606 [/* no pattern yet */]>;
2608 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2610 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2611 [/* no pattern yet */]>;
2613 multiclass RotateQuadByBitCountImm
2615 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2616 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2617 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2618 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2620 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2621 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2624 defm ROTQBII : RotateQuadByBitCountImm;
2626 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2627 // ROTHM v8i16 form:
2628 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2629 // so this only matches a synthetically generated/lowered code
2631 // NOTE(2): $rB must be negated before the right rotate!
2632 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2634 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2635 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2636 RotateShift, pattern>;
2639 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2640 [/* see patterns below - $rB must be negated */]>;
2642 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2643 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2645 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2646 (ROTHMv8i16 VECREG:$rA,
2647 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2649 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2650 (ROTHMv8i16 VECREG:$rA,
2651 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2653 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2654 // Note: This instruction doesn't match a pattern because rB must be negated
2655 // for the instruction to work. Thus, the pattern below the instruction!
2658 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2659 [/* see patterns below - $rB must be negated! */]>;
2661 def : Pat<(srl R16C:$rA, R32C:$rB),
2662 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2664 def : Pat<(srl R16C:$rA, R16C:$rB),
2666 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2668 def : Pat<(srl R16C:$rA, R8C:$rB),
2670 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2672 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2673 // that the immediate can be complemented, so that the user doesn't have to
2676 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2677 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2678 RotateShift, pattern>;
2681 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2682 [/* no pattern */]>;
2684 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2685 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2687 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2688 (ROTHMIv8i16 VECREG:$rA, (TO_IMM32 imm:$val))>;
2690 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2691 (ROTHMIv8i16 VECREG:$rA, (TO_IMM32 imm:$val))>;
2694 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2695 [/* no pattern */]>;
2697 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2698 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2700 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2701 (ROTHMIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
2703 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2704 (ROTHMIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
2706 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2707 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2708 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2709 RotateShift, pattern>;
2712 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2713 [/* see patterns below - $rB must be negated */]>;
2715 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R32C:$rB),
2716 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2718 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R16C:$rB),
2719 (ROTMv4i32 VECREG:$rA,
2720 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2722 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R8C:$rB),
2723 (ROTMv4i32 VECREG:$rA,
2724 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2727 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2728 [/* see patterns below - $rB must be negated */]>;
2730 def : Pat<(srl R32C:$rA, R32C:$rB),
2731 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2733 def : Pat<(srl R32C:$rA, R16C:$rB),
2735 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2737 def : Pat<(srl R32C:$rA, R8C:$rB),
2739 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2741 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2743 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2744 "rotmi\t$rT, $rA, $val", RotateShift,
2745 [(set (v4i32 VECREG:$rT),
2746 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2748 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2749 (ROTMIv4i32 VECREG:$rA, (TO_IMM32 uimm7:$val))>;
2751 def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (i8 uimm7:$val)),
2752 (ROTMIv4i32 VECREG:$rA, (TO_IMM32 uimm7:$val))>;
2754 // ROTMI r32 form: know how to complement the immediate value.
2756 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2757 "rotmi\t$rT, $rA, $val", RotateShift,
2758 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2760 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2761 (ROTMIr32 R32C:$rA, (TO_IMM32 uimm7:$val))>;
2763 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2764 (ROTMIr32 R32C:$rA, (TO_IMM32 uimm7:$val))>;
2766 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2767 // ROTQMBY: This is a vector form merely so that when used in an
2768 // instruction pattern, type checking will succeed. This instruction assumes
2769 // that the user knew to negate $rB.
2770 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2772 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2773 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2774 RotateShift, pattern>;
2776 class ROTQMBYVecInst<ValueType vectype>:
2777 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2778 [/* no pattern, $rB must be negated */]>;
2780 class ROTQMBYRegInst<RegisterClass rclass>:
2781 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2782 [/* no pattern */]>;
2784 multiclass RotateQuadBytes
2786 def v16i8: ROTQMBYVecInst<v16i8>;
2787 def v8i16: ROTQMBYVecInst<v8i16>;
2788 def v4i32: ROTQMBYVecInst<v4i32>;
2789 def v2i64: ROTQMBYVecInst<v2i64>;
2791 def r128: ROTQMBYRegInst<GPRC>;
2792 def r64: ROTQMBYRegInst<R64C>;
2795 defm ROTQMBY : RotateQuadBytes;
2797 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2798 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2799 RotateShift, pattern>;
2801 class ROTQMBYIVecInst<ValueType vectype>:
2802 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2803 [/* no pattern */]>;
2805 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2807 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2808 [/* no pattern */]>;
2810 // 128-bit zero extension form:
2811 class ROTQMBYIZExtInst<RegisterClass rclass, Operand optype, PatLeaf pred>:
2812 ROTQMBYIInst<(outs GPRC:$rT), (ins rclass:$rA, optype:$val),
2813 [/* no pattern */]>;
2815 multiclass RotateQuadBytesImm
2817 def v16i8: ROTQMBYIVecInst<v16i8>;
2818 def v8i16: ROTQMBYIVecInst<v8i16>;
2819 def v4i32: ROTQMBYIVecInst<v4i32>;
2820 def v2i64: ROTQMBYIVecInst<v2i64>;
2822 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2823 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2825 def r128_zext_r8: ROTQMBYIZExtInst<R8C, rotNeg7imm, uimm7>;
2826 def r128_zext_r16: ROTQMBYIZExtInst<R16C, rotNeg7imm, uimm7>;
2827 def r128_zext_r32: ROTQMBYIZExtInst<R32C, rotNeg7imm, uimm7>;
2828 def r128_zext_r64: ROTQMBYIZExtInst<R64C, rotNeg7imm, uimm7>;
2831 defm ROTQMBYI : RotateQuadBytesImm;
2833 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2834 // Rotate right and mask by bit count
2835 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2837 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2838 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2839 RotateShift, pattern>;
2841 class ROTQMBYBIVecInst<ValueType vectype>:
2842 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2843 [/* no pattern, */]>;
2845 multiclass RotateMaskQuadByBitCount
2847 def v16i8: ROTQMBYBIVecInst<v16i8>;
2848 def v8i16: ROTQMBYBIVecInst<v8i16>;
2849 def v4i32: ROTQMBYBIVecInst<v4i32>;
2850 def v2i64: ROTQMBYBIVecInst<v2i64>;
2853 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2855 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2856 // Rotate quad and mask by bits
2857 // Note that the rotate amount has to be negated
2858 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2860 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2861 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2862 RotateShift, pattern>;
2864 class ROTQMBIVecInst<ValueType vectype>:
2865 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2866 [/* no pattern */]>;
2868 class ROTQMBIRegInst<RegisterClass rclass>:
2869 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2870 [/* no pattern */]>;
2872 multiclass RotateMaskQuadByBits
2874 def v16i8: ROTQMBIVecInst<v16i8>;
2875 def v8i16: ROTQMBIVecInst<v8i16>;
2876 def v4i32: ROTQMBIVecInst<v4i32>;
2877 def v2i64: ROTQMBIVecInst<v2i64>;
2879 def r128: ROTQMBIRegInst<GPRC>;
2880 def r64: ROTQMBIRegInst<R64C>;
2883 defm ROTQMBI: RotateMaskQuadByBits;
2885 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2886 // Rotate quad and mask by bits, immediate
2887 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2889 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2890 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2891 RotateShift, pattern>;
2893 class ROTQMBIIVecInst<ValueType vectype>:
2894 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2895 [/* no pattern */]>;
2897 class ROTQMBIIRegInst<RegisterClass rclass>:
2898 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2899 [/* no pattern */]>;
2901 multiclass RotateMaskQuadByBitsImm
2903 def v16i8: ROTQMBIIVecInst<v16i8>;
2904 def v8i16: ROTQMBIIVecInst<v8i16>;
2905 def v4i32: ROTQMBIIVecInst<v4i32>;
2906 def v2i64: ROTQMBIIVecInst<v2i64>;
2908 def r128: ROTQMBIIRegInst<GPRC>;
2909 def r64: ROTQMBIIRegInst<R64C>;
2912 defm ROTQMBII: RotateMaskQuadByBitsImm;
2914 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2915 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2918 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2919 "rotmah\t$rT, $rA, $rB", RotateShift,
2920 [/* see patterns below - $rB must be negated */]>;
2922 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R32C:$rB),
2923 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2925 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R16C:$rB),
2926 (ROTMAHv8i16 VECREG:$rA,
2927 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2929 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R8C:$rB),
2930 (ROTMAHv8i16 VECREG:$rA,
2931 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2934 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2935 "rotmah\t$rT, $rA, $rB", RotateShift,
2936 [/* see patterns below - $rB must be negated */]>;
2938 def : Pat<(sra R16C:$rA, R32C:$rB),
2939 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2941 def : Pat<(sra R16C:$rA, R16C:$rB),
2942 (ROTMAHr16 R16C:$rA,
2943 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2945 def : Pat<(sra R16C:$rA, R8C:$rB),
2946 (ROTMAHr16 R16C:$rA,
2947 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2950 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2951 "rotmahi\t$rT, $rA, $val", RotateShift,
2952 [(set (v8i16 VECREG:$rT),
2953 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2955 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2956 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (TO_IMM32 uimm7:$val))>;
2958 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2959 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (TO_IMM32 uimm7:$val))>;
2962 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2963 "rotmahi\t$rT, $rA, $val", RotateShift,
2964 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2966 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2967 (ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
2969 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2970 (ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
2973 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2974 "rotma\t$rT, $rA, $rB", RotateShift,
2975 [/* see patterns below - $rB must be negated */]>;
2977 def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R32C:$rB),
2978 (ROTMAv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2980 def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R16C:$rB),
2981 (ROTMAv4i32 VECREG:$rA,
2982 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2984 def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R8C:$rB),
2985 (ROTMAv4i32 VECREG:$rA,
2986 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2989 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2990 "rotma\t$rT, $rA, $rB", RotateShift,
2991 [/* see patterns below - $rB must be negated */]>;
2993 def : Pat<(sra R32C:$rA, R32C:$rB),
2994 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2996 def : Pat<(sra R32C:$rA, R16C:$rB),
2998 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
3000 def : Pat<(sra R32C:$rA, R8C:$rB),
3002 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
3004 class ROTMAIInst<dag OOL, dag IOL, list<dag> pattern>:
3005 RRForm<0b01011110000, OOL, IOL,
3006 "rotmai\t$rT, $rA, $val",
3007 RotateShift, pattern>;
3009 class ROTMAIVecInst<ValueType vectype, Operand intop, ValueType inttype>:
3010 ROTMAIInst<(outs VECREG:$rT), (ins VECREG:$rA, intop:$val),
3011 [(set (vectype VECREG:$rT),
3012 (SPUvec_sra VECREG:$rA, (inttype uimm7:$val)))]>;
3014 class ROTMAIRegInst<RegisterClass rclass, Operand intop, ValueType inttype>:
3015 ROTMAIInst<(outs rclass:$rT), (ins rclass:$rA, intop:$val),
3016 [(set rclass:$rT, (sra rclass:$rA, (inttype uimm7:$val)))]>;
3018 multiclass RotateMaskAlgebraicImm {
3019 def v2i64_i32 : ROTMAIVecInst<v2i64, rotNeg7imm, i32>;
3020 def v4i32_i32 : ROTMAIVecInst<v4i32, rotNeg7imm, i32>;
3021 def r64_i32 : ROTMAIRegInst<R64C, rotNeg7imm, i32>;
3022 def r32_i32 : ROTMAIRegInst<R32C, rotNeg7imm, i32>;
3025 defm ROTMAI : RotateMaskAlgebraicImm;
3027 //===----------------------------------------------------------------------===//
3028 // Branch and conditionals:
3029 //===----------------------------------------------------------------------===//
3031 let isTerminator = 1, isBarrier = 1 in {
3032 // Halt If Equal (r32 preferred slot only, no vector form)
3034 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
3035 "heq\t$rA, $rB", BranchResolv,
3036 [/* no pattern to match */]>;
3039 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
3040 "heqi\t$rA, $val", BranchResolv,
3041 [/* no pattern to match */]>;
3043 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
3044 // contrasting with HLGT/HLGTI, which use unsigned comparison:
3046 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
3047 "hgt\t$rA, $rB", BranchResolv,
3048 [/* no pattern to match */]>;
3051 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
3052 "hgti\t$rA, $val", BranchResolv,
3053 [/* no pattern to match */]>;
3056 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
3057 "hlgt\t$rA, $rB", BranchResolv,
3058 [/* no pattern to match */]>;
3061 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
3062 "hlgti\t$rA, $val", BranchResolv,
3063 [/* no pattern to match */]>;
3066 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3067 // Comparison operators for i8, i16 and i32:
3068 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3070 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
3071 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
3074 multiclass CmpEqualByte
3077 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3078 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
3079 (v8i16 VECREG:$rB)))]>;
3082 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
3083 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
3086 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
3087 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
3090 multiclass CmpEqualByteImm
3093 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3094 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
3095 v16i8SExt8Imm:$val))]>;
3097 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3098 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
3101 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
3102 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
3105 multiclass CmpEqualHalfword
3107 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3108 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
3109 (v8i16 VECREG:$rB)))]>;
3111 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3112 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
3115 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
3116 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
3119 multiclass CmpEqualHalfwordImm
3121 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3122 [(set (v8i16 VECREG:$rT),
3123 (seteq (v8i16 VECREG:$rA),
3124 (v8i16 v8i16SExt10Imm:$val)))]>;
3125 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3126 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
3129 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
3130 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
3133 multiclass CmpEqualWord
3135 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3136 [(set (v4i32 VECREG:$rT),
3137 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3139 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3140 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
3143 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
3144 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
3147 multiclass CmpEqualWordImm
3149 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3150 [(set (v4i32 VECREG:$rT),
3151 (seteq (v4i32 VECREG:$rA),
3152 (v4i32 v4i32SExt16Imm:$val)))]>;
3154 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3155 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
3158 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
3159 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
3162 multiclass CmpGtrByte
3165 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3166 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3167 (v8i16 VECREG:$rB)))]>;
3170 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
3171 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
3174 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
3175 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
3178 multiclass CmpGtrByteImm
3181 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3182 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
3183 v16i8SExt8Imm:$val))]>;
3185 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3186 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
3189 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
3190 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
3193 multiclass CmpGtrHalfword
3195 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3196 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3197 (v8i16 VECREG:$rB)))]>;
3199 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3200 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
3203 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
3204 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
3207 multiclass CmpGtrHalfwordImm
3209 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3210 [(set (v8i16 VECREG:$rT),
3211 (setgt (v8i16 VECREG:$rA),
3212 (v8i16 v8i16SExt10Imm:$val)))]>;
3213 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3214 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
3217 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
3218 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
3221 multiclass CmpGtrWord
3223 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3224 [(set (v4i32 VECREG:$rT),
3225 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3227 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3228 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
3231 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
3232 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
3235 multiclass CmpGtrWordImm
3237 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3238 [(set (v4i32 VECREG:$rT),
3239 (setgt (v4i32 VECREG:$rA),
3240 (v4i32 v4i32SExt16Imm:$val)))]>;
3242 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3243 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
3245 // CGTIv4f32, CGTIf32: These are used in the f32 fdiv instruction sequence:
3246 def v4f32: CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3247 [(set (v4i32 VECREG:$rT),
3248 (setgt (v4i32 (bitconvert (v4f32 VECREG:$rA))),
3249 (v4i32 v4i32SExt16Imm:$val)))]>;
3251 def f32: CGTIInst<(outs R32C:$rT), (ins R32FP:$rA, s10imm_i32:$val),
3252 [/* no pattern */]>;
3255 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
3256 RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB",
3259 multiclass CmpLGtrByte
3262 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3263 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3264 (v8i16 VECREG:$rB)))]>;
3267 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
3268 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
3271 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
3272 RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val",
3275 multiclass CmpLGtrByteImm
3278 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3279 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
3280 v16i8SExt8Imm:$val))]>;
3282 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3283 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
3286 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
3287 RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB",
3290 multiclass CmpLGtrHalfword
3292 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3293 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3294 (v8i16 VECREG:$rB)))]>;
3296 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3297 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
3300 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
3301 RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val",
3304 multiclass CmpLGtrHalfwordImm
3306 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3307 [(set (v8i16 VECREG:$rT),
3308 (setugt (v8i16 VECREG:$rA),
3309 (v8i16 v8i16SExt10Imm:$val)))]>;
3310 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3311 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
3314 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
3315 RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB",
3318 multiclass CmpLGtrWord
3320 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3321 [(set (v4i32 VECREG:$rT),
3322 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3324 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3325 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
3328 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
3329 RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val",
3332 multiclass CmpLGtrWordImm
3334 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3335 [(set (v4i32 VECREG:$rT),
3336 (setugt (v4i32 VECREG:$rA),
3337 (v4i32 v4i32SExt16Imm:$val)))]>;
3339 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3340 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
3343 defm CEQB : CmpEqualByte;
3344 defm CEQBI : CmpEqualByteImm;
3345 defm CEQH : CmpEqualHalfword;
3346 defm CEQHI : CmpEqualHalfwordImm;
3347 defm CEQ : CmpEqualWord;
3348 defm CEQI : CmpEqualWordImm;
3349 defm CGTB : CmpGtrByte;
3350 defm CGTBI : CmpGtrByteImm;
3351 defm CGTH : CmpGtrHalfword;
3352 defm CGTHI : CmpGtrHalfwordImm;
3353 defm CGT : CmpGtrWord;
3354 defm CGTI : CmpGtrWordImm;
3355 defm CLGTB : CmpLGtrByte;
3356 defm CLGTBI : CmpLGtrByteImm;
3357 defm CLGTH : CmpLGtrHalfword;
3358 defm CLGTHI : CmpLGtrHalfwordImm;
3359 defm CLGT : CmpLGtrWord;
3360 defm CLGTI : CmpLGtrWordImm;
3362 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3363 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
3364 // define a pattern to generate the right code, as a binary operator
3365 // (in a manner of speaking.)
3368 // 1. This only matches the setcc set of conditionals. Special pattern
3369 // matching is used for select conditionals.
3371 // 2. The "DAG" versions of these classes is almost exclusively used for
3372 // i64 comparisons. See the tblgen fundamentals documentation for what
3373 // ".ResultInstrs[0]" means; see TargetSelectionDAG.td and the Pattern
3374 // class for where ResultInstrs originates.
3375 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3377 class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3378 SPUInstr xorinst, SPUInstr cmpare>:
3379 Pat<(cond rclass:$rA, rclass:$rB),
3380 (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
3382 class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3383 PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
3384 Pat<(cond rclass:$rA, (inttype immpred:$imm)),
3385 (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
3387 def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
3388 def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
3390 def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
3391 def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
3393 def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
3394 def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
3396 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
3397 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3398 Pat<(cond rclass:$rA, rclass:$rB),
3399 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3400 (cmpOp2 rclass:$rA, rclass:$rB))>;
3402 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3404 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3405 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
3406 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
3407 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
3409 def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
3410 def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
3411 def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
3412 def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
3413 def : Pat<(setle R8C:$rA, R8C:$rB),
3414 (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3415 def : Pat<(setle R8C:$rA, immU8:$imm),
3416 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3418 def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
3419 def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
3420 ORr16, CGTHIr16, CEQHIr16>;
3421 def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
3422 def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
3423 def : Pat<(setle R16C:$rA, R16C:$rB),
3424 (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3425 def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
3426 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3428 def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
3429 def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
3430 ORr32, CGTIr32, CEQIr32>;
3431 def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
3432 def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
3433 def : Pat<(setle R32C:$rA, R32C:$rB),
3434 (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3435 def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
3436 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3438 def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
3439 def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
3440 def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
3441 def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
3442 def : Pat<(setule R8C:$rA, R8C:$rB),
3443 (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3444 def : Pat<(setule R8C:$rA, immU8:$imm),
3445 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3447 def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
3448 def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
3449 ORr16, CLGTHIr16, CEQHIr16>;
3450 def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
3451 def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
3452 CLGTHIr16, CEQHIr16>;
3453 def : Pat<(setule R16C:$rA, R16C:$rB),
3454 (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3455 def : Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
3456 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3458 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
3459 def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
3460 ORr32, CLGTIr32, CEQIr32>;
3461 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
3462 def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
3463 def : Pat<(setule R32C:$rA, R32C:$rB),
3464 (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3465 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
3466 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3468 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3469 // select conditional patterns:
3470 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3472 class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3473 SPUInstr selinstr, SPUInstr cmpare>:
3474 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3475 rclass:$rTrue, rclass:$rFalse),
3476 (selinstr rclass:$rTrue, rclass:$rFalse,
3477 (cmpare rclass:$rA, rclass:$rB))>;
3479 class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3480 PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
3481 Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
3482 rclass:$rTrue, rclass:$rFalse),
3483 (selinstr rclass:$rTrue, rclass:$rFalse,
3484 (cmpare rclass:$rA, immpred:$imm))>;
3486 def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
3487 def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
3488 def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
3489 def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
3490 def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
3491 def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
3493 def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
3494 def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
3495 def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
3496 def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
3497 def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
3498 def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
3500 def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
3501 def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
3502 def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
3503 def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
3504 def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
3505 def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
3507 class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3508 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3510 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3511 rclass:$rTrue, rclass:$rFalse),
3512 (selinstr rclass:$rFalse, rclass:$rTrue,
3513 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3514 (cmpOp2 rclass:$rA, rclass:$rB)))>;
3516 class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3518 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3520 Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
3521 rclass:$rTrue, rclass:$rFalse),
3522 (selinstr rclass:$rFalse, rclass:$rTrue,
3523 (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
3524 (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
3526 def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
3527 def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
3528 SELBr8, ORr8, CGTBIr8, CEQBIr8>;
3530 def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
3531 def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
3532 SELBr16, ORr16, CGTHIr16, CEQHIr16>;
3534 def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
3535 def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
3536 SELBr32, ORr32, CGTIr32, CEQIr32>;
3538 def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
3539 def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
3540 SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
3542 def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
3543 def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
3544 SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
3546 def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
3547 def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
3548 SELBr32, ORr32, CLGTIr32, CEQIr32>;
3550 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3553 // All calls clobber the non-callee-saved registers:
3554 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
3555 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
3556 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
3557 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
3558 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
3559 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
3560 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
3561 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
3562 // All of these instructions use $lr (aka $0)
3564 // Branch relative and set link: Used if we actually know that the target
3565 // is within [-32768, 32767] bytes of the target
3567 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
3568 "brsl\t$$lr, $func",
3569 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
3571 // Branch absolute and set link: Used if we actually know that the target
3572 // is an absolute address
3574 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
3575 "brasl\t$$lr, $func",
3576 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
3578 // Branch indirect and set link if external data. These instructions are not
3579 // actually generated, matched by an intrinsic:
3580 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
3581 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
3582 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
3583 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
3585 // Branch indirect and set link. This is the "X-form" address version of a
3588 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
3591 // Support calls to external symbols:
3592 def : Pat<(SPUcall (SPUpcrel texternalsym:$func, 0)),
3593 (BRSL texternalsym:$func)>;
3595 def : Pat<(SPUcall (SPUaform texternalsym:$func, 0)),
3596 (BRASL texternalsym:$func)>;
3598 // Unconditional branches:
3599 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
3600 let isBarrier = 1 in {
3602 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3606 // Unconditional, absolute address branch
3608 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3610 [/* no pattern */]>;
3614 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3617 // Conditional branches:
3618 class BRNZInst<dag IOL, list<dag> pattern>:
3619 RI16Form<0b010000100, (outs), IOL, "brnz\t$rCond,$dest",
3620 BranchResolv, pattern>;
3622 class BRNZRegInst<RegisterClass rclass>:
3623 BRNZInst<(ins rclass:$rCond, brtarget:$dest),
3624 [(brcond rclass:$rCond, bb:$dest)]>;
3626 class BRNZVecInst<ValueType vectype>:
3627 BRNZInst<(ins VECREG:$rCond, brtarget:$dest),
3628 [(brcond (vectype VECREG:$rCond), bb:$dest)]>;
3630 multiclass BranchNotZero {
3631 def v4i32 : BRNZVecInst<v4i32>;
3632 def r32 : BRNZRegInst<R32C>;
3635 defm BRNZ : BranchNotZero;
3637 class BRZInst<dag IOL, list<dag> pattern>:
3638 RI16Form<0b000000100, (outs), IOL, "brz\t$rT,$dest",
3639 BranchResolv, pattern>;
3641 class BRZRegInst<RegisterClass rclass>:
3642 BRZInst<(ins rclass:$rT, brtarget:$dest), [/* no pattern */]>;
3644 class BRZVecInst<ValueType vectype>:
3645 BRZInst<(ins VECREG:$rT, brtarget:$dest), [/* no pattern */]>;
3647 multiclass BranchZero {
3648 def v4i32: BRZVecInst<v4i32>;
3649 def r32: BRZRegInst<R32C>;
3652 defm BRZ: BranchZero;
3654 // Note: LLVM doesn't do branch conditional, indirect. Otherwise these would
3657 class BINZInst<dag IOL, list<dag> pattern>:
3658 BICondForm<0b10010100100, (outs), IOL, "binz\t$rA, $dest", pattern>;
3660 class BINZRegInst<RegisterClass rclass>:
3661 BINZInst<(ins rclass:$rA, brtarget:$dest),
3662 [(brcond rclass:$rA, R32C:$dest)]>;
3664 class BINZVecInst<ValueType vectype>:
3665 BINZInst<(ins VECREG:$rA, R32C:$dest),
3666 [(brcond (vectype VECREG:$rA), R32C:$dest)]>;
3668 multiclass BranchNotZeroIndirect {
3669 def v4i32: BINZVecInst<v4i32>;
3670 def r32: BINZRegInst<R32C>;
3673 defm BINZ: BranchNotZeroIndirect;
3675 class BIZInst<dag IOL, list<dag> pattern>:
3676 BICondForm<0b00010100100, (outs), IOL, "biz\t$rA, $func", pattern>;
3678 class BIZRegInst<RegisterClass rclass>:
3679 BIZInst<(ins rclass:$rA, R32C:$func), [/* no pattern */]>;
3681 class BIZVecInst<ValueType vectype>:
3682 BIZInst<(ins VECREG:$rA, R32C:$func), [/* no pattern */]>;
3684 multiclass BranchZeroIndirect {
3685 def v4i32: BIZVecInst<v4i32>;
3686 def r32: BIZRegInst<R32C>;
3689 defm BIZ: BranchZeroIndirect;
3692 class BRHNZInst<dag IOL, list<dag> pattern>:
3693 RI16Form<0b011000100, (outs), IOL, "brhnz\t$rCond,$dest", BranchResolv,
3696 class BRHNZRegInst<RegisterClass rclass>:
3697 BRHNZInst<(ins rclass:$rCond, brtarget:$dest),
3698 [(brcond rclass:$rCond, bb:$dest)]>;
3700 class BRHNZVecInst<ValueType vectype>:
3701 BRHNZInst<(ins VECREG:$rCond, brtarget:$dest), [/* no pattern */]>;
3703 multiclass BranchNotZeroHalfword {
3704 def v8i16: BRHNZVecInst<v8i16>;
3705 def r16: BRHNZRegInst<R16C>;
3708 defm BRHNZ: BranchNotZeroHalfword;
3710 class BRHZInst<dag IOL, list<dag> pattern>:
3711 RI16Form<0b001000100, (outs), IOL, "brhz\t$rT,$dest", BranchResolv,
3714 class BRHZRegInst<RegisterClass rclass>:
3715 BRHZInst<(ins rclass:$rT, brtarget:$dest), [/* no pattern */]>;
3717 class BRHZVecInst<ValueType vectype>:
3718 BRHZInst<(ins VECREG:$rT, brtarget:$dest), [/* no pattern */]>;
3720 multiclass BranchZeroHalfword {
3721 def v8i16: BRHZVecInst<v8i16>;
3722 def r16: BRHZRegInst<R16C>;
3725 defm BRHZ: BranchZeroHalfword;
3728 //===----------------------------------------------------------------------===//
3729 // setcc and brcond patterns:
3730 //===----------------------------------------------------------------------===//
3732 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3733 (BRHZr16 R16C:$rA, bb:$dest)>;
3734 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3735 (BRHNZr16 R16C:$rA, bb:$dest)>;
3737 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3738 (BRZr32 R32C:$rA, bb:$dest)>;
3739 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3740 (BRNZr32 R32C:$rA, bb:$dest)>;
3742 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3744 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3745 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3747 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3748 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3750 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3751 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3753 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3754 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3757 defm BRCONDeq : BranchCondEQ<seteq, BRHNZr16, BRNZr32>;
3758 defm BRCONDne : BranchCondEQ<setne, BRHZr16, BRZr32>;
3760 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3762 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3763 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3765 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3766 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3768 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3769 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3771 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3772 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3775 defm BRCONDugt : BranchCondLGT<setugt, BRHNZr16, BRNZr32>;
3776 defm BRCONDule : BranchCondLGT<setule, BRHZr16, BRZr32>;
3778 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3779 SPUInstr orinst32, SPUInstr brinst32>
3781 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3782 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3783 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3786 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3787 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3788 (CEQHr16 R16C:$rA, R16:$rB)),
3791 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3792 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3793 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3796 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3797 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3798 (CEQr32 R32C:$rA, R32C:$rB)),
3802 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZr16, ORr32, BRNZr32>;
3803 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZr16, ORr32, BRZr32>;
3805 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3807 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3808 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3810 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3811 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3813 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3814 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3816 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3817 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3820 defm BRCONDgt : BranchCondGT<setgt, BRHNZr16, BRNZr32>;
3821 defm BRCONDle : BranchCondGT<setle, BRHZr16, BRZr32>;
3823 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3824 SPUInstr orinst32, SPUInstr brinst32>
3826 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3827 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3828 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3831 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3832 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3833 (CEQHr16 R16C:$rA, R16:$rB)),
3836 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3837 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3838 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3841 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3842 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3843 (CEQr32 R32C:$rA, R32C:$rB)),
3847 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZr16, ORr32, BRNZr32>;
3848 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZr16, ORr32, BRZr32>;
3850 let isTerminator = 1, isBarrier = 1 in {
3851 let isReturn = 1 in {
3853 RETForm<"bi\t$$lr", [(retflag)]>;
3857 //===----------------------------------------------------------------------===//
3858 // Single precision floating point instructions
3859 //===----------------------------------------------------------------------===//
3861 class FAInst<dag OOL, dag IOL, list<dag> pattern>:
3862 RRForm<0b01011000100, OOL, IOL, "fa\t$rT, $rA, $rB",
3865 class FAVecInst<ValueType vectype>:
3866 FAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3867 [(set (vectype VECREG:$rT),
3868 (fadd (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
3872 def v4f32: FAVecInst<v4f32>;
3873 def f32: FAInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3874 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3879 class FSInst<dag OOL, dag IOL, list<dag> pattern>:
3880 RRForm<0b01011000100, OOL, IOL, "fs\t$rT, $rA, $rB",
3883 class FSVecInst<ValueType vectype>:
3884 FSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3885 [(set (vectype VECREG:$rT),
3886 (fsub (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
3890 def v4f32: FSVecInst<v4f32>;
3891 def f32: FSInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3892 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3897 // Floating point reciprocal estimate
3899 class FRESTInst<dag OOL, dag IOL>:
3900 RRForm_1<0b00110111000, OOL, IOL,
3901 "frest\t$rT, $rA", SPrecFP,
3902 [/* no pattern */]>;
3905 FRESTInst<(outs VECREG:$rT), (ins VECREG:$rA)>;
3908 FRESTInst<(outs R32FP:$rT), (ins R32FP:$rA)>;
3910 // Floating point interpolate (used in conjunction with reciprocal estimate)
3912 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3913 "fi\t$rT, $rA, $rB", SPrecFP,
3914 [/* no pattern */]>;
3917 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3918 "fi\t$rT, $rA, $rB", SPrecFP,
3919 [/* no pattern */]>;
3921 //--------------------------------------------------------------------------
3922 // Basic single precision floating point comparisons:
3924 // Note: There is no support on SPU for single precision NaN. Consequently,
3925 // ordered and unordered comparisons are the same.
3926 //--------------------------------------------------------------------------
3929 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3930 "fceq\t$rT, $rA, $rB", SPrecFP,
3931 [(set R32C:$rT, (setueq R32FP:$rA, R32FP:$rB))]>;
3933 def : Pat<(setoeq R32FP:$rA, R32FP:$rB),
3934 (FCEQf32 R32FP:$rA, R32FP:$rB)>;
3937 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3938 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3939 [(set R32C:$rT, (setueq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3941 def : Pat<(setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)),
3942 (FCMEQf32 R32FP:$rA, R32FP:$rB)>;
3945 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3946 "fcgt\t$rT, $rA, $rB", SPrecFP,
3947 [(set R32C:$rT, (setugt R32FP:$rA, R32FP:$rB))]>;
3949 def : Pat<(setugt R32FP:$rA, R32FP:$rB),
3950 (FCGTf32 R32FP:$rA, R32FP:$rB)>;
3953 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3954 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3955 [(set R32C:$rT, (setugt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3957 def : Pat<(setugt (fabs R32FP:$rA), (fabs R32FP:$rB)),
3958 (FCMGTf32 R32FP:$rA, R32FP:$rB)>;
3960 //--------------------------------------------------------------------------
3961 // Single precision floating point comparisons and SETCC equivalents:
3962 //--------------------------------------------------------------------------
3964 def : SETCCNegCondReg<setune, R32FP, i32, XORIr32, FCEQf32>;
3965 def : SETCCNegCondReg<setone, R32FP, i32, XORIr32, FCEQf32>;
3967 def : SETCCBinOpReg<setuge, R32FP, ORr32, FCGTf32, FCEQf32>;
3968 def : SETCCBinOpReg<setoge, R32FP, ORr32, FCGTf32, FCEQf32>;
3970 def : SETCCBinOpReg<setult, R32FP, NORr32, FCGTf32, FCEQf32>;
3971 def : SETCCBinOpReg<setolt, R32FP, NORr32, FCGTf32, FCEQf32>;
3973 def : Pat<(setule R32FP:$rA, R32FP:$rB),
3974 (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
3975 def : Pat<(setole R32FP:$rA, R32FP:$rB),
3976 (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
3978 // FP Status and Control Register Write
3979 // Why isn't rT a don't care in the ISA?
3980 // Should we create a special RRForm_3 for this guy and zero out the rT?
3982 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3983 "fscrwr\t$rA", SPrecFP,
3984 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3986 // FP Status and Control Register Read
3988 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3989 "fscrrd\t$rT", SPrecFP,
3990 [/* This instruction requires an intrinsic */]>;
3992 // llvm instruction space
3993 // How do these map onto cell instructions?
3995 // frest rC rB # c = 1/b (both lines)
3997 // fm rD rA rC # d = a * 1/b
3998 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3999 // fma rB rB rC rD # b = b * c + d
4000 // = -(d *b -a) * c + d
4001 // = a * c - c ( a *b *c - a)
4006 // These llvm instructions will actually map to library calls.
4007 // All that's needed, then, is to check that the appropriate library is
4008 // imported and do a brsl to the proper function name.
4009 // frem # fmod(x, y): x - (x/y) * y
4010 // (Note: fmod(double, double), fmodf(float,float)
4014 // Unimplemented SPU instruction space
4015 // floating reciprocal absolute square root estimate (frsqest)
4017 // The following are probably just intrinsics
4018 // status and control register write
4019 // status and control register read
4021 //--------------------------------------
4022 // Floating point multiply instructions
4023 //--------------------------------------
4026 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
4027 "fm\t$rT, $rA, $rB", SPrecFP,
4028 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
4029 (v4f32 VECREG:$rB)))]>;
4032 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
4033 "fm\t$rT, $rA, $rB", SPrecFP,
4034 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
4036 // Floating point multiply and add
4037 // e.g. d = c + (a * b)
4039 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4040 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
4041 [(set (v4f32 VECREG:$rT),
4042 (fadd (v4f32 VECREG:$rC),
4043 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
4046 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
4047 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
4048 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
4050 // FP multiply and subtract
4051 // Subtracts value in rC from product
4054 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4055 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
4056 [(set (v4f32 VECREG:$rT),
4057 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
4058 (v4f32 VECREG:$rC)))]>;
4061 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
4062 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
4064 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
4066 // Floating Negative Mulitply and Subtract
4067 // Subtracts product from value in rC
4068 // res = fneg(fms a b c)
4071 // NOTE: subtraction order
4075 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
4076 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
4077 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
4080 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4081 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
4082 [(set (v4f32 VECREG:$rT),
4083 (fsub (v4f32 VECREG:$rC),
4084 (fmul (v4f32 VECREG:$rA),
4085 (v4f32 VECREG:$rB))))]>;
4087 //--------------------------------------
4088 // Floating Point Conversions
4089 // Signed conversions:
4091 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
4092 "csflt\t$rT, $rA, 0", SPrecFP,
4093 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
4095 // Convert signed integer to floating point
4097 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
4098 "csflt\t$rT, $rA, 0", SPrecFP,
4099 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
4101 // Convert unsigned into to float
4103 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
4104 "cuflt\t$rT, $rA, 0", SPrecFP,
4105 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
4108 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
4109 "cuflt\t$rT, $rA, 0", SPrecFP,
4110 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
4112 // Convert float to unsigned int
4113 // Assume that scale = 0
4116 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
4117 "cfltu\t$rT, $rA, 0", SPrecFP,
4118 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
4121 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
4122 "cfltu\t$rT, $rA, 0", SPrecFP,
4123 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
4125 // Convert float to signed int
4126 // Assume that scale = 0
4129 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
4130 "cflts\t$rT, $rA, 0", SPrecFP,
4131 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
4134 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
4135 "cflts\t$rT, $rA, 0", SPrecFP,
4136 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
4138 //===----------------------------------------------------------------------==//
4139 // Single<->Double precision conversions
4140 //===----------------------------------------------------------------------==//
4142 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
4143 // v4f32, output is v2f64--which goes in the name?)
4145 // Floating point extend single to double
4146 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
4147 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
4150 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
4151 "fesd\t$rT, $rA", SPrecFP,
4152 [/*(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))*/]>;
4155 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
4156 "fesd\t$rT, $rA", SPrecFP,
4157 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
4159 // Floating point round double to single
4161 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
4162 // "frds\t$rT, $rA,", SPrecFP,
4163 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
4166 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
4167 "frds\t$rT, $rA", SPrecFP,
4168 [(set R32FP:$rT, (fround R64FP:$rA))]>;
4170 //ToDo include anyextend?
4172 //===----------------------------------------------------------------------==//
4173 // Double precision floating point instructions
4174 //===----------------------------------------------------------------------==//
4176 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
4177 "dfa\t$rT, $rA, $rB", DPrecFP,
4178 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
4181 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
4182 "dfa\t$rT, $rA, $rB", DPrecFP,
4183 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
4186 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
4187 "dfs\t$rT, $rA, $rB", DPrecFP,
4188 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
4191 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
4192 "dfs\t$rT, $rA, $rB", DPrecFP,
4193 [(set (v2f64 VECREG:$rT),
4194 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
4197 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
4198 "dfm\t$rT, $rA, $rB", DPrecFP,
4199 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
4202 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
4203 "dfm\t$rT, $rA, $rB", DPrecFP,
4204 [(set (v2f64 VECREG:$rT),
4205 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
4208 RRForm<0b00111010110, (outs R64FP:$rT),
4209 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
4210 "dfma\t$rT, $rA, $rB", DPrecFP,
4211 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
4212 RegConstraint<"$rC = $rT">,
4216 RRForm<0b00111010110, (outs VECREG:$rT),
4217 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4218 "dfma\t$rT, $rA, $rB", DPrecFP,
4219 [(set (v2f64 VECREG:$rT),
4220 (fadd (v2f64 VECREG:$rC),
4221 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
4222 RegConstraint<"$rC = $rT">,
4226 RRForm<0b10111010110, (outs R64FP:$rT),
4227 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
4228 "dfms\t$rT, $rA, $rB", DPrecFP,
4229 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
4230 RegConstraint<"$rC = $rT">,
4234 RRForm<0b10111010110, (outs VECREG:$rT),
4235 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4236 "dfms\t$rT, $rA, $rB", DPrecFP,
4237 [(set (v2f64 VECREG:$rT),
4238 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
4239 (v2f64 VECREG:$rC)))]>;
4241 // DFNMS: - (a * b - c)
4242 // - (a * b) + c => c - (a * b)
4244 class DFNMSInst<dag OOL, dag IOL, list<dag> pattern>:
4245 RRForm<0b01111010110, OOL, IOL, "dfnms\t$rT, $rA, $rB",
4247 RegConstraint<"$rC = $rT">,
4250 class DFNMSVecInst<list<dag> pattern>:
4251 DFNMSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4254 class DFNMSRegInst<list<dag> pattern>:
4255 DFNMSInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
4258 multiclass DFMultiplySubtract
4260 def v2f64 : DFNMSVecInst<[(set (v2f64 VECREG:$rT),
4261 (fsub (v2f64 VECREG:$rC),
4262 (fmul (v2f64 VECREG:$rA),
4263 (v2f64 VECREG:$rB))))]>;
4265 def f64 : DFNMSRegInst<[(set R64FP:$rT,
4267 (fmul R64FP:$rA, R64FP:$rB)))]>;
4270 defm DFNMS : DFMultiplySubtract;
4275 RRForm<0b11111010110, (outs R64FP:$rT),
4276 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
4277 "dfnma\t$rT, $rA, $rB", DPrecFP,
4278 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
4279 RegConstraint<"$rC = $rT">,
4283 RRForm<0b11111010110, (outs VECREG:$rT),
4284 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4285 "dfnma\t$rT, $rA, $rB", DPrecFP,
4286 [(set (v2f64 VECREG:$rT),
4287 (fneg (fadd (v2f64 VECREG:$rC),
4288 (fmul (v2f64 VECREG:$rA),
4289 (v2f64 VECREG:$rB)))))]>,
4290 RegConstraint<"$rC = $rT">,
4293 //===----------------------------------------------------------------------==//
4294 // Floating point negation and absolute value
4295 //===----------------------------------------------------------------------==//
4297 def : Pat<(fneg (v4f32 VECREG:$rA)),
4298 (XORfnegvec (v4f32 VECREG:$rA),
4299 (v4f32 (ILHUv4i32 0x8000)))>;
4301 def : Pat<(fneg R32FP:$rA),
4302 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
4304 // Floating point absolute value
4305 // Note: f64 fabs is custom-selected.
4307 def : Pat<(fabs R32FP:$rA),
4308 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
4310 def : Pat<(fabs (v4f32 VECREG:$rA)),
4311 (ANDfabsvec (v4f32 VECREG:$rA),
4312 (IOHLv4i32 (ILHUv4i32 0x7fff), 0xffff))>;
4314 //===----------------------------------------------------------------------===//
4315 // Hint for branch instructions:
4316 //===----------------------------------------------------------------------===//
4318 /* def HBR : SPUInstr<(outs), (ins), "hbr\t" */
4320 //===----------------------------------------------------------------------===//
4321 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
4322 // in the odd pipeline)
4323 //===----------------------------------------------------------------------===//
4325 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
4328 let Inst{0-10} = 0b10000000010;
4329 let Inst{11-17} = 0;
4330 let Inst{18-24} = 0;
4331 let Inst{25-31} = 0;
4334 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
4337 let Inst{0-10} = 0b10000000000;
4338 let Inst{11-17} = 0;
4339 let Inst{18-24} = 0;
4340 let Inst{25-31} = 0;
4343 //===----------------------------------------------------------------------===//
4344 // Bit conversions (type conversions between vector/packed types)
4345 // NOTE: Promotions are handled using the XS* instructions.
4346 //===----------------------------------------------------------------------===//
4347 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
4348 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
4349 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
4350 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
4351 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
4353 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
4354 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
4355 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
4356 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
4357 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
4359 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
4360 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
4361 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
4362 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
4363 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
4365 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
4366 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
4367 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
4368 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
4369 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
4371 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
4372 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
4373 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
4374 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
4375 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
4377 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
4378 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
4379 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
4380 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
4381 def : Pat<(v2f64 (bitconvert (v4f32 VECREG:$src))), (v2f64 VECREG:$src)>;
4383 def : Pat<(i128 (bitconvert (v16i8 VECREG:$src))),
4384 (ORi128_vec VECREG:$src)>;
4385 def : Pat<(i128 (bitconvert (v8i16 VECREG:$src))),
4386 (ORi128_vec VECREG:$src)>;
4387 def : Pat<(i128 (bitconvert (v4i32 VECREG:$src))),
4388 (ORi128_vec VECREG:$src)>;
4389 def : Pat<(i128 (bitconvert (v2i64 VECREG:$src))),
4390 (ORi128_vec VECREG:$src)>;
4391 def : Pat<(i128 (bitconvert (v4f32 VECREG:$src))),
4392 (ORi128_vec VECREG:$src)>;
4393 def : Pat<(i128 (bitconvert (v2f64 VECREG:$src))),
4394 (ORi128_vec VECREG:$src)>;
4396 def : Pat<(v16i8 (bitconvert (i128 GPRC:$src))),
4397 (v16i8 (ORvec_i128 GPRC:$src))>;
4398 def : Pat<(v8i16 (bitconvert (i128 GPRC:$src))),
4399 (v8i16 (ORvec_i128 GPRC:$src))>;
4400 def : Pat<(v4i32 (bitconvert (i128 GPRC:$src))),
4401 (v4i32 (ORvec_i128 GPRC:$src))>;
4402 def : Pat<(v2i64 (bitconvert (i128 GPRC:$src))),
4403 (v2i64 (ORvec_i128 GPRC:$src))>;
4404 def : Pat<(v4f32 (bitconvert (i128 GPRC:$src))),
4405 (v4f32 (ORvec_i128 GPRC:$src))>;
4406 def : Pat<(v2f64 (bitconvert (i128 GPRC:$src))),
4407 (v2f64 (ORvec_i128 GPRC:$src))>;
4409 //===----------------------------------------------------------------------===//
4410 // Instruction patterns:
4411 //===----------------------------------------------------------------------===//
4413 // General 32-bit constants:
4414 def : Pat<(i32 imm:$imm),
4415 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
4417 // Single precision float constants:
4418 def : Pat<(f32 fpimm:$imm),
4419 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
4421 // General constant 32-bit vectors
4422 def : Pat<(v4i32 v4i32Imm:$imm),
4423 (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
4424 (LO16_vec v4i32Imm:$imm))>;
4427 def : Pat<(i8 imm:$imm),
4430 //===----------------------------------------------------------------------===//
4431 // Zero/Any/Sign extensions
4432 //===----------------------------------------------------------------------===//
4434 // sext 8->32: Sign extend bytes to words
4435 def : Pat<(sext_inreg R32C:$rSrc, i8),
4436 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
4438 def : Pat<(i32 (sext R8C:$rSrc)),
4439 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
4441 // sext 8->64: Sign extend bytes to double word
4442 def : Pat<(sext_inreg R64C:$rSrc, i8),
4443 (XSWDr64_inreg (XSHWr64 (XSBHr64 R64C:$rSrc)))>;
4445 def : Pat<(i64 (sext R8C:$rSrc)),
4446 (XSWDr64 (XSHWr16 (XSBHr8 R8C:$rSrc)))>;
4448 // zext 8->16: Zero extend bytes to halfwords
4449 def : Pat<(i16 (zext R8C:$rSrc)),
4450 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
4452 // zext 8->32: Zero extend bytes to words
4453 def : Pat<(i32 (zext R8C:$rSrc)),
4454 (ANDIi8i32 R8C:$rSrc, 0xff)>;
4456 // zext 8->64: Zero extend bytes to double words
4457 def : Pat<(i64 (zext R8C:$rSrc)),
4458 (ORi64_v2i64 (SELBv4i32 (ROTQMBYv4i32
4459 (ORv4i32_i32 (ANDIi8i32 R8C:$rSrc, 0xff)),
4462 (FSMBIv4i32 0x0f0f)))>;
4464 // anyext 8->16: Extend 8->16 bits, irrespective of sign, preserves high bits
4465 def : Pat<(i16 (anyext R8C:$rSrc)),
4466 (ORHIi8i16 R8C:$rSrc, 0)>;
4468 // anyext 8->32: Extend 8->32 bits, irrespective of sign, preserves high bits
4469 def : Pat<(i32 (anyext R8C:$rSrc)),
4470 (ORIi8i32 R8C:$rSrc, 0)>;
4472 // sext 16->64: Sign extend halfword to double word
4473 def : Pat<(sext_inreg R64C:$rSrc, i16),
4474 (XSWDr64_inreg (XSHWr64 R64C:$rSrc))>;
4476 def : Pat<(sext R16C:$rSrc),
4477 (XSWDr64 (XSHWr16 R16C:$rSrc))>;
4479 // zext 16->32: Zero extend halfwords to words
4480 def : Pat<(i32 (zext R16C:$rSrc)),
4481 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
4483 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
4484 (ANDIi16i32 R16C:$rSrc, 0xf)>;
4486 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
4487 (ANDIi16i32 R16C:$rSrc, 0xff)>;
4489 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
4490 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
4492 // anyext 16->32: Extend 16->32 bits, irrespective of sign
4493 def : Pat<(i32 (anyext R16C:$rSrc)),
4494 (ORIi16i32 R16C:$rSrc, 0)>;
4496 //===----------------------------------------------------------------------===//
4498 // These truncates are for the SPU's supported types (i8, i16, i32). i64 and
4499 // above are custom lowered.
4500 //===----------------------------------------------------------------------===//
4502 def : Pat<(i8 (trunc GPRC:$src)),
4504 (SHUFBgprc GPRC:$src, GPRC:$src,
4505 (IOHLv4i32 (ILHUv4i32 0x0f0f), 0x0f0f)))>;
4507 def : Pat<(i8 (trunc R64C:$src)),
4510 (ORv2i64_i64 R64C:$src),
4511 (ORv2i64_i64 R64C:$src),
4512 (IOHLv4i32 (ILHUv4i32 0x0707), 0x0707)))>;
4514 def : Pat<(i8 (trunc R32C:$src)),
4517 (ORv4i32_i32 R32C:$src),
4518 (ORv4i32_i32 R32C:$src),
4519 (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)))>;
4521 def : Pat<(i8 (trunc R16C:$src)),
4524 (ORv8i16_i16 R16C:$src),
4525 (ORv8i16_i16 R16C:$src),
4526 (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)))>;
4528 def : Pat<(i16 (trunc GPRC:$src)),
4530 (SHUFBgprc GPRC:$src, GPRC:$src,
4531 (IOHLv4i32 (ILHUv4i32 0x0e0f), 0x0e0f)))>;
4533 def : Pat<(i16 (trunc R64C:$src)),
4536 (ORv2i64_i64 R64C:$src),
4537 (ORv2i64_i64 R64C:$src),
4538 (IOHLv4i32 (ILHUv4i32 0x0607), 0x0607)))>;
4540 def : Pat<(i16 (trunc R32C:$src)),
4543 (ORv4i32_i32 R32C:$src),
4544 (ORv4i32_i32 R32C:$src),
4545 (IOHLv4i32 (ILHUv4i32 0x0203), 0x0203)))>;
4547 def : Pat<(i32 (trunc GPRC:$src)),
4549 (SHUFBgprc GPRC:$src, GPRC:$src,
4550 (IOHLv4i32 (ILHUv4i32 0x0c0d), 0x0e0f)))>;
4552 def : Pat<(i32 (trunc R64C:$src)),
4555 (ORv2i64_i64 R64C:$src),
4556 (ORv2i64_i64 R64C:$src),
4557 (IOHLv4i32 (ILHUv4i32 0x0405), 0x0607)))>;
4559 //===----------------------------------------------------------------------===//
4560 // Address generation: SPU, like PPC, has to split addresses into high and
4561 // low parts in order to load them into a register.
4562 //===----------------------------------------------------------------------===//
4564 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
4565 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
4566 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
4567 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
4569 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
4570 (SPUlo tglobaladdr:$in, 0)),
4571 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4573 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
4574 (SPUlo texternalsym:$in, 0)),
4575 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4577 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
4578 (SPUlo tjumptable:$in, 0)),
4579 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4581 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
4582 (SPUlo tconstpool:$in, 0)),
4583 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4585 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
4586 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4588 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
4589 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4591 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
4592 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4594 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
4595 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4598 include "CellSDKIntrinsics.td"
4599 // Various math operator instruction sequences
4600 include "SPUMathInstr.td"
4601 // 64-bit "instructions"/support
4602 include "SPU64InstrInfo.td"
4603 // 128-bit "instructions"/support
4604 include "SPU128InstrInfo.td"