1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start imm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end imm:$amt)]>;
33 //===----------------------------------------------------------------------===//
34 // DWARF debugging Pseudo Instructions
35 //===----------------------------------------------------------------------===//
37 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
38 "${:comment} .loc $file, $line, $col",
39 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
42 //===----------------------------------------------------------------------===//
44 // NB: The ordering is actually important, since the instruction selection
45 // will try each of the instructions in sequence, i.e., the D-form first with
46 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
47 // finally the X-form with the register-register.
48 //===----------------------------------------------------------------------===//
50 let isSimpleLoad = 1 in {
51 class LoadDFormVec<ValueType vectype>
52 : RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
55 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
58 class LoadDForm<RegisterClass rclass>
59 : RI10Form<0b00101100, (outs rclass:$rT), (ins memri10:$src),
62 [(set rclass:$rT, (load dform_addr:$src))]>
67 def v16i8: LoadDFormVec<v16i8>;
68 def v8i16: LoadDFormVec<v8i16>;
69 def v4i32: LoadDFormVec<v4i32>;
70 def v2i64: LoadDFormVec<v2i64>;
71 def v4f32: LoadDFormVec<v4f32>;
72 def v2f64: LoadDFormVec<v2f64>;
74 def r128: LoadDForm<GPRC>;
75 def r64: LoadDForm<R64C>;
76 def r32: LoadDForm<R32C>;
77 def f32: LoadDForm<R32FP>;
78 def f64: LoadDForm<R64FP>;
79 def r16: LoadDForm<R16C>;
80 def r8: LoadDForm<R8C>;
83 class LoadAFormVec<ValueType vectype>
84 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
87 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
90 class LoadAForm<RegisterClass rclass>
91 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
94 [(set rclass:$rT, (load aform_addr:$src))]>
99 def v16i8: LoadAFormVec<v16i8>;
100 def v8i16: LoadAFormVec<v8i16>;
101 def v4i32: LoadAFormVec<v4i32>;
102 def v2i64: LoadAFormVec<v2i64>;
103 def v4f32: LoadAFormVec<v4f32>;
104 def v2f64: LoadAFormVec<v2f64>;
106 def r128: LoadAForm<GPRC>;
107 def r64: LoadAForm<R64C>;
108 def r32: LoadAForm<R32C>;
109 def f32: LoadAForm<R32FP>;
110 def f64: LoadAForm<R64FP>;
111 def r16: LoadAForm<R16C>;
112 def r8: LoadAForm<R8C>;
115 class LoadXFormVec<ValueType vectype>
116 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
119 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
122 class LoadXForm<RegisterClass rclass>
123 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
126 [(set rclass:$rT, (load xform_addr:$src))]>
129 multiclass LoadXForms
131 def v16i8: LoadXFormVec<v16i8>;
132 def v8i16: LoadXFormVec<v8i16>;
133 def v4i32: LoadXFormVec<v4i32>;
134 def v2i64: LoadXFormVec<v2i64>;
135 def v4f32: LoadXFormVec<v4f32>;
136 def v2f64: LoadXFormVec<v2f64>;
138 def r128: LoadXForm<GPRC>;
139 def r64: LoadXForm<R64C>;
140 def r32: LoadXForm<R32C>;
141 def f32: LoadXForm<R32FP>;
142 def f64: LoadXForm<R64FP>;
143 def r16: LoadXForm<R16C>;
144 def r8: LoadXForm<R8C>;
147 defm LQA : LoadAForms;
148 defm LQD : LoadDForms;
149 defm LQX : LoadXForms;
151 /* Load quadword, PC relative: Not much use at this point in time.
152 Might be of use later for relocatable code. It's effectively the
153 same as LQA, but uses PC-relative addressing.
154 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
155 "lqr\t$rT, $disp", LoadStore,
156 [(set VECREG:$rT, (load iaddr:$disp))]>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
163 class StoreDFormVec<ValueType vectype>
164 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
167 [(store (vectype VECREG:$rT), dform_addr:$src)]>
170 class StoreDForm<RegisterClass rclass>
171 : RI10Form<0b00100100, (outs), (ins rclass:$rT, memri10:$src),
174 [(store rclass:$rT, dform_addr:$src)]>
177 multiclass StoreDForms
179 def v16i8: StoreDFormVec<v16i8>;
180 def v8i16: StoreDFormVec<v8i16>;
181 def v4i32: StoreDFormVec<v4i32>;
182 def v2i64: StoreDFormVec<v2i64>;
183 def v4f32: StoreDFormVec<v4f32>;
184 def v2f64: StoreDFormVec<v2f64>;
186 def r128: StoreDForm<GPRC>;
187 def r64: StoreDForm<R64C>;
188 def r32: StoreDForm<R32C>;
189 def f32: StoreDForm<R32FP>;
190 def f64: StoreDForm<R64FP>;
191 def r16: StoreDForm<R16C>;
192 def r8: StoreDForm<R8C>;
195 class StoreAFormVec<ValueType vectype>
196 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
199 [(store (vectype VECREG:$rT), aform_addr:$src)]>;
201 class StoreAForm<RegisterClass rclass>
202 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
205 [(store rclass:$rT, aform_addr:$src)]>;
207 multiclass StoreAForms
209 def v16i8: StoreAFormVec<v16i8>;
210 def v8i16: StoreAFormVec<v8i16>;
211 def v4i32: StoreAFormVec<v4i32>;
212 def v2i64: StoreAFormVec<v2i64>;
213 def v4f32: StoreAFormVec<v4f32>;
214 def v2f64: StoreAFormVec<v2f64>;
216 def r128: StoreAForm<GPRC>;
217 def r64: StoreAForm<R64C>;
218 def r32: StoreAForm<R32C>;
219 def f32: StoreAForm<R32FP>;
220 def f64: StoreAForm<R64FP>;
221 def r16: StoreAForm<R16C>;
222 def r8: StoreAForm<R8C>;
225 class StoreXFormVec<ValueType vectype>
226 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
229 [(store (vectype VECREG:$rT), xform_addr:$src)]>
232 class StoreXForm<RegisterClass rclass>
233 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
236 [(store rclass:$rT, xform_addr:$src)]>
239 multiclass StoreXForms
241 def v16i8: StoreXFormVec<v16i8>;
242 def v8i16: StoreXFormVec<v8i16>;
243 def v4i32: StoreXFormVec<v4i32>;
244 def v2i64: StoreXFormVec<v2i64>;
245 def v4f32: StoreXFormVec<v4f32>;
246 def v2f64: StoreXFormVec<v2f64>;
248 def r128: StoreXForm<GPRC>;
249 def r64: StoreXForm<R64C>;
250 def r32: StoreXForm<R32C>;
251 def f32: StoreXForm<R32FP>;
252 def f64: StoreXForm<R64FP>;
253 def r16: StoreXForm<R16C>;
254 def r8: StoreXForm<R8C>;
257 defm STQD : StoreDForms;
258 defm STQA : StoreAForms;
259 defm STQX : StoreXForms;
261 /* Store quadword, PC relative: Not much use at this point in time. Might
262 be useful for relocatable code.
263 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
264 "stqr\t$rT, $disp", LoadStore,
265 [(store VECREG:$rT, iaddr:$disp)]>;
268 //===----------------------------------------------------------------------===//
269 // Generate Controls for Insertion:
270 //===----------------------------------------------------------------------===//
273 RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
274 "cbd\t$rT, $src", ShuffleOp,
275 [(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
277 def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
278 "cbx\t$rT, $src", ShuffleOp,
279 [(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
281 def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
282 "chd\t$rT, $src", ShuffleOp,
283 [(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
285 def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
286 "chx\t$rT, $src", ShuffleOp,
287 [(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
289 def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
290 "cwd\t$rT, $src", ShuffleOp,
291 [(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
293 def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
294 "cwx\t$rT, $src", ShuffleOp,
295 [(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
297 def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
298 "cdd\t$rT, $src", ShuffleOp,
299 [(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
301 def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
302 "cdx\t$rT, $src", ShuffleOp,
303 [(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
305 //===----------------------------------------------------------------------===//
306 // Constant formation:
307 //===----------------------------------------------------------------------===//
310 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
311 "ilh\t$rT, $val", ImmLoad,
312 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
315 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
316 "ilh\t$rT, $val", ImmLoad,
317 [(set R16C:$rT, immSExt16:$val)]>;
319 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
320 // the right constant")
322 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
323 "ilh\t$rT, $val", ImmLoad,
324 [(set R8C:$rT, immSExt8:$val)]>;
326 // IL does sign extension!
328 class ILInst<dag OOL, dag IOL, list<dag> pattern>:
329 RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val",
332 class ILVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
333 ILInst<(outs VECREG:$rT), (ins immtype:$val),
334 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
336 class ILRegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
337 ILInst<(outs rclass:$rT), (ins immtype:$val),
338 [(set rclass:$rT, xform:$val)]>;
340 multiclass ImmediateLoad
342 def v2i64: ILVecInst<v2i64, s16imm_i64, v2i64SExt16Imm>;
343 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
345 // TODO: Need v2f64, v4f32
347 def r64: ILRegInst<R64C, s16imm_i64, immSExt16>;
348 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
349 def f32: ILRegInst<R32FP, s16imm_f32, fpimmSExt16>;
350 def f64: ILRegInst<R64FP, s16imm_f64, fpimmSExt16>;
353 defm IL : ImmediateLoad;
355 class ILHUInst<dag OOL, dag IOL, list<dag> pattern>:
356 RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val",
359 class ILHUVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
360 ILHUInst<(outs VECREG:$rT), (ins immtype:$val),
361 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
363 class ILHURegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
364 ILHUInst<(outs rclass:$rT), (ins immtype:$val),
365 [(set rclass:$rT, xform:$val)]>;
367 multiclass ImmLoadHalfwordUpper
369 def v2i64: ILHUVecInst<v2i64, u16imm_i64, immILHUvec_i64>;
370 def v4i32: ILHUVecInst<v4i32, u16imm, immILHUvec>;
372 def r64: ILHURegInst<R64C, u16imm_i64, hi16>;
373 def r32: ILHURegInst<R32C, u16imm, hi16>;
375 // Loads the high portion of an address
376 def hi: ILHURegInst<R32C, symbolHi, hi16>;
378 // Used in custom lowering constant SFP loads:
379 def f32: ILHURegInst<R32FP, f16imm, hi16_f32>;
382 defm ILHU : ImmLoadHalfwordUpper;
384 // Immediate load address (can also be used to load 18-bit unsigned constants,
385 // see the zext 16->32 pattern)
387 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
388 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
391 class ILAVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
392 ILAInst<(outs VECREG:$rT), (ins immtype:$val),
393 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
395 class ILARegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
396 ILAInst<(outs rclass:$rT), (ins immtype:$val),
397 [(set rclass:$rT, xform:$val)]>;
399 multiclass ImmLoadAddress
401 def v2i64: ILAVecInst<v2i64, u18imm, v2i64Uns18Imm>;
402 def v4i32: ILAVecInst<v4i32, u18imm, v4i32Uns18Imm>;
404 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
405 def r32: ILARegInst<R32C, u18imm, imm18>;
406 def f32: ILARegInst<R32FP, f18imm, fpimm18>;
407 def f64: ILARegInst<R64FP, f18imm_f64, fpimm18>;
409 def lo: ILARegInst<R32C, symbolLo, imm18>;
411 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
415 defm ILA : ImmLoadAddress;
417 // Immediate OR, Halfword Lower: The "other" part of loading large constants
418 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
419 // Note that these are really two operand instructions, but they're encoded
420 // as three operands with the first two arguments tied-to each other.
422 class IOHLInst<dag OOL, dag IOL, list<dag> pattern>:
423 RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val",
425 RegConstraint<"$rS = $rT">,
428 class IOHLVecInst<ValueType vectype, Operand immtype /* , PatLeaf xform */>:
429 IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val),
432 class IOHLRegInst<RegisterClass rclass, Operand immtype /* , PatLeaf xform */>:
433 IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val),
436 multiclass ImmOrHalfwordLower
438 def v2i64: IOHLVecInst<v2i64, u16imm_i64>;
439 def v4i32: IOHLVecInst<v4i32, u16imm>;
441 def r32: IOHLRegInst<R32C, i32imm>;
442 def f32: IOHLRegInst<R32FP, f32imm>;
444 def lo: IOHLRegInst<R32C, symbolLo>;
447 defm IOHL: ImmOrHalfwordLower;
449 // Form select mask for bytes using immediate, used in conjunction with the
452 class FSMBIVec<ValueType vectype>:
453 RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
456 [(set (vectype VECREG:$rT), (SPUfsmbi (i32 immU16:$val)))]>;
458 multiclass FormSelectMaskBytesImm
460 def v16i8: FSMBIVec<v16i8>;
461 def v8i16: FSMBIVec<v8i16>;
462 def v4i32: FSMBIVec<v4i32>;
463 def v2i64: FSMBIVec<v2i64>;
466 defm FSMBI : FormSelectMaskBytesImm;
468 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
470 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
471 "fsmb\t$rT, $rA", SelectOp,
472 [(set (v16i8 VECREG:$rT), (SPUfsmbi R16C:$rA))]>;
474 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
475 // only 8-bits wide (even though it's input as 16-bits here)
477 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
478 "fsmh\t$rT, $rA", SelectOp,
479 [(set (v8i16 VECREG:$rT), (SPUfsmbi R16C:$rA))]>;
481 // fsm: Form select mask for words. Like the other fsm* instructions,
482 // only the lower 4 bits of $rA are significant.
484 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA),
485 "fsm\t$rT, $rA", SelectOp,
486 [(set (v4i32 VECREG:$rT), (SPUfsmbi R16C:$rA))]>;
488 //===----------------------------------------------------------------------===//
489 // Integer and Logical Operations:
490 //===----------------------------------------------------------------------===//
493 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
494 "ah\t$rT, $rA, $rB", IntegerOp,
495 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
497 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
498 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
501 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
502 "ah\t$rT, $rA, $rB", IntegerOp,
503 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
506 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
507 "ahi\t$rT, $rA, $val", IntegerOp,
508 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
509 v8i16SExt10Imm:$val))]>;
512 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
513 "ahi\t$rT, $rA, $val", IntegerOp,
514 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
517 RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
518 "a\t$rT, $rA, $rB", IntegerOp,
519 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
521 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
522 (Avec VECREG:$rA, VECREG:$rB)>;
525 RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
526 "a\t$rT, $rA, $rB", IntegerOp,
527 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
530 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
531 "a\t$rT, $rA, $rB", IntegerOp,
532 [(set R8C:$rT, (add R8C:$rA, R8C:$rB))]>;
535 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
536 "ai\t$rT, $rA, $val", IntegerOp,
537 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
538 v4i32SExt10Imm:$val))]>;
541 RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
542 "ai\t$rT, $rA, $val", IntegerOp,
543 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
546 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
547 "sfh\t$rT, $rA, $rB", IntegerOp,
548 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
549 (v8i16 VECREG:$rB)))]>;
552 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
553 "sfh\t$rT, $rA, $rB", IntegerOp,
554 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
557 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
558 "sfhi\t$rT, $rA, $val", IntegerOp,
559 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
560 (v8i16 VECREG:$rA)))]>;
562 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
563 "sfhi\t$rT, $rA, $val", IntegerOp,
564 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
566 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
567 (ins VECREG:$rA, VECREG:$rB),
568 "sf\t$rT, $rA, $rB", IntegerOp,
569 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
571 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
572 "sf\t$rT, $rA, $rB", IntegerOp,
573 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
576 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
577 "sfi\t$rT, $rA, $val", IntegerOp,
578 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
579 (v4i32 VECREG:$rA)))]>;
581 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
582 (ins R32C:$rA, s10imm_i32:$val),
583 "sfi\t$rT, $rA, $val", IntegerOp,
584 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
586 // ADDX: only available in vector form, doesn't match a pattern.
588 RRForm<0b00000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
590 "addx\t$rT, $rA, $rB", IntegerOp,
592 RegConstraint<"$rCarry = $rT">,
595 // CG: only available in vector form, doesn't match a pattern.
597 RRForm<0b01000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
599 "cg\t$rT, $rA, $rB", IntegerOp,
601 RegConstraint<"$rCarry = $rT">,
604 // SFX: only available in vector form, doesn't match a pattern
606 RRForm<0b10000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
608 "sfx\t$rT, $rA, $rB", IntegerOp,
610 RegConstraint<"$rCarry = $rT">,
613 // BG: only available in vector form, doesn't match a pattern.
615 RRForm<0b01000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
617 "bg\t$rT, $rA, $rB", IntegerOp,
619 RegConstraint<"$rCarry = $rT">,
622 // BGX: only available in vector form, doesn't match a pattern.
624 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
626 "bgx\t$rT, $rA, $rB", IntegerOp,
628 RegConstraint<"$rCarry = $rT">,
631 // Halfword multiply variants:
632 // N.B: These can be used to build up larger quantities (16x16 -> 32)
635 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
636 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
637 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
638 (v8i16 VECREG:$rB)))]>;
641 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
642 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
643 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
646 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
647 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
648 [(set (v4i32 VECREG:$rT),
649 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
652 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
653 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
654 [(set R32C:$rT, (mul (zext R16C:$rA),
658 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
659 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
660 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
662 // mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
663 // this only produces the lower 16 bits)
665 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
666 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
667 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
670 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
671 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
672 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
674 // mpyui: same issues as other multiplies, plus, this doesn't match a
675 // pattern... but may be used during target DAG selection or lowering
677 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
678 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
682 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
683 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
686 // mpya: 16 x 16 + 16 -> 32 bit result
688 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
689 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
690 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
691 (v8i16 VECREG:$rB)))),
692 (v4i32 VECREG:$rC)))]>;
695 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
696 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
697 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
700 def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
701 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
703 def MPYAr32_sextinreg:
704 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
705 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
706 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
707 (sext_inreg R32C:$rB, i16)),
711 // RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
712 // "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
713 // [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
716 // mpyh: multiply high, used to synthesize 32-bit multiplies
718 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
719 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
720 [(set (v4i32 VECREG:$rT),
721 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
724 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
725 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
726 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
728 // mpys: multiply high and shift right (returns the top half of
729 // a 16-bit multiply, sign extended to 32 bits.)
731 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
732 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
736 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
737 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
740 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
741 // the top 16 bits of the $rA, $rB)
743 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
744 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
745 [(set (v8i16 VECREG:$rT),
746 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
749 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
750 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
753 // mpyhha: Multiply high-high, add to $rT:
755 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
756 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
760 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
761 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
764 // mpyhhu: Multiply high-high, unsigned
766 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
767 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
771 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
772 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
775 // mpyhhau: Multiply high-high, unsigned
777 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
778 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
782 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
783 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
786 // clz: Count leading zeroes
788 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
789 "clz\t$rT, $rA", IntegerOp,
793 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
794 "clz\t$rT, $rA", IntegerOp,
795 [(set R32C:$rT, (ctlz R32C:$rA))]>;
797 // cntb: Count ones in bytes (aka "population count")
798 // NOTE: This instruction is really a vector instruction, but the custom
799 // lowering code uses it in unorthodox ways to support CTPOP for other
802 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
803 "cntb\t$rT, $rA", IntegerOp,
804 [(set (v16i8 VECREG:$rT), (SPUcntb_v16i8 (v16i8 VECREG:$rA)))]>;
807 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
808 "cntb\t$rT, $rA", IntegerOp,
809 [(set (v8i16 VECREG:$rT), (SPUcntb_v8i16 (v8i16 VECREG:$rA)))]>;
812 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
813 "cntb\t$rT, $rA", IntegerOp,
814 [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>;
816 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
817 // quantity stored into $rT
819 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
820 "gbb\t$rT, $rA", GatherOp,
823 // gbh: Gather all low order bits from each halfword in $rA into a single
824 // 8-bit quantity stored in $rT
826 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
827 "gbh\t$rT, $rA", GatherOp,
830 // gb: Gather all low order bits from each word in $rA into a single
831 // 4-bit quantity stored in $rT
833 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
834 "gb\t$rT, $rA", GatherOp,
837 // avgb: average bytes
839 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
840 "avgb\t$rT, $rA, $rB", ByteOp,
843 // absdb: absolute difference of bytes
845 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
846 "absdb\t$rT, $rA, $rB", ByteOp,
849 // sumb: sum bytes into halfwords
851 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
852 "sumb\t$rT, $rA, $rB", ByteOp,
855 // Sign extension operations:
857 RRForm_1<0b01101101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
858 "xsbh\t$rDst, $rSrc", IntegerOp,
859 [(set (v8i16 VECREG:$rDst), (sext (v16i8 VECREG:$rSrc)))]>;
861 // Ordinary form for XSBH
863 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R16C:$rSrc),
864 "xsbh\t$rDst, $rSrc", IntegerOp,
865 [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>;
868 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R8C:$rSrc),
869 "xsbh\t$rDst, $rSrc", IntegerOp,
870 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
872 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
873 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
874 // pattern below). Intentionally doesn't match a pattern because we want the
875 // sext 8->32 pattern to do the work for us, namely because we need the extra
878 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
879 "xsbh\t$rDst, $rSrc", IntegerOp,
880 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i8))]>;
882 // Sign extend halfwords to words:
884 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
885 "xshw\t$rDest, $rSrc", IntegerOp,
886 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
889 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
890 "xshw\t$rDst, $rSrc", IntegerOp,
891 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
894 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
895 "xshw\t$rDst, $rSrc", IntegerOp,
896 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
899 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
900 "xswd\t$rDst, $rSrc", IntegerOp,
901 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
904 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
905 "xswd\t$rDst, $rSrc", IntegerOp,
906 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
909 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
910 "xswd\t$rDst, $rSrc", IntegerOp,
911 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
913 def : Pat<(sext R32C:$inp),
914 (XSWDr32 R32C:$inp)>;
918 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
919 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
922 class ANDVecInst<ValueType vectype>:
923 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
924 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
925 (vectype VECREG:$rB)))]>;
927 class ANDRegInst<RegisterClass rclass>:
928 ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
929 [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>;
931 multiclass BitwiseAnd
933 def v16i8: ANDVecInst<v16i8>;
934 def v8i16: ANDVecInst<v8i16>;
935 def v4i32: ANDVecInst<v4i32>;
936 def v2i64: ANDVecInst<v2i64>;
938 def r128: ANDRegInst<GPRC>;
939 def r64: ANDRegInst<R64C>;
940 def r32: ANDRegInst<R32C>;
941 def r16: ANDRegInst<R16C>;
942 def r8: ANDRegInst<R8C>;
944 //===---------------------------------------------
945 // Special instructions to perform the fabs instruction
946 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
947 [/* Intentionally does not match a pattern */]>;
949 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
950 [/* Intentionally does not match a pattern */]>;
952 // Could use v4i32, but won't for clarity
953 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
954 [/* Intentionally does not match a pattern */]>;
956 //===---------------------------------------------
958 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
959 // quantities -- see 16->32 zext pattern.
961 // This pattern is somewhat artificial, since it might match some
962 // compiler generated pattern but it is unlikely to do so.
964 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
965 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
968 defm AND : BitwiseAnd;
970 // N.B.: vnot_conv is one of those special target selection pattern fragments,
971 // in which we expect there to be a bit_convert on the constant. Bear in mind
972 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
973 // constant -1 vector.)
975 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
976 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
979 class ANDCVecInst<ValueType vectype>:
980 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
981 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
982 (vnot (vectype VECREG:$rB))))]>;
984 class ANDCRegInst<RegisterClass rclass>:
985 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
986 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
988 multiclass AndComplement
990 def v16i8: ANDCVecInst<v16i8>;
991 def v8i16: ANDCVecInst<v8i16>;
992 def v4i32: ANDCVecInst<v4i32>;
993 def v2i64: ANDCVecInst<v2i64>;
995 def r128: ANDCRegInst<GPRC>;
996 def r64: ANDCRegInst<R64C>;
997 def r32: ANDCRegInst<R32C>;
998 def r16: ANDCRegInst<R16C>;
999 def r8: ANDCRegInst<R8C>;
1002 defm ANDC : AndComplement;
1004 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1005 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1006 IntegerOp, pattern>;
1008 multiclass AndByteImm
1010 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1011 [(set (v16i8 VECREG:$rT),
1012 (and (v16i8 VECREG:$rA),
1013 (v16i8 v16i8U8Imm:$val)))]>;
1015 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1016 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1019 defm ANDBI : AndByteImm;
1021 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1022 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1023 IntegerOp, pattern>;
1025 multiclass AndHalfwordImm
1027 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1028 [(set (v8i16 VECREG:$rT),
1029 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1031 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1032 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1034 // Zero-extend i8 to i16:
1035 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1036 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1039 defm ANDHI : AndHalfwordImm;
1041 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1042 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1043 IntegerOp, pattern>;
1045 multiclass AndWordImm
1047 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1048 [(set (v4i32 VECREG:$rT),
1049 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1051 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1052 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1054 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1056 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1058 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1060 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1061 // zext 16->32 pattern below.
1063 // Note that this pattern is somewhat artificial, since it might match
1064 // something the compiler generates but is unlikely to occur in practice.
1065 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1067 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1070 defm ANDI : AndWordImm;
1072 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1073 // Bitwise OR group:
1074 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1076 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1077 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1078 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1079 IntegerOp, pattern>;
1081 class ORVecInst<ValueType vectype>:
1082 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1083 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1084 (vectype VECREG:$rB)))]>;
1086 class ORRegInst<RegisterClass rclass>:
1087 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1088 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1090 class ORPromoteScalar<RegisterClass rclass>:
1091 ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB),
1092 [/* no pattern */]>;
1094 class ORExtractElt<RegisterClass rclass>:
1095 ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB),
1096 [/* no pattern */]>;
1098 multiclass BitwiseOr
1100 def v16i8: ORVecInst<v16i8>;
1101 def v8i16: ORVecInst<v8i16>;
1102 def v4i32: ORVecInst<v4i32>;
1103 def v2i64: ORVecInst<v2i64>;
1105 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1106 [(set (v4f32 VECREG:$rT),
1107 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1108 (v4i32 VECREG:$rB)))))]>;
1110 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1111 [(set (v2f64 VECREG:$rT),
1112 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1113 (v2i64 VECREG:$rB)))))]>;
1115 def r64: ORRegInst<R64C>;
1116 def r32: ORRegInst<R32C>;
1117 def r16: ORRegInst<R16C>;
1118 def r8: ORRegInst<R8C>;
1120 // OR instructions used to copy f32 and f64 registers.
1121 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1122 [/* no pattern */]>;
1124 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1125 [/* no pattern */]>;
1127 // scalar->vector promotion:
1128 def v16i8_i8: ORPromoteScalar<R8C>;
1129 def v8i16_i16: ORPromoteScalar<R16C>;
1130 def v4i32_i32: ORPromoteScalar<R32C>;
1131 def v2i64_i64: ORPromoteScalar<R64C>;
1132 def v4f32_f32: ORPromoteScalar<R32FP>;
1133 def v2f64_f64: ORPromoteScalar<R64FP>;
1135 // extract element 0:
1136 def i8_v16i8: ORExtractElt<R8C>;
1137 def i16_v8i16: ORExtractElt<R16C>;
1138 def i32_v4i32: ORExtractElt<R32C>;
1139 def i64_v2i64: ORExtractElt<R64C>;
1140 def f32_v4f32: ORExtractElt<R32FP>;
1141 def f64_v2f64: ORExtractElt<R64FP>;
1144 defm OR : BitwiseOr;
1146 // scalar->vector promotion patterns:
1147 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
1148 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
1150 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1151 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1153 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1154 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1156 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1157 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1159 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1160 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1162 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1163 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1165 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1167 def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)),
1168 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1170 def : Pat<(SPUextract_elt0_chained (v16i8 VECREG:$rA)),
1171 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1173 def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
1174 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1176 def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
1177 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1179 def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
1180 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1182 def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
1183 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1185 def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
1186 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1188 def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
1189 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1191 def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
1192 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1194 def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
1195 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1197 def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
1198 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1200 def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
1201 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1203 // ORC: Bitwise "or" with complement (c = a | ~b)
1205 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1206 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1207 IntegerOp, pattern>;
1209 class ORCVecInst<ValueType vectype>:
1210 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1211 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1212 (vnot (vectype VECREG:$rB))))]>;
1214 class ORCRegInst<RegisterClass rclass>:
1215 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1216 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1218 multiclass BitwiseOrComplement
1220 def v16i8: ORCVecInst<v16i8>;
1221 def v8i16: ORCVecInst<v8i16>;
1222 def v4i32: ORCVecInst<v4i32>;
1223 def v2i64: ORCVecInst<v2i64>;
1225 def r64: ORCRegInst<R64C>;
1226 def r32: ORCRegInst<R32C>;
1227 def r16: ORCRegInst<R16C>;
1228 def r8: ORCRegInst<R8C>;
1231 defm ORC : BitwiseOrComplement;
1233 // OR byte immediate
1234 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1235 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1236 IntegerOp, pattern>;
1238 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1239 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1240 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1241 (vectype immpred:$val)))]>;
1243 multiclass BitwiseOrByteImm
1245 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1247 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1248 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1251 defm ORBI : BitwiseOrByteImm;
1253 // OR halfword immediate
1254 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1255 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1256 IntegerOp, pattern>;
1258 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1259 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1260 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1263 multiclass BitwiseOrHalfwordImm
1265 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1267 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1268 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1270 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1271 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1272 [(set R16C:$rT, (or (anyext R8C:$rA),
1273 i16ImmSExt10:$val))]>;
1276 defm ORHI : BitwiseOrHalfwordImm;
1278 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1279 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1280 IntegerOp, pattern>;
1282 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1283 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1284 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1287 // Bitwise "or" with immediate
1288 multiclass BitwiseOrImm
1290 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1292 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1293 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1295 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1296 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1297 // infra "anyext 16->32" pattern.)
1298 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1299 [(set R32C:$rT, (or (anyext R16C:$rA),
1300 i32ImmSExt10:$val))]>;
1302 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1303 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1304 // infra "anyext 16->32" pattern.)
1305 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1306 [(set R32C:$rT, (or (anyext R8C:$rA),
1307 i32ImmSExt10:$val))]>;
1310 defm ORI : BitwiseOrImm;
1312 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1313 // $rT[0], slots 1-3 are zeroed.
1315 // FIXME: Needs to match an intrinsic pattern.
1317 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1318 "orx\t$rT, $rA, $rB", IntegerOp,
1323 class XORInst<dag OOL, dag IOL, list<dag> pattern> :
1324 RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB",
1325 IntegerOp, pattern>;
1327 class XORVecInst<ValueType vectype>:
1328 XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1329 [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA),
1330 (vectype VECREG:$rB)))]>;
1332 class XORRegInst<RegisterClass rclass>:
1333 XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1334 [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>;
1336 multiclass BitwiseExclusiveOr
1338 def v16i8: XORVecInst<v16i8>;
1339 def v8i16: XORVecInst<v8i16>;
1340 def v4i32: XORVecInst<v4i32>;
1341 def v2i64: XORVecInst<v2i64>;
1343 def r128: XORRegInst<GPRC>;
1344 def r64: XORRegInst<R64C>;
1345 def r32: XORRegInst<R32C>;
1346 def r16: XORRegInst<R16C>;
1347 def r8: XORRegInst<R8C>;
1349 // Special forms for floating point instructions.
1350 // fneg and fabs require bitwise logical ops to manipulate the sign bit.
1352 def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1353 [/* no pattern */]>;
1355 def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1356 [/* no pattern */]>;
1358 def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1359 [/* no pattern, see fneg{32,64} */]>;
1362 defm XOR : BitwiseExclusiveOr;
1364 //==----------------------------------------------------------
1366 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1367 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1368 IntegerOp, pattern>;
1370 multiclass XorByteImm
1373 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1374 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1377 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1378 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1381 defm XORBI : XorByteImm;
1384 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1385 "xorhi\t$rT, $rA, $val", IntegerOp,
1386 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1387 v8i16SExt10Imm:$val))]>;
1390 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1391 "xorhi\t$rT, $rA, $val", IntegerOp,
1392 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1395 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1396 "xori\t$rT, $rA, $val", IntegerOp,
1397 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1398 v4i32SExt10Imm:$val))]>;
1401 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1402 "xori\t$rT, $rA, $val", IntegerOp,
1403 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1407 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1408 "nand\t$rT, $rA, $rB", IntegerOp,
1409 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1410 (v16i8 VECREG:$rB))))]>;
1413 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1414 "nand\t$rT, $rA, $rB", IntegerOp,
1415 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1416 (v8i16 VECREG:$rB))))]>;
1419 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1420 "nand\t$rT, $rA, $rB", IntegerOp,
1421 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1422 (v4i32 VECREG:$rB))))]>;
1425 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1426 "nand\t$rT, $rA, $rB", IntegerOp,
1427 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1430 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1431 "nand\t$rT, $rA, $rB", IntegerOp,
1432 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1435 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1436 "nand\t$rT, $rA, $rB", IntegerOp,
1437 [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
1441 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1442 "nor\t$rT, $rA, $rB", IntegerOp,
1443 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1444 (v16i8 VECREG:$rB))))]>;
1447 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1448 "nor\t$rT, $rA, $rB", IntegerOp,
1449 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1450 (v8i16 VECREG:$rB))))]>;
1453 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1454 "nor\t$rT, $rA, $rB", IntegerOp,
1455 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1456 (v4i32 VECREG:$rB))))]>;
1459 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1460 "nor\t$rT, $rA, $rB", IntegerOp,
1461 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1464 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1465 "nor\t$rT, $rA, $rB", IntegerOp,
1466 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1469 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1470 "nor\t$rT, $rA, $rB", IntegerOp,
1471 [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
1474 class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
1475 RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC",
1476 IntegerOp, pattern>;
1478 class SELBVecInst<ValueType vectype>:
1479 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1480 [(set (vectype VECREG:$rT),
1481 (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)),
1482 (and (vnot (vectype VECREG:$rC)),
1483 (vectype VECREG:$rA))))]>;
1485 class SELBRegInst<RegisterClass rclass>:
1486 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
1488 (or (and rclass:$rA, rclass:$rC),
1489 (and rclass:$rB, (not rclass:$rC))))]>;
1491 multiclass SelectBits
1493 def v16i8: SELBVecInst<v16i8>;
1494 def v8i16: SELBVecInst<v8i16>;
1495 def v4i32: SELBVecInst<v4i32>;
1496 def v2i64: SELBVecInst<v2i64>;
1498 def r128: SELBRegInst<GPRC>;
1499 def r64: SELBRegInst<R64C>;
1500 def r32: SELBRegInst<R32C>;
1501 def r16: SELBRegInst<R16C>;
1502 def r8: SELBRegInst<R8C>;
1505 defm SELB : SelectBits;
1507 class SPUselbPat<ValueType vectype, SPUInstr inst>:
1508 Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)),
1509 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1511 def : SPUselbPat<v16i8, SELBv16i8>;
1512 def : SPUselbPat<v8i16, SELBv8i16>;
1513 def : SPUselbPat<v4i32, SELBv4i32>;
1514 def : SPUselbPat<v2i64, SELBv2i64>;
1516 class SelectConditional<RegisterClass rclass, SPUInstr inst>:
1517 Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse),
1518 (inst rclass:$rCond, rclass:$rFalse, rclass:$rTrue)>;
1520 def : SelectConditional<R32C, SELBr32>;
1521 def : SelectConditional<R16C, SELBr16>;
1522 def : SelectConditional<R8C, SELBr8>;
1524 // EQV: Equivalence (1 for each same bit, otherwise 0)
1526 // Note: There are a lot of ways to match this bit operator and these patterns
1527 // attempt to be as exhaustive as possible.
1529 class EQVInst<dag OOL, dag IOL, list<dag> pattern>:
1530 RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB",
1531 IntegerOp, pattern>;
1533 class EQVVecInst<ValueType vectype>:
1534 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1535 [(set (vectype VECREG:$rT),
1536 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1537 (and (vnot (vectype VECREG:$rA)),
1538 (vnot (vectype VECREG:$rB)))))]>;
1540 class EQVRegInst<RegisterClass rclass>:
1541 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1542 [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB),
1543 (and (not rclass:$rA), (not rclass:$rB))))]>;
1545 class EQVVecPattern1<ValueType vectype>:
1546 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1547 [(set (vectype VECREG:$rT),
1548 (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>;
1550 class EQVRegPattern1<RegisterClass rclass>:
1551 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1552 [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>;
1554 class EQVVecPattern2<ValueType vectype>:
1555 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1556 [(set (vectype VECREG:$rT),
1557 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1558 (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>;
1560 class EQVRegPattern2<RegisterClass rclass>:
1561 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1563 (or (and rclass:$rA, rclass:$rB),
1564 (not (or rclass:$rA, rclass:$rB))))]>;
1566 class EQVVecPattern3<ValueType vectype>:
1567 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1568 [(set (vectype VECREG:$rT),
1569 (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>;
1571 class EQVRegPattern3<RegisterClass rclass>:
1572 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1573 [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>;
1575 multiclass BitEquivalence
1577 def v16i8: EQVVecInst<v16i8>;
1578 def v8i16: EQVVecInst<v8i16>;
1579 def v4i32: EQVVecInst<v4i32>;
1580 def v2i64: EQVVecInst<v2i64>;
1582 def v16i8_1: EQVVecPattern1<v16i8>;
1583 def v8i16_1: EQVVecPattern1<v8i16>;
1584 def v4i32_1: EQVVecPattern1<v4i32>;
1585 def v2i64_1: EQVVecPattern1<v2i64>;
1587 def v16i8_2: EQVVecPattern2<v16i8>;
1588 def v8i16_2: EQVVecPattern2<v8i16>;
1589 def v4i32_2: EQVVecPattern2<v4i32>;
1590 def v2i64_2: EQVVecPattern2<v2i64>;
1592 def v16i8_3: EQVVecPattern3<v16i8>;
1593 def v8i16_3: EQVVecPattern3<v8i16>;
1594 def v4i32_3: EQVVecPattern3<v4i32>;
1595 def v2i64_3: EQVVecPattern3<v2i64>;
1597 def r128: EQVRegInst<GPRC>;
1598 def r64: EQVRegInst<R64C>;
1599 def r32: EQVRegInst<R32C>;
1600 def r16: EQVRegInst<R16C>;
1601 def r8: EQVRegInst<R8C>;
1603 def r128_1: EQVRegPattern1<GPRC>;
1604 def r64_1: EQVRegPattern1<R64C>;
1605 def r32_1: EQVRegPattern1<R32C>;
1606 def r16_1: EQVRegPattern1<R16C>;
1607 def r8_1: EQVRegPattern1<R8C>;
1609 def r128_2: EQVRegPattern2<GPRC>;
1610 def r64_2: EQVRegPattern2<R64C>;
1611 def r32_2: EQVRegPattern2<R32C>;
1612 def r16_2: EQVRegPattern2<R16C>;
1613 def r8_2: EQVRegPattern2<R8C>;
1615 def r128_3: EQVRegPattern3<GPRC>;
1616 def r64_3: EQVRegPattern3<R64C>;
1617 def r32_3: EQVRegPattern3<R32C>;
1618 def r16_3: EQVRegPattern3<R16C>;
1619 def r8_3: EQVRegPattern3<R8C>;
1622 defm EQV: BitEquivalence;
1624 //===----------------------------------------------------------------------===//
1625 // Vector shuffle...
1626 //===----------------------------------------------------------------------===//
1627 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
1628 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
1629 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
1630 // the SPUISD::SHUFB opcode.
1631 //===----------------------------------------------------------------------===//
1633 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
1634 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
1635 IntegerOp, pattern>;
1637 class SHUFBVecInst<ValueType vectype>:
1638 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1639 [(set (vectype VECREG:$rT), (SPUshuffle (vectype VECREG:$rA),
1640 (vectype VECREG:$rB),
1641 (vectype VECREG:$rC)))]>;
1643 // It's this pattern that's probably the most useful, since SPUISelLowering
1644 // methods create a v16i8 vector for $rC:
1645 class SHUFBVecPat1<ValueType vectype, SPUInstr inst>:
1646 Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB),
1647 (v16i8 VECREG:$rC)),
1648 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1650 multiclass ShuffleBytes
1652 def v16i8 : SHUFBVecInst<v16i8>;
1653 def v8i16 : SHUFBVecInst<v8i16>;
1654 def v4i32 : SHUFBVecInst<v4i32>;
1655 def v2i64 : SHUFBVecInst<v2i64>;
1657 def v4f32 : SHUFBVecInst<v4f32>;
1658 def v2f64 : SHUFBVecInst<v2f64>;
1661 defm SHUFB : ShuffleBytes;
1663 def : SHUFBVecPat1<v8i16, SHUFBv16i8>;
1664 def : SHUFBVecPat1<v4i32, SHUFBv16i8>;
1665 def : SHUFBVecPat1<v2i64, SHUFBv16i8>;
1666 def : SHUFBVecPat1<v4f32, SHUFBv16i8>;
1667 def : SHUFBVecPat1<v2f64, SHUFBv16i8>;
1669 //===----------------------------------------------------------------------===//
1670 // Shift and rotate group:
1671 //===----------------------------------------------------------------------===//
1673 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
1674 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
1675 RotateShift, pattern>;
1677 class SHLHVecInst<ValueType vectype>:
1678 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1679 [(set (vectype VECREG:$rT),
1680 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
1682 // $rB gets promoted to 32-bit register type when confronted with
1683 // this llvm assembly code:
1685 // define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
1686 // %A = shl i16 %arg1, %arg2
1690 multiclass ShiftLeftHalfword
1692 def v8i16: SHLHVecInst<v8i16>;
1693 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1694 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1695 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1696 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1699 defm SHLH : ShiftLeftHalfword;
1701 //===----------------------------------------------------------------------===//
1703 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
1704 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
1705 RotateShift, pattern>;
1707 class SHLHIVecInst<ValueType vectype>:
1708 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1709 [(set (vectype VECREG:$rT),
1710 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
1712 multiclass ShiftLeftHalfwordImm
1714 def v8i16: SHLHIVecInst<v8i16>;
1715 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
1716 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
1719 defm SHLHI : ShiftLeftHalfwordImm;
1721 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
1722 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
1724 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
1725 (SHLHIr16 R16C:$rA, uimm7:$val)>;
1727 //===----------------------------------------------------------------------===//
1729 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
1730 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
1731 RotateShift, pattern>;
1733 multiclass ShiftLeftWord
1736 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1737 [(set (v4i32 VECREG:$rT),
1738 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
1740 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1741 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
1744 defm SHL: ShiftLeftWord;
1746 //===----------------------------------------------------------------------===//
1748 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
1749 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
1750 RotateShift, pattern>;
1752 multiclass ShiftLeftWordImm
1755 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1756 [(set (v4i32 VECREG:$rT),
1757 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
1760 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
1761 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
1764 defm SHLI : ShiftLeftWordImm;
1766 //===----------------------------------------------------------------------===//
1767 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
1768 // register) to the left. Vector form is here to ensure type correctness.
1770 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
1771 // of 7 bits is actually possible.
1773 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
1774 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
1775 // bytes with SHLQBY.
1777 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
1778 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
1779 RotateShift, pattern>;
1781 class SHLQBIVecInst<ValueType vectype>:
1782 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1783 [(set (vectype VECREG:$rT),
1784 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
1786 multiclass ShiftLeftQuadByBits
1788 def v16i8: SHLQBIVecInst<v16i8>;
1789 def v8i16: SHLQBIVecInst<v8i16>;
1790 def v4i32: SHLQBIVecInst<v4i32>;
1791 def v2i64: SHLQBIVecInst<v2i64>;
1794 defm SHLQBI : ShiftLeftQuadByBits;
1796 // See note above on SHLQBI. In this case, the predicate actually does then
1797 // enforcement, whereas with SHLQBI, we have to "take it on faith."
1798 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
1799 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
1800 RotateShift, pattern>;
1802 class SHLQBIIVecInst<ValueType vectype>:
1803 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1804 [(set (vectype VECREG:$rT),
1805 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
1807 multiclass ShiftLeftQuadByBitsImm
1809 def v16i8 : SHLQBIIVecInst<v16i8>;
1810 def v8i16 : SHLQBIIVecInst<v8i16>;
1811 def v4i32 : SHLQBIIVecInst<v4i32>;
1812 def v2i64 : SHLQBIIVecInst<v2i64>;
1815 defm SHLQBII : ShiftLeftQuadByBitsImm;
1817 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
1818 // not by bits. See notes above on SHLQBI.
1820 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
1821 RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB",
1822 RotateShift, pattern>;
1824 class SHLQBYVecInst<ValueType vectype>:
1825 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1826 [(set (vectype VECREG:$rT),
1827 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
1829 multiclass ShiftLeftQuadBytes
1831 def v16i8: SHLQBYVecInst<v16i8>;
1832 def v8i16: SHLQBYVecInst<v8i16>;
1833 def v4i32: SHLQBYVecInst<v4i32>;
1834 def v2i64: SHLQBYVecInst<v2i64>;
1835 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
1836 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
1839 defm SHLQBY: ShiftLeftQuadBytes;
1841 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
1842 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
1843 RotateShift, pattern>;
1845 class SHLQBYIVecInst<ValueType vectype>:
1846 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1847 [(set (vectype VECREG:$rT),
1848 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
1850 multiclass ShiftLeftQuadBytesImm
1852 def v16i8: SHLQBYIVecInst<v16i8>;
1853 def v8i16: SHLQBYIVecInst<v8i16>;
1854 def v4i32: SHLQBYIVecInst<v4i32>;
1855 def v2i64: SHLQBYIVecInst<v2i64>;
1856 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
1858 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
1861 defm SHLQBYI : ShiftLeftQuadBytesImm;
1863 // Special form for truncating i64 to i32:
1864 def SHLQBYItrunc64: SHLQBYIInst<(outs R32C:$rT), (ins R64C:$rA, u7imm_i32:$val),
1865 [/* no pattern, see below */]>;
1867 def : Pat<(trunc R64C:$rSrc),
1868 (SHLQBYItrunc64 R64C:$rSrc, 4)>;
1870 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1872 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1873 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
1874 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
1875 RotateShift, pattern>;
1877 class ROTHVecInst<ValueType vectype>:
1878 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1879 [(set (vectype VECREG:$rT),
1880 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
1882 class ROTHRegInst<RegisterClass rclass>:
1883 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1884 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
1886 multiclass RotateLeftHalfword
1888 def v8i16: ROTHVecInst<v8i16>;
1889 def r16: ROTHRegInst<R16C>;
1892 defm ROTH: RotateLeftHalfword;
1894 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1895 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
1897 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1898 // Rotate halfword, immediate:
1899 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1900 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
1901 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
1902 RotateShift, pattern>;
1904 class ROTHIVecInst<ValueType vectype>:
1905 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1906 [(set (vectype VECREG:$rT),
1907 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
1909 multiclass RotateLeftHalfwordImm
1911 def v8i16: ROTHIVecInst<v8i16>;
1912 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
1913 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
1914 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
1915 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
1918 defm ROTHI: RotateLeftHalfwordImm;
1920 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
1921 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
1923 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1925 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1927 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
1928 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
1929 RotateShift, pattern>;
1931 class ROTVecInst<ValueType vectype>:
1932 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1933 [(set (vectype VECREG:$rT),
1934 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
1936 class ROTRegInst<RegisterClass rclass>:
1937 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
1939 (rotl rclass:$rA, R32C:$rB))]>;
1941 multiclass RotateLeftWord
1943 def v4i32: ROTVecInst<v4i32>;
1944 def r32: ROTRegInst<R32C>;
1947 defm ROT: RotateLeftWord;
1949 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
1951 def ROTr32_r16_anyext:
1952 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
1953 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
1955 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
1956 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
1958 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
1959 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
1961 def ROTr32_r8_anyext:
1962 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
1963 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
1965 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
1966 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
1968 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
1969 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
1971 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1972 // Rotate word, immediate
1973 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1975 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
1976 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
1977 RotateShift, pattern>;
1979 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
1980 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
1981 [(set (vectype VECREG:$rT),
1982 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
1984 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
1985 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
1986 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
1988 multiclass RotateLeftWordImm
1990 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
1991 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
1992 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
1994 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
1995 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
1996 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
1999 defm ROTI : RotateLeftWordImm;
2001 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2002 // Rotate quad by byte (count)
2003 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2005 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2006 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2007 RotateShift, pattern>;
2009 class ROTQBYVecInst<ValueType vectype>:
2010 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2011 [(set (vectype VECREG:$rT),
2012 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2014 multiclass RotateQuadLeftByBytes
2016 def v16i8: ROTQBYVecInst<v16i8>;
2017 def v8i16: ROTQBYVecInst<v8i16>;
2018 def v4i32: ROTQBYVecInst<v4i32>;
2019 def v2i64: ROTQBYVecInst<v2i64>;
2022 defm ROTQBY: RotateQuadLeftByBytes;
2024 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
2025 (ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
2026 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
2027 (ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
2028 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
2029 (ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
2030 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
2031 (ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
2033 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2034 // Rotate quad by byte (count), immediate
2035 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2037 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2038 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2039 RotateShift, pattern>;
2041 class ROTQBYIVecInst<ValueType vectype>:
2042 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2043 [(set (vectype VECREG:$rT),
2044 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2046 multiclass RotateQuadByBytesImm
2048 def v16i8: ROTQBYIVecInst<v16i8>;
2049 def v8i16: ROTQBYIVecInst<v8i16>;
2050 def v4i32: ROTQBYIVecInst<v4i32>;
2051 def v2i64: ROTQBYIVecInst<v2i64>;
2054 defm ROTQBYI: RotateQuadByBytesImm;
2056 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2057 (ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
2058 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2059 (ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
2060 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2061 (ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
2062 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
2063 (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
2065 // See ROTQBY note above.
2067 RI7Form<0b00110011100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2068 "rotqbybi\t$rT, $rA, $val", RotateShift,
2071 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2072 // See ROTQBY note above.
2074 // Assume that the user of this instruction knows to shift the rotate count
2076 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2078 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2079 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2080 RotateShift, pattern>;
2082 class ROTQBIVecInst<ValueType vectype>:
2083 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2084 [/* no pattern yet */]>;
2086 class ROTQBIRegInst<RegisterClass rclass>:
2087 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2088 [/* no pattern yet */]>;
2090 multiclass RotateQuadByBitCount
2092 def v16i8: ROTQBIVecInst<v16i8>;
2093 def v8i16: ROTQBIVecInst<v8i16>;
2094 def v4i32: ROTQBIVecInst<v4i32>;
2095 def v2i64: ROTQBIVecInst<v2i64>;
2097 def r128: ROTQBIRegInst<GPRC>;
2098 def r64: ROTQBIRegInst<R64C>;
2101 defm ROTQBI: RotateQuadByBitCount;
2103 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2104 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2105 RotateShift, pattern>;
2107 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2109 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2110 [/* no pattern yet */]>;
2112 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2114 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2115 [/* no pattern yet */]>;
2117 multiclass RotateQuadByBitCountImm
2119 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2120 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2121 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2122 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2124 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2125 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2128 defm ROTQBII : RotateQuadByBitCountImm;
2130 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2131 // ROTHM v8i16 form:
2132 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2133 // so this only matches a synthetically generated/lowered code
2135 // NOTE(2): $rB must be negated before the right rotate!
2136 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2138 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2139 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2140 RotateShift, pattern>;
2143 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2144 [/* see patterns below - $rB must be negated */]>;
2146 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2147 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2149 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2150 (ROTHMv8i16 VECREG:$rA,
2151 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2153 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2154 (ROTHMv8i16 VECREG:$rA,
2155 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2157 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2158 // Note: This instruction doesn't match a pattern because rB must be negated
2159 // for the instruction to work. Thus, the pattern below the instruction!
2162 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2163 [/* see patterns below - $rB must be negated! */]>;
2165 def : Pat<(srl R16C:$rA, R32C:$rB),
2166 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2168 def : Pat<(srl R16C:$rA, R16C:$rB),
2170 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2172 def : Pat<(srl R16C:$rA, R8C:$rB),
2174 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2176 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2177 // that the immediate can be complemented, so that the user doesn't have to
2180 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2181 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2182 RotateShift, pattern>;
2185 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2186 [/* no pattern */]>;
2188 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2189 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2191 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2192 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2194 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2195 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2198 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2199 [/* no pattern */]>;
2201 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2202 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2204 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2205 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2207 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2208 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2210 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2211 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2212 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2213 RotateShift, pattern>;
2216 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2217 [/* see patterns below - $rB must be negated */]>;
2219 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
2220 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2222 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
2223 (ROTMv4i32 VECREG:$rA,
2224 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2226 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
2227 (ROTMv4i32 VECREG:$rA,
2228 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2231 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2232 [/* see patterns below - $rB must be negated */]>;
2234 def : Pat<(srl R32C:$rA, R32C:$rB),
2235 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2237 def : Pat<(srl R32C:$rA, R16C:$rB),
2239 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2241 def : Pat<(srl R32C:$rA, R8C:$rB),
2243 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2245 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2247 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2248 "rotmi\t$rT, $rA, $val", RotateShift,
2249 [(set (v4i32 VECREG:$rT),
2250 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2252 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
2253 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2255 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
2256 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2258 // ROTMI r32 form: know how to complement the immediate value.
2260 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2261 "rotmi\t$rT, $rA, $val", RotateShift,
2262 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2264 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2265 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2267 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2268 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2270 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2271 // ROTQMBYvec: This is a vector form merely so that when used in an
2272 // instruction pattern, type checking will succeed. This instruction assumes
2273 // that the user knew to negate $rB.
2275 // Using the SPUrotquad_rz_bytes target-specific DAG node, the patterns
2276 // ensure that $rB is negated.
2277 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2279 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2280 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2281 RotateShift, pattern>;
2283 class ROTQMBYVecInst<ValueType vectype>:
2284 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2285 [/* no pattern, $rB must be negated */]>;
2287 class ROTQMBYRegInst<RegisterClass rclass>:
2288 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2290 (SPUrotquad_rz_bytes rclass:$rA, R32C:$rB))]>;
2292 multiclass RotateQuadBytes
2294 def v16i8: ROTQMBYVecInst<v16i8>;
2295 def v8i16: ROTQMBYVecInst<v8i16>;
2296 def v4i32: ROTQMBYVecInst<v4i32>;
2297 def v2i64: ROTQMBYVecInst<v2i64>;
2299 def r128: ROTQMBYRegInst<GPRC>;
2300 def r64: ROTQMBYRegInst<R64C>;
2303 defm ROTQMBY : RotateQuadBytes;
2305 def : Pat<(SPUrotquad_rz_bytes (v16i8 VECREG:$rA), R32C:$rB),
2306 (ROTQMBYv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2307 def : Pat<(SPUrotquad_rz_bytes (v8i16 VECREG:$rA), R32C:$rB),
2308 (ROTQMBYv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2309 def : Pat<(SPUrotquad_rz_bytes (v4i32 VECREG:$rA), R32C:$rB),
2310 (ROTQMBYv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2311 def : Pat<(SPUrotquad_rz_bytes (v2i64 VECREG:$rA), R32C:$rB),
2312 (ROTQMBYv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2313 def : Pat<(SPUrotquad_rz_bytes GPRC:$rA, R32C:$rB),
2314 (ROTQMBYr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2315 def : Pat<(SPUrotquad_rz_bytes R64C:$rA, R32C:$rB),
2316 (ROTQMBYr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2318 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2319 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2320 RotateShift, pattern>;
2322 class ROTQMBYIVecInst<ValueType vectype>:
2323 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2324 [(set (vectype VECREG:$rT),
2325 (SPUrotquad_rz_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2327 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2328 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2330 (SPUrotquad_rz_bytes rclass:$rA, (inttype pred:$val)))]>;
2332 multiclass RotateQuadBytesImm
2334 def v16i8: ROTQMBYIVecInst<v16i8>;
2335 def v8i16: ROTQMBYIVecInst<v8i16>;
2336 def v4i32: ROTQMBYIVecInst<v4i32>;
2337 def v2i64: ROTQMBYIVecInst<v2i64>;
2339 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2340 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2343 defm ROTQMBYI : RotateQuadBytesImm;
2346 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2347 // Rotate right and mask by bit count
2348 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2350 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2351 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2352 RotateShift, pattern>;
2354 class ROTQMBYBIVecInst<ValueType vectype>:
2355 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2356 [/* no pattern, intrinsic? */]>;
2358 multiclass RotateMaskQuadByBitCount
2360 def v16i8: ROTQMBYBIVecInst<v16i8>;
2361 def v8i16: ROTQMBYBIVecInst<v8i16>;
2362 def v4i32: ROTQMBYBIVecInst<v4i32>;
2363 def v2i64: ROTQMBYBIVecInst<v2i64>;
2366 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2368 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2369 // Rotate quad and mask by bits
2370 // Note that the rotate amount has to be negated
2371 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2373 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2374 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2375 RotateShift, pattern>;
2377 class ROTQMBIVecInst<ValueType vectype>:
2378 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2379 [/* no pattern */]>;
2381 class ROTQMBIRegInst<RegisterClass rclass>:
2382 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2383 [/* no pattern */]>;
2385 multiclass RotateMaskQuadByBits
2387 def v16i8: ROTQMBIVecInst<v16i8>;
2388 def v8i16: ROTQMBIVecInst<v8i16>;
2389 def v4i32: ROTQMBIVecInst<v4i32>;
2390 def v2i64: ROTQMBIVecInst<v2i64>;
2392 def r128: ROTQMBIRegInst<GPRC>;
2393 def r64: ROTQMBIRegInst<R64C>;
2396 defm ROTQMBI: RotateMaskQuadByBits;
2398 def : Pat<(SPUrotquad_rz_bits (v16i8 VECREG:$rA), R32C:$rB),
2399 (ROTQMBIv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2400 def : Pat<(SPUrotquad_rz_bits (v8i16 VECREG:$rA), R32C:$rB),
2401 (ROTQMBIv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2402 def : Pat<(SPUrotquad_rz_bits (v4i32 VECREG:$rA), R32C:$rB),
2403 (ROTQMBIv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2404 def : Pat<(SPUrotquad_rz_bits (v2i64 VECREG:$rA), R32C:$rB),
2405 (ROTQMBIv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2406 def : Pat<(SPUrotquad_rz_bits GPRC:$rA, R32C:$rB),
2407 (ROTQMBIr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2408 def : Pat<(SPUrotquad_rz_bits R64C:$rA, R32C:$rB),
2409 (ROTQMBIr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2411 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2412 // Rotate quad and mask by bits, immediate
2413 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2415 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2416 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2417 RotateShift, pattern>;
2419 class ROTQMBIIVecInst<ValueType vectype>:
2420 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2421 [(set (vectype VECREG:$rT),
2422 (SPUrotquad_rz_bits (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2424 class ROTQMBIIRegInst<RegisterClass rclass>:
2425 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2427 (SPUrotquad_rz_bits rclass:$rA, (i32 uimm7:$val)))]>;
2429 multiclass RotateMaskQuadByBitsImm
2431 def v16i8: ROTQMBIIVecInst<v16i8>;
2432 def v8i16: ROTQMBIIVecInst<v8i16>;
2433 def v4i32: ROTQMBIIVecInst<v4i32>;
2434 def v2i64: ROTQMBIIVecInst<v2i64>;
2436 def r128: ROTQMBIIRegInst<GPRC>;
2437 def r64: ROTQMBIIRegInst<R64C>;
2440 defm ROTQMBII: RotateMaskQuadByBitsImm;
2442 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2443 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2446 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2447 "rotmah\t$rT, $rA, $rB", RotateShift,
2448 [/* see patterns below - $rB must be negated */]>;
2450 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2451 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2453 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2454 (ROTMAHv8i16 VECREG:$rA,
2455 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2457 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2458 (ROTMAHv8i16 VECREG:$rA,
2459 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2462 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2463 "rotmah\t$rT, $rA, $rB", RotateShift,
2464 [/* see patterns below - $rB must be negated */]>;
2466 def : Pat<(sra R16C:$rA, R32C:$rB),
2467 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2469 def : Pat<(sra R16C:$rA, R16C:$rB),
2470 (ROTMAHr16 R16C:$rA,
2471 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2473 def : Pat<(sra R16C:$rA, R8C:$rB),
2474 (ROTMAHr16 R16C:$rA,
2475 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2478 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2479 "rotmahi\t$rT, $rA, $val", RotateShift,
2480 [(set (v8i16 VECREG:$rT),
2481 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2483 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2484 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2486 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2487 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2490 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2491 "rotmahi\t$rT, $rA, $val", RotateShift,
2492 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2494 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2495 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2497 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2498 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2501 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2502 "rotma\t$rT, $rA, $rB", RotateShift,
2503 [/* see patterns below - $rB must be negated */]>;
2505 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2506 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2508 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2509 (ROTMAv4i32 (v4i32 VECREG:$rA),
2510 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2512 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2513 (ROTMAv4i32 (v4i32 VECREG:$rA),
2514 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2517 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2518 "rotma\t$rT, $rA, $rB", RotateShift,
2519 [/* see patterns below - $rB must be negated */]>;
2521 def : Pat<(sra R32C:$rA, R32C:$rB),
2522 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2524 def : Pat<(sra R32C:$rA, R16C:$rB),
2526 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2528 def : Pat<(sra R32C:$rA, R8C:$rB),
2530 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2533 RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2534 "rotmai\t$rT, $rA, $val", RotateShift,
2535 [(set (v4i32 VECREG:$rT),
2536 (SPUvec_sra VECREG:$rA, (i32 uimm7:$val)))]>;
2538 def : Pat<(SPUvec_sra VECREG:$rA, (i16 uimm7:$val)),
2539 (ROTMAIv4i32 VECREG:$rA, uimm7:$val)>;
2542 RRForm<0b01011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2543 "rotmai\t$rT, $rA, $val", RotateShift,
2544 [(set R32C:$rT, (sra R32C:$rA, (i32 uimm7:$val)))]>;
2546 def : Pat<(sra R32C:$rA, (i16 uimm7:$val)),
2547 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2549 def : Pat<(sra R32C:$rA, (i8 uimm7:$val)),
2550 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2552 //===----------------------------------------------------------------------===//
2553 // Branch and conditionals:
2554 //===----------------------------------------------------------------------===//
2556 let isTerminator = 1, isBarrier = 1 in {
2557 // Halt If Equal (r32 preferred slot only, no vector form)
2559 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2560 "heq\t$rA, $rB", BranchResolv,
2561 [/* no pattern to match */]>;
2564 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2565 "heqi\t$rA, $val", BranchResolv,
2566 [/* no pattern to match */]>;
2568 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2569 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2571 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2572 "hgt\t$rA, $rB", BranchResolv,
2573 [/* no pattern to match */]>;
2576 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2577 "hgti\t$rA, $val", BranchResolv,
2578 [/* no pattern to match */]>;
2581 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2582 "hlgt\t$rA, $rB", BranchResolv,
2583 [/* no pattern to match */]>;
2586 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2587 "hlgti\t$rA, $val", BranchResolv,
2588 [/* no pattern to match */]>;
2591 //------------------------------------------------------------------------
2592 // Comparison operators:
2593 //------------------------------------------------------------------------
2595 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
2596 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
2599 multiclass CmpEqualByte
2602 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2603 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2604 (v8i16 VECREG:$rB)))]>;
2607 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2608 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
2611 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
2612 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
2615 multiclass CmpEqualByteImm
2618 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2619 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
2620 v16i8SExt8Imm:$val))]>;
2622 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2623 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
2626 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
2627 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
2630 multiclass CmpEqualHalfword
2632 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2633 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2634 (v8i16 VECREG:$rB)))]>;
2636 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2637 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
2640 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
2641 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
2644 multiclass CmpEqualHalfwordImm
2646 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2647 [(set (v8i16 VECREG:$rT),
2648 (seteq (v8i16 VECREG:$rA),
2649 (v8i16 v8i16SExt10Imm:$val)))]>;
2650 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2651 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
2654 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
2655 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
2658 multiclass CmpEqualWord
2660 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2661 [(set (v4i32 VECREG:$rT),
2662 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2664 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2665 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2668 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
2669 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
2672 multiclass CmpEqualWordImm
2674 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2675 [(set (v4i32 VECREG:$rT),
2676 (seteq (v4i32 VECREG:$rA),
2677 (v4i32 v4i32SExt16Imm:$val)))]>;
2679 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2680 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2683 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2684 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
2687 multiclass CmpGtrByte
2690 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2691 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2692 (v8i16 VECREG:$rB)))]>;
2695 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2696 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
2699 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2700 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
2703 multiclass CmpGtrByteImm
2706 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2707 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
2708 v16i8SExt8Imm:$val))]>;
2710 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2711 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
2714 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2715 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
2718 multiclass CmpGtrHalfword
2720 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2721 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2722 (v8i16 VECREG:$rB)))]>;
2724 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2725 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
2728 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2729 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
2732 multiclass CmpGtrHalfwordImm
2734 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2735 [(set (v8i16 VECREG:$rT),
2736 (setgt (v8i16 VECREG:$rA),
2737 (v8i16 v8i16SExt10Imm:$val)))]>;
2738 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2739 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
2742 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
2743 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
2746 multiclass CmpGtrWord
2748 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2749 [(set (v4i32 VECREG:$rT),
2750 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2752 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2753 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
2756 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2757 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
2760 multiclass CmpGtrWordImm
2762 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2763 [(set (v4i32 VECREG:$rT),
2764 (setgt (v4i32 VECREG:$rA),
2765 (v4i32 v4i32SExt16Imm:$val)))]>;
2767 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2768 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
2771 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2772 RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB",
2775 multiclass CmpLGtrByte
2778 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2779 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2780 (v8i16 VECREG:$rB)))]>;
2783 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2784 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
2787 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2788 RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val",
2791 multiclass CmpLGtrByteImm
2794 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2795 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
2796 v16i8SExt8Imm:$val))]>;
2798 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2799 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
2802 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2803 RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB",
2806 multiclass CmpLGtrHalfword
2808 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2809 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2810 (v8i16 VECREG:$rB)))]>;
2812 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2813 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
2816 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2817 RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val",
2820 multiclass CmpLGtrHalfwordImm
2822 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2823 [(set (v8i16 VECREG:$rT),
2824 (setugt (v8i16 VECREG:$rA),
2825 (v8i16 v8i16SExt10Imm:$val)))]>;
2826 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2827 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
2830 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
2831 RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB",
2834 multiclass CmpLGtrWord
2836 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2837 [(set (v4i32 VECREG:$rT),
2838 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2840 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2841 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
2844 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2845 RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val",
2848 multiclass CmpLGtrWordImm
2850 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2851 [(set (v4i32 VECREG:$rT),
2852 (setugt (v4i32 VECREG:$rA),
2853 (v4i32 v4i32SExt16Imm:$val)))]>;
2855 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2856 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
2859 defm CEQB : CmpEqualByte;
2860 defm CEQBI : CmpEqualByteImm;
2861 defm CEQH : CmpEqualHalfword;
2862 defm CEQHI : CmpEqualHalfwordImm;
2863 defm CEQ : CmpEqualWord;
2864 defm CEQI : CmpEqualWordImm;
2865 defm CGTB : CmpGtrByte;
2866 defm CGTBI : CmpGtrByteImm;
2867 defm CGTH : CmpGtrHalfword;
2868 defm CGTHI : CmpGtrHalfwordImm;
2869 defm CGT : CmpGtrWord;
2870 defm CGTI : CmpGtrWordImm;
2871 defm CLGTB : CmpLGtrByte;
2872 defm CLGTBI : CmpLGtrByteImm;
2873 defm CLGTH : CmpLGtrHalfword;
2874 defm CLGTHI : CmpLGtrHalfwordImm;
2875 defm CLGT : CmpLGtrWord;
2876 defm CLGTI : CmpLGtrWordImm;
2878 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
2879 // define a pattern to generate the right code, as a binary operator
2880 // (in a manner of speaking.)
2882 class SETCCNegCond<PatFrag cond, RegisterClass rclass, dag pattern>:
2883 Pat<(cond rclass:$rA, rclass:$rB), pattern>;
2885 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
2886 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
2887 Pat<(cond rclass:$rA, rclass:$rB),
2888 (binop (cmpOp1 rclass:$rA, rclass:$rB),
2889 (cmpOp2 rclass:$rA, rclass:$rB))>;
2891 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
2893 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
2894 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
2895 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
2896 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
2898 def CGTEQBr8: SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
2899 def CGTEQBIr8: SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
2900 def CLTBr8: SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
2901 def CLTBIr8: SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
2902 def CLTEQr8: Pat<(setle R8C:$rA, R8C:$rB),
2903 (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
2904 def CLTEQIr8: Pat<(setle R8C:$rA, immU8:$imm),
2905 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
2907 def CGTEQHr16: SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
2908 def CGTEQHIr16: SETCCBinOpImm<setge, R16C, i16ImmUns10, i16,
2909 ORr16, CGTHIr16, CEQHIr16>;
2910 def CLTHr16: SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
2911 def CLTHIr16: SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
2912 def CLTEQr16: Pat<(setle R16C:$rA, R16C:$rB),
2913 (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
2914 def CLTEQIr16: Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
2915 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
2917 def CGTEQHr32: SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
2918 def CGTEQHIr32: SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
2919 ORr32, CGTIr32, CEQIr32>;
2920 def CLTr32: SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
2921 def CLTIr32: SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
2922 def CLTEQr32: Pat<(setle R32C:$rA, R32C:$rB),
2923 (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
2924 def CLTEQIr32: Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
2925 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
2927 def CLGTEQBr8: SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
2928 def CLGTEQBIr8: SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
2929 def CLLTBr8: SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
2930 def CLLTBIr8: SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
2931 def CLLTEQr8: Pat<(setule R8C:$rA, R8C:$rB),
2932 (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
2933 def CLLTEQIr8: Pat<(setule R8C:$rA, immU8:$imm),
2934 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
2936 def CLGTEQHr16: SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
2937 def CLGTEQHIr16: SETCCBinOpImm<setuge, R16C, i16ImmUns10, i16,
2938 ORr16, CLGTHIr16, CEQHIr16>;
2939 def CLLTHr16: SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
2940 def CLLTHIr16: SETCCBinOpImm<setult, R16C, immSExt8, i16, NORr16, CLGTHIr16, CEQHIr16>;
2941 def CLLTEQr16: Pat<(setule R16C:$rA, R16C:$rB),
2942 (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
2943 def CLLTEQIr16: Pat<(setule R16C:$rA, i16ImmUns10:$imm),
2944 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
2947 def CLGTEQHr32: SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
2948 def CLGTEQHIr32: SETCCBinOpImm<setuge, R32C, i32ImmUns10, i32,
2949 ORr32, CLGTIr32, CEQIr32>;
2950 def CLLTr32: SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
2951 def CLLTIr32: SETCCBinOpImm<setult, R32C, immSExt8, i32, NORr32, CLGTIr32, CEQIr32>;
2952 def CLLTEQr32: Pat<(setule R32C:$rA, R32C:$rB),
2953 (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
2954 def CLLTEQIr32: Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
2955 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
2957 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2960 // All calls clobber the non-callee-saved registers:
2961 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
2962 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
2963 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
2964 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
2965 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
2966 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
2967 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
2968 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
2969 // All of these instructions use $lr (aka $0)
2971 // Branch relative and set link: Used if we actually know that the target
2972 // is within [-32768, 32767] bytes of the target
2974 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
2975 "brsl\t$$lr, $func",
2976 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
2978 // Branch absolute and set link: Used if we actually know that the target
2979 // is an absolute address
2981 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
2982 "brasl\t$$lr, $func",
2983 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
2985 // Branch indirect and set link if external data. These instructions are not
2986 // actually generated, matched by an intrinsic:
2987 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
2988 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
2989 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
2990 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
2992 // Branch indirect and set link. This is the "X-form" address version of a
2995 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
2998 // Unconditional branches:
2999 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
3001 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3005 // Unconditional, absolute address branch
3007 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3009 [/* no pattern */]>;
3013 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3015 // Various branches:
3017 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
3018 "brnz\t$rCond,$dest",
3020 [(brcond R32C:$rCond, bb:$dest)]>;
3023 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
3026 [/* no pattern */]>;
3029 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
3030 "brhnz\t$rCond,$dest",
3032 [(brcond R16C:$rCond, bb:$dest)]>;
3035 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
3038 [/* no pattern */]>;
3042 BICondForm<0b10010100100, "binz\t$rA, $func",
3043 [(SPUbinz R32C:$rA, R32C:$func)]>;
3046 BICondForm<0b00010100100, "biz\t$rA, $func",
3047 [(SPUbiz R32C:$rA, R32C:$func)]>;
3051 //===----------------------------------------------------------------------===//
3052 // setcc and brcond patterns:
3053 //===----------------------------------------------------------------------===//
3055 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3056 (BRHZ R16C:$rA, bb:$dest)>;
3057 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3058 (BRHNZ R16C:$rA, bb:$dest)>;
3060 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3061 (BRZ R32C:$rA, bb:$dest)>;
3062 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3063 (BRNZ R32C:$rA, bb:$dest)>;
3065 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3067 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3068 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3070 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3071 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3073 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3074 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3076 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3077 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3080 defm BRCONDeq : BranchCondEQ<seteq, BRHZ, BRZ>;
3081 defm BRCONDne : BranchCondEQ<setne, BRHNZ, BRNZ>;
3083 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3085 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3086 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3088 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3089 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3091 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3092 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3094 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3095 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3098 defm BRCONDugt : BranchCondLGT<setugt, BRHNZ, BRNZ>;
3099 defm BRCONDule : BranchCondLGT<setule, BRHZ, BRZ>;
3101 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3102 SPUInstr orinst32, SPUInstr brinst32>
3104 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3105 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3106 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3109 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3110 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3111 (CEQHr16 R16C:$rA, R16:$rB)),
3114 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3115 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3116 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3119 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3120 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3121 (CEQr32 R32C:$rA, R32C:$rB)),
3125 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZ, ORr32, BRNZ>;
3126 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZ, ORr32, BRZ>;
3128 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3130 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3131 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3133 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3134 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3136 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3137 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3139 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3140 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3143 defm BRCONDgt : BranchCondGT<setgt, BRHNZ, BRNZ>;
3144 defm BRCONDle : BranchCondGT<setle, BRHZ, BRZ>;
3146 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3147 SPUInstr orinst32, SPUInstr brinst32>
3149 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3150 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3151 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3154 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3155 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3156 (CEQHr16 R16C:$rA, R16:$rB)),
3159 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3160 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3161 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3164 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3165 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3166 (CEQr32 R32C:$rA, R32C:$rB)),
3170 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZ, ORr32, BRNZ>;
3171 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZ, ORr32, BRZ>;
3173 let isTerminator = 1, isBarrier = 1 in {
3174 let isReturn = 1 in {
3176 RETForm<"bi\t$$lr", [(retflag)]>;
3180 //===----------------------------------------------------------------------===//
3181 // Single precision floating point instructions
3182 //===----------------------------------------------------------------------===//
3185 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3186 "fa\t$rT, $rA, $rB", SPrecFP,
3187 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3190 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3191 "fa\t$rT, $rA, $rB", SPrecFP,
3192 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3195 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3196 "fs\t$rT, $rA, $rB", SPrecFP,
3197 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3200 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3201 "fs\t$rT, $rA, $rB", SPrecFP,
3202 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3204 // Floating point reciprocal estimate
3206 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
3207 "frest\t$rT, $rA", SPrecFP,
3208 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
3211 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
3212 "frest\t$rT, $rA", SPrecFP,
3213 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
3215 // Floating point interpolate (used in conjunction with reciprocal estimate)
3217 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3218 "fi\t$rT, $rA, $rB", SPrecFP,
3219 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
3220 (v4f32 VECREG:$rB)))]>;
3223 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3224 "fi\t$rT, $rA, $rB", SPrecFP,
3225 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
3227 // Floating Compare Equal
3229 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3230 "fceq\t$rT, $rA, $rB", SPrecFP,
3231 [(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
3234 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3235 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3236 [(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3239 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3240 "fcgt\t$rT, $rA, $rB", SPrecFP,
3241 [(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
3244 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3245 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3246 [(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3248 // FP Status and Control Register Write
3249 // Why isn't rT a don't care in the ISA?
3250 // Should we create a special RRForm_3 for this guy and zero out the rT?
3252 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3253 "fscrwr\t$rA", SPrecFP,
3254 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3256 // FP Status and Control Register Read
3258 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3259 "fscrrd\t$rT", SPrecFP,
3260 [/* This instruction requires an intrinsic */]>;
3262 // llvm instruction space
3263 // How do these map onto cell instructions?
3265 // frest rC rB # c = 1/b (both lines)
3267 // fm rD rA rC # d = a * 1/b
3268 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3269 // fma rB rB rC rD # b = b * c + d
3270 // = -(d *b -a) * c + d
3271 // = a * c - c ( a *b *c - a)
3276 // These llvm instructions will actually map to library calls.
3277 // All that's needed, then, is to check that the appropriate library is
3278 // imported and do a brsl to the proper function name.
3279 // frem # fmod(x, y): x - (x/y) * y
3280 // (Note: fmod(double, double), fmodf(float,float)
3284 // Unimplemented SPU instruction space
3285 // floating reciprocal absolute square root estimate (frsqest)
3287 // The following are probably just intrinsics
3288 // status and control register write
3289 // status and control register read
3291 //--------------------------------------
3292 // Floating point multiply instructions
3293 //--------------------------------------
3296 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3297 "fm\t$rT, $rA, $rB", SPrecFP,
3298 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
3299 (v4f32 VECREG:$rB)))]>;
3302 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3303 "fm\t$rT, $rA, $rB", SPrecFP,
3304 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
3306 // Floating point multiply and add
3307 // e.g. d = c + (a * b)
3309 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3310 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3311 [(set (v4f32 VECREG:$rT),
3312 (fadd (v4f32 VECREG:$rC),
3313 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
3316 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3317 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3318 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3320 // FP multiply and subtract
3321 // Subtracts value in rC from product
3324 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3325 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3326 [(set (v4f32 VECREG:$rT),
3327 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
3328 (v4f32 VECREG:$rC)))]>;
3331 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3332 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3334 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
3336 // Floating Negative Mulitply and Subtract
3337 // Subtracts product from value in rC
3338 // res = fneg(fms a b c)
3341 // NOTE: subtraction order
3345 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3346 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3347 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3350 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3351 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3352 [(set (v4f32 VECREG:$rT),
3353 (fsub (v4f32 VECREG:$rC),
3354 (fmul (v4f32 VECREG:$rA),
3355 (v4f32 VECREG:$rB))))]>;
3357 //--------------------------------------
3358 // Floating Point Conversions
3359 // Signed conversions:
3361 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3362 "csflt\t$rT, $rA, 0", SPrecFP,
3363 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
3365 // Convert signed integer to floating point
3367 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
3368 "csflt\t$rT, $rA, 0", SPrecFP,
3369 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
3371 // Convert unsigned into to float
3373 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3374 "cuflt\t$rT, $rA, 0", SPrecFP,
3375 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
3378 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
3379 "cuflt\t$rT, $rA, 0", SPrecFP,
3380 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
3382 // Convert float to unsigned int
3383 // Assume that scale = 0
3386 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3387 "cfltu\t$rT, $rA, 0", SPrecFP,
3388 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
3391 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3392 "cfltu\t$rT, $rA, 0", SPrecFP,
3393 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
3395 // Convert float to signed int
3396 // Assume that scale = 0
3399 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3400 "cflts\t$rT, $rA, 0", SPrecFP,
3401 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
3404 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3405 "cflts\t$rT, $rA, 0", SPrecFP,
3406 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
3408 //===----------------------------------------------------------------------==//
3409 // Single<->Double precision conversions
3410 //===----------------------------------------------------------------------==//
3412 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
3413 // v4f32, output is v2f64--which goes in the name?)
3415 // Floating point extend single to double
3416 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
3417 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
3420 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3421 "fesd\t$rT, $rA", SPrecFP,
3422 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
3425 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
3426 "fesd\t$rT, $rA", SPrecFP,
3427 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
3429 // Floating point round double to single
3431 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3432 // "frds\t$rT, $rA,", SPrecFP,
3433 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
3436 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
3437 "frds\t$rT, $rA", SPrecFP,
3438 [(set R32FP:$rT, (fround R64FP:$rA))]>;
3440 //ToDo include anyextend?
3442 //===----------------------------------------------------------------------==//
3443 // Double precision floating point instructions
3444 //===----------------------------------------------------------------------==//
3446 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3447 "dfa\t$rT, $rA, $rB", DPrecFP,
3448 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
3451 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3452 "dfa\t$rT, $rA, $rB", DPrecFP,
3453 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3456 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3457 "dfs\t$rT, $rA, $rB", DPrecFP,
3458 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
3461 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3462 "dfs\t$rT, $rA, $rB", DPrecFP,
3463 [(set (v2f64 VECREG:$rT),
3464 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3467 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3468 "dfm\t$rT, $rA, $rB", DPrecFP,
3469 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
3472 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3473 "dfm\t$rT, $rA, $rB", DPrecFP,
3474 [(set (v2f64 VECREG:$rT),
3475 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3478 RRForm<0b00111010110, (outs R64FP:$rT),
3479 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3480 "dfma\t$rT, $rA, $rB", DPrecFP,
3481 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3482 RegConstraint<"$rC = $rT">,
3486 RRForm<0b00111010110, (outs VECREG:$rT),
3487 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3488 "dfma\t$rT, $rA, $rB", DPrecFP,
3489 [(set (v2f64 VECREG:$rT),
3490 (fadd (v2f64 VECREG:$rC),
3491 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
3492 RegConstraint<"$rC = $rT">,
3496 RRForm<0b10111010110, (outs R64FP:$rT),
3497 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3498 "dfms\t$rT, $rA, $rB", DPrecFP,
3499 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
3500 RegConstraint<"$rC = $rT">,
3504 RRForm<0b10111010110, (outs VECREG:$rT),
3505 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3506 "dfms\t$rT, $rA, $rB", DPrecFP,
3507 [(set (v2f64 VECREG:$rT),
3508 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3509 (v2f64 VECREG:$rC)))]>;
3511 // FNMS: - (a * b - c)
3512 // - (a * b) + c => c - (a * b)
3514 RRForm<0b01111010110, (outs R64FP:$rT),
3515 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3516 "dfnms\t$rT, $rA, $rB", DPrecFP,
3517 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3518 RegConstraint<"$rC = $rT">,
3521 def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
3522 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
3525 RRForm<0b01111010110, (outs VECREG:$rT),
3526 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3527 "dfnms\t$rT, $rA, $rB", DPrecFP,
3528 [(set (v2f64 VECREG:$rT),
3529 (fsub (v2f64 VECREG:$rC),
3530 (fmul (v2f64 VECREG:$rA),
3531 (v2f64 VECREG:$rB))))]>,
3532 RegConstraint<"$rC = $rT">,
3535 def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3536 (v2f64 VECREG:$rC))),
3537 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
3542 RRForm<0b11111010110, (outs R64FP:$rT),
3543 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3544 "dfnma\t$rT, $rA, $rB", DPrecFP,
3545 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
3546 RegConstraint<"$rC = $rT">,
3550 RRForm<0b11111010110, (outs VECREG:$rT),
3551 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3552 "dfnma\t$rT, $rA, $rB", DPrecFP,
3553 [(set (v2f64 VECREG:$rT),
3554 (fneg (fadd (v2f64 VECREG:$rC),
3555 (fmul (v2f64 VECREG:$rA),
3556 (v2f64 VECREG:$rB)))))]>,
3557 RegConstraint<"$rC = $rT">,
3560 //===----------------------------------------------------------------------==//
3561 // Floating point negation and absolute value
3562 //===----------------------------------------------------------------------==//
3564 def : Pat<(fneg (v4f32 VECREG:$rA)),
3565 (XORfnegvec (v4f32 VECREG:$rA),
3566 (v4f32 (ILHUv4i32 0x8000)))>;
3568 def : Pat<(fneg R32FP:$rA),
3569 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
3571 def : Pat<(fneg (v2f64 VECREG:$rA)),
3572 (XORfnegvec (v2f64 VECREG:$rA),
3573 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
3575 def : Pat<(fneg R64FP:$rA),
3576 (XORfneg64 R64FP:$rA,
3577 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
3579 // Floating point absolute value
3581 def : Pat<(fabs R32FP:$rA),
3582 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
3584 def : Pat<(fabs (v4f32 VECREG:$rA)),
3585 (ANDfabsvec (v4f32 VECREG:$rA),
3586 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3588 def : Pat<(fabs R64FP:$rA),
3589 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
3591 def : Pat<(fabs (v2f64 VECREG:$rA)),
3592 (ANDfabsvec (v2f64 VECREG:$rA),
3593 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3595 //===----------------------------------------------------------------------===//
3596 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
3597 // in the odd pipeline)
3598 //===----------------------------------------------------------------------===//
3600 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
3603 let Inst{0-10} = 0b10000000010;
3604 let Inst{11-17} = 0;
3605 let Inst{18-24} = 0;
3606 let Inst{25-31} = 0;
3609 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
3612 let Inst{0-10} = 0b10000000000;
3613 let Inst{11-17} = 0;
3614 let Inst{18-24} = 0;
3615 let Inst{25-31} = 0;
3618 //===----------------------------------------------------------------------===//
3619 // Bit conversions (type conversions between vector/packed types)
3620 // NOTE: Promotions are handled using the XS* instructions. Truncation
3622 //===----------------------------------------------------------------------===//
3623 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3624 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3625 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3626 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3627 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3629 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3630 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3631 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3632 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3633 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3635 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3636 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3637 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3638 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3639 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3641 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3642 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3643 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3644 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3645 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3647 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3648 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3649 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3650 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3651 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3653 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3654 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3655 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3656 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3657 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3659 def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3660 def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
3662 //===----------------------------------------------------------------------===//
3663 // Instruction patterns:
3664 //===----------------------------------------------------------------------===//
3666 // General 32-bit constants:
3667 def : Pat<(i32 imm:$imm),
3668 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3670 // Single precision float constants:
3671 def : Pat<(f32 fpimm:$imm),
3672 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3674 // General constant 32-bit vectors
3675 def : Pat<(v4i32 v4i32Imm:$imm),
3676 (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
3677 (LO16_vec v4i32Imm:$imm))>;
3680 def : Pat<(i8 imm:$imm),
3683 //===----------------------------------------------------------------------===//
3684 // Call instruction patterns:
3685 //===----------------------------------------------------------------------===//
3690 //===----------------------------------------------------------------------===//
3691 // Zero/Any/Sign extensions
3692 //===----------------------------------------------------------------------===//
3694 // zext 1->32: Zero extend i1 to i32
3695 def : Pat<(SPUextract_i1_zext R32C:$rSrc),
3696 (ANDIr32 R32C:$rSrc, 0x1)>;
3698 // sext 8->32: Sign extend bytes to words
3699 def : Pat<(sext_inreg R32C:$rSrc, i8),
3700 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
3702 def : Pat<(i32 (sext R8C:$rSrc)),
3703 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
3705 def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
3706 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
3707 (v4i32 VECREG:$rSrc))))>;
3709 // zext 8->16: Zero extend bytes to halfwords
3710 def : Pat<(i16 (zext R8C:$rSrc)),
3711 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
3713 // zext 8->32 from preferred slot in load/store
3714 def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
3715 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
3718 // zext 8->32: Zero extend bytes to words
3719 def : Pat<(i32 (zext R8C:$rSrc)),
3720 (ANDIi8i32 R8C:$rSrc, 0xff)>;
3722 // anyext 8->16: Extend 8->16 bits, irrespective of sign
3723 def : Pat<(i16 (anyext R8C:$rSrc)),
3724 (ORHIi8i16 R8C:$rSrc, 0)>;
3726 // anyext 8->32: Extend 8->32 bits, irrespective of sign
3727 def : Pat<(i32 (anyext R8C:$rSrc)),
3728 (ORIi8i32 R8C:$rSrc, 0)>;
3730 // zext 16->32: Zero extend halfwords to words
3731 def : Pat<(i32 (zext R16C:$rSrc)),
3732 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
3734 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
3735 (ANDIi16i32 R16C:$rSrc, 0xf)>;
3737 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
3738 (ANDIi16i32 R16C:$rSrc, 0xff)>;
3740 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
3741 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
3743 // anyext 16->32: Extend 16->32 bits, irrespective of sign
3744 def : Pat<(i32 (anyext R16C:$rSrc)),
3745 (ORIi16i32 R16C:$rSrc, 0)>;
3747 //===----------------------------------------------------------------------===//
3748 // Address generation: SPU, like PPC, has to split addresses into high and
3749 // low parts in order to load them into a register.
3750 //===----------------------------------------------------------------------===//
3752 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
3753 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
3754 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
3755 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
3757 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
3758 (SPUlo tglobaladdr:$in, 0)),
3759 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
3761 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
3762 (SPUlo texternalsym:$in, 0)),
3763 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
3765 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
3766 (SPUlo tjumptable:$in, 0)),
3767 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
3769 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
3770 (SPUlo tconstpool:$in, 0)),
3771 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
3773 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
3774 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
3776 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
3777 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
3779 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
3780 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
3782 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
3783 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
3786 include "CellSDKIntrinsics.td"