1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start imm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end imm:$amt)]>;
33 //===----------------------------------------------------------------------===//
34 // DWARF debugging Pseudo Instructions
35 //===----------------------------------------------------------------------===//
37 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
38 "${:comment} .loc $file, $line, $col",
39 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
42 //===----------------------------------------------------------------------===//
44 // NB: The ordering is actually important, since the instruction selection
45 // will try each of the instructions in sequence, i.e., the D-form first with
46 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
47 // finally the X-form with the register-register.
48 //===----------------------------------------------------------------------===//
50 let isSimpleLoad = 1 in {
51 class LoadDFormVec<ValueType vectype>
52 : RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
55 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
58 class LoadDForm<RegisterClass rclass>
59 : RI10Form<0b00101100, (outs rclass:$rT), (ins memri10:$src),
62 [(set rclass:$rT, (load dform_addr:$src))]>
67 def v16i8: LoadDFormVec<v16i8>;
68 def v8i16: LoadDFormVec<v8i16>;
69 def v4i32: LoadDFormVec<v4i32>;
70 def v2i64: LoadDFormVec<v2i64>;
71 def v4f32: LoadDFormVec<v4f32>;
72 def v2f64: LoadDFormVec<v2f64>;
74 def r128: LoadDForm<GPRC>;
75 def r64: LoadDForm<R64C>;
76 def r32: LoadDForm<R32C>;
77 def f32: LoadDForm<R32FP>;
78 def f64: LoadDForm<R64FP>;
79 def r16: LoadDForm<R16C>;
80 def r8: LoadDForm<R8C>;
83 class LoadAFormVec<ValueType vectype>
84 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
87 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
90 class LoadAForm<RegisterClass rclass>
91 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
94 [(set rclass:$rT, (load aform_addr:$src))]>
99 def v16i8: LoadAFormVec<v16i8>;
100 def v8i16: LoadAFormVec<v8i16>;
101 def v4i32: LoadAFormVec<v4i32>;
102 def v2i64: LoadAFormVec<v2i64>;
103 def v4f32: LoadAFormVec<v4f32>;
104 def v2f64: LoadAFormVec<v2f64>;
106 def r128: LoadAForm<GPRC>;
107 def r64: LoadAForm<R64C>;
108 def r32: LoadAForm<R32C>;
109 def f32: LoadAForm<R32FP>;
110 def f64: LoadAForm<R64FP>;
111 def r16: LoadAForm<R16C>;
112 def r8: LoadAForm<R8C>;
115 class LoadXFormVec<ValueType vectype>
116 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
119 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
122 class LoadXForm<RegisterClass rclass>
123 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
126 [(set rclass:$rT, (load xform_addr:$src))]>
129 multiclass LoadXForms
131 def v16i8: LoadXFormVec<v16i8>;
132 def v8i16: LoadXFormVec<v8i16>;
133 def v4i32: LoadXFormVec<v4i32>;
134 def v2i64: LoadXFormVec<v2i64>;
135 def v4f32: LoadXFormVec<v4f32>;
136 def v2f64: LoadXFormVec<v2f64>;
138 def r128: LoadXForm<GPRC>;
139 def r64: LoadXForm<R64C>;
140 def r32: LoadXForm<R32C>;
141 def f32: LoadXForm<R32FP>;
142 def f64: LoadXForm<R64FP>;
143 def r16: LoadXForm<R16C>;
144 def r8: LoadXForm<R8C>;
147 defm LQA : LoadAForms;
148 defm LQD : LoadDForms;
149 defm LQX : LoadXForms;
151 /* Load quadword, PC relative: Not much use at this point in time.
152 Might be of use later for relocatable code. It's effectively the
153 same as LQA, but uses PC-relative addressing.
154 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
155 "lqr\t$rT, $disp", LoadStore,
156 [(set VECREG:$rT, (load iaddr:$disp))]>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
163 class StoreDFormVec<ValueType vectype>
164 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
167 [(store (vectype VECREG:$rT), dform_addr:$src)]>
170 class StoreDForm<RegisterClass rclass>
171 : RI10Form<0b00100100, (outs), (ins rclass:$rT, memri10:$src),
174 [(store rclass:$rT, dform_addr:$src)]>
177 multiclass StoreDForms
179 def v16i8: StoreDFormVec<v16i8>;
180 def v8i16: StoreDFormVec<v8i16>;
181 def v4i32: StoreDFormVec<v4i32>;
182 def v2i64: StoreDFormVec<v2i64>;
183 def v4f32: StoreDFormVec<v4f32>;
184 def v2f64: StoreDFormVec<v2f64>;
186 def r128: StoreDForm<GPRC>;
187 def r64: StoreDForm<R64C>;
188 def r32: StoreDForm<R32C>;
189 def f32: StoreDForm<R32FP>;
190 def f64: StoreDForm<R64FP>;
191 def r16: StoreDForm<R16C>;
192 def r8: StoreDForm<R8C>;
195 class StoreAFormVec<ValueType vectype>
196 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
199 [(store (vectype VECREG:$rT), aform_addr:$src)]>;
201 class StoreAForm<RegisterClass rclass>
202 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
205 [(store rclass:$rT, aform_addr:$src)]>;
207 multiclass StoreAForms
209 def v16i8: StoreAFormVec<v16i8>;
210 def v8i16: StoreAFormVec<v8i16>;
211 def v4i32: StoreAFormVec<v4i32>;
212 def v2i64: StoreAFormVec<v2i64>;
213 def v4f32: StoreAFormVec<v4f32>;
214 def v2f64: StoreAFormVec<v2f64>;
216 def r128: StoreAForm<GPRC>;
217 def r64: StoreAForm<R64C>;
218 def r32: StoreAForm<R32C>;
219 def f32: StoreAForm<R32FP>;
220 def f64: StoreAForm<R64FP>;
221 def r16: StoreAForm<R16C>;
222 def r8: StoreAForm<R8C>;
225 class StoreXFormVec<ValueType vectype>
226 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
229 [(store (vectype VECREG:$rT), xform_addr:$src)]>
232 class StoreXForm<RegisterClass rclass>
233 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
236 [(store rclass:$rT, xform_addr:$src)]>
239 multiclass StoreXForms
241 def v16i8: StoreXFormVec<v16i8>;
242 def v8i16: StoreXFormVec<v8i16>;
243 def v4i32: StoreXFormVec<v4i32>;
244 def v2i64: StoreXFormVec<v2i64>;
245 def v4f32: StoreXFormVec<v4f32>;
246 def v2f64: StoreXFormVec<v2f64>;
248 def r128: StoreXForm<GPRC>;
249 def r64: StoreXForm<R64C>;
250 def r32: StoreXForm<R32C>;
251 def f32: StoreXForm<R32FP>;
252 def f64: StoreXForm<R64FP>;
253 def r16: StoreXForm<R16C>;
254 def r8: StoreXForm<R8C>;
257 defm STQD : StoreDForms;
258 defm STQA : StoreAForms;
259 defm STQX : StoreXForms;
261 /* Store quadword, PC relative: Not much use at this point in time. Might
262 be useful for relocatable code.
263 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
264 "stqr\t$rT, $disp", LoadStore,
265 [(store VECREG:$rT, iaddr:$disp)]>;
268 //===----------------------------------------------------------------------===//
269 // Generate Controls for Insertion:
270 //===----------------------------------------------------------------------===//
273 RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
274 "cbd\t$rT, $src", ShuffleOp,
275 [(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
277 def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
278 "cbx\t$rT, $src", ShuffleOp,
279 [(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
281 def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
282 "chd\t$rT, $src", ShuffleOp,
283 [(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
285 def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
286 "chx\t$rT, $src", ShuffleOp,
287 [(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
289 def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
290 "cwd\t$rT, $src", ShuffleOp,
291 [(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
293 def CWDf32 : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
294 "cwd\t$rT, $src", ShuffleOp,
295 [(set (v4f32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
297 def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
298 "cwx\t$rT, $src", ShuffleOp,
299 [(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
301 def CWXf32 : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
302 "cwx\t$rT, $src", ShuffleOp,
303 [(set (v4f32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
305 def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
306 "cdd\t$rT, $src", ShuffleOp,
307 [(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
309 def CDDf64 : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
310 "cdd\t$rT, $src", ShuffleOp,
311 [(set (v2f64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
313 def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
314 "cdx\t$rT, $src", ShuffleOp,
315 [(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
317 def CDXf64 : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
318 "cdx\t$rT, $src", ShuffleOp,
319 [(set (v2f64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
321 //===----------------------------------------------------------------------===//
322 // Constant formation:
323 //===----------------------------------------------------------------------===//
326 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
327 "ilh\t$rT, $val", ImmLoad,
328 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
331 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
332 "ilh\t$rT, $val", ImmLoad,
333 [(set R16C:$rT, immSExt16:$val)]>;
335 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
336 // the right constant")
338 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
339 "ilh\t$rT, $val", ImmLoad,
340 [(set R8C:$rT, immSExt8:$val)]>;
342 // IL does sign extension!
344 class ILInst<dag OOL, dag IOL, list<dag> pattern>:
345 RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val",
348 class ILVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
349 ILInst<(outs VECREG:$rT), (ins immtype:$val),
350 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
352 class ILRegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
353 ILInst<(outs rclass:$rT), (ins immtype:$val),
354 [(set rclass:$rT, xform:$val)]>;
356 multiclass ImmediateLoad
358 def v2i64: ILVecInst<v2i64, s16imm_i64, v2i64SExt16Imm>;
359 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
361 // TODO: Need v2f64, v4f32
363 def r64: ILRegInst<R64C, s16imm_i64, immSExt16>;
364 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
365 def f32: ILRegInst<R32FP, s16imm_f32, fpimmSExt16>;
366 def f64: ILRegInst<R64FP, s16imm_f64, fpimmSExt16>;
369 defm IL : ImmediateLoad;
371 class ILHUInst<dag OOL, dag IOL, list<dag> pattern>:
372 RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val",
375 class ILHUVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
376 ILHUInst<(outs VECREG:$rT), (ins immtype:$val),
377 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
379 class ILHURegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
380 ILHUInst<(outs rclass:$rT), (ins immtype:$val),
381 [(set rclass:$rT, xform:$val)]>;
383 multiclass ImmLoadHalfwordUpper
385 def v2i64: ILHUVecInst<v2i64, u16imm_i64, immILHUvec_i64>;
386 def v4i32: ILHUVecInst<v4i32, u16imm_i32, immILHUvec>;
388 def r64: ILHURegInst<R64C, u16imm_i64, hi16>;
389 def r32: ILHURegInst<R32C, u16imm_i32, hi16>;
391 // Loads the high portion of an address
392 def hi: ILHURegInst<R32C, symbolHi, hi16>;
394 // Used in custom lowering constant SFP loads:
395 def f32: ILHURegInst<R32FP, f16imm, hi16_f32>;
398 defm ILHU : ImmLoadHalfwordUpper;
400 // Immediate load address (can also be used to load 18-bit unsigned constants,
401 // see the zext 16->32 pattern)
403 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
404 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
407 class ILAVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
408 ILAInst<(outs VECREG:$rT), (ins immtype:$val),
409 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
411 class ILARegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
412 ILAInst<(outs rclass:$rT), (ins immtype:$val),
413 [(set rclass:$rT, xform:$val)]>;
415 multiclass ImmLoadAddress
417 def v2i64: ILAVecInst<v2i64, u18imm, v2i64Uns18Imm>;
418 def v4i32: ILAVecInst<v4i32, u18imm, v4i32Uns18Imm>;
420 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
421 def r32: ILARegInst<R32C, u18imm, imm18>;
422 def f32: ILARegInst<R32FP, f18imm, fpimm18>;
423 def f64: ILARegInst<R64FP, f18imm_f64, fpimm18>;
425 def lo: ILARegInst<R32C, symbolLo, imm18>;
427 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
431 defm ILA : ImmLoadAddress;
433 // Immediate OR, Halfword Lower: The "other" part of loading large constants
434 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
435 // Note that these are really two operand instructions, but they're encoded
436 // as three operands with the first two arguments tied-to each other.
438 class IOHLInst<dag OOL, dag IOL, list<dag> pattern>:
439 RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val",
441 RegConstraint<"$rS = $rT">,
444 class IOHLVecInst<ValueType vectype, Operand immtype /* , PatLeaf xform */>:
445 IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val),
448 class IOHLRegInst<RegisterClass rclass, Operand immtype /* , PatLeaf xform */>:
449 IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val),
452 multiclass ImmOrHalfwordLower
454 def v2i64: IOHLVecInst<v2i64, u16imm_i64>;
455 def v4i32: IOHLVecInst<v4i32, u16imm_i32>;
457 def r32: IOHLRegInst<R32C, i32imm>;
458 def f32: IOHLRegInst<R32FP, f32imm>;
460 def lo: IOHLRegInst<R32C, symbolLo>;
463 defm IOHL: ImmOrHalfwordLower;
465 // Form select mask for bytes using immediate, used in conjunction with the
468 class FSMBIVec<ValueType vectype>:
469 RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
472 [(set (vectype VECREG:$rT), (SPUselmask (i16 immU16:$val)))]>;
474 multiclass FormSelectMaskBytesImm
476 def v16i8: FSMBIVec<v16i8>;
477 def v8i16: FSMBIVec<v8i16>;
478 def v4i32: FSMBIVec<v4i32>;
479 def v2i64: FSMBIVec<v2i64>;
482 defm FSMBI : FormSelectMaskBytesImm;
484 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
486 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
487 "fsmb\t$rT, $rA", SelectOp,
488 [(set (v16i8 VECREG:$rT), (SPUselmask R16C:$rA))]>;
490 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
491 // only 8-bits wide (even though it's input as 16-bits here)
493 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
494 "fsmh\t$rT, $rA", SelectOp,
495 [(set (v8i16 VECREG:$rT), (SPUselmask R16C:$rA))]>;
497 // fsm: Form select mask for words. Like the other fsm* instructions,
498 // only the lower 4 bits of $rA are significant.
499 class FSMInst<ValueType vectype, RegisterClass rclass>:
500 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins rclass:$rA),
503 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
505 multiclass FormSelectMaskWord {
506 def r32 : FSMInst<v4i32, R32C>;
507 def r16 : FSMInst<v4i32, R16C>;
510 defm FSM : FormSelectMaskWord;
512 // Special case when used for i64 math operations
513 multiclass FormSelectMaskWord64 {
514 def r32 : FSMInst<v2i64, R32C>;
515 def r16 : FSMInst<v2i64, R16C>;
518 defm FSM64 : FormSelectMaskWord64;
520 //===----------------------------------------------------------------------===//
521 // Integer and Logical Operations:
522 //===----------------------------------------------------------------------===//
525 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
526 "ah\t$rT, $rA, $rB", IntegerOp,
527 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
529 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
530 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
533 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
534 "ah\t$rT, $rA, $rB", IntegerOp,
535 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
538 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
539 "ahi\t$rT, $rA, $val", IntegerOp,
540 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
541 v8i16SExt10Imm:$val))]>;
544 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
545 "ahi\t$rT, $rA, $val", IntegerOp,
546 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
549 RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
550 "a\t$rT, $rA, $rB", IntegerOp,
551 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
553 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
554 (Avec VECREG:$rA, VECREG:$rB)>;
557 RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
558 "a\t$rT, $rA, $rB", IntegerOp,
559 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
562 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
563 "a\t$rT, $rA, $rB", IntegerOp,
567 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
568 "ai\t$rT, $rA, $val", IntegerOp,
569 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
570 v4i32SExt10Imm:$val))]>;
573 RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
574 "ai\t$rT, $rA, $val", IntegerOp,
575 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
578 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
579 "sfh\t$rT, $rA, $rB", IntegerOp,
580 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
581 (v8i16 VECREG:$rB)))]>;
584 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
585 "sfh\t$rT, $rA, $rB", IntegerOp,
586 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
589 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
590 "sfhi\t$rT, $rA, $val", IntegerOp,
591 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
592 (v8i16 VECREG:$rA)))]>;
594 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
595 "sfhi\t$rT, $rA, $val", IntegerOp,
596 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
598 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
599 (ins VECREG:$rA, VECREG:$rB),
600 "sf\t$rT, $rA, $rB", IntegerOp,
601 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
603 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
604 "sf\t$rT, $rA, $rB", IntegerOp,
605 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
608 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
609 "sfi\t$rT, $rA, $val", IntegerOp,
610 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
611 (v4i32 VECREG:$rA)))]>;
613 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
614 (ins R32C:$rA, s10imm_i32:$val),
615 "sfi\t$rT, $rA, $val", IntegerOp,
616 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
618 // ADDX: only available in vector form, doesn't match a pattern.
619 class ADDXInst<dag OOL, dag IOL, list<dag> pattern>:
620 RRForm<0b00000010110, OOL, IOL,
621 "addx\t$rT, $rA, $rB",
624 class ADDXVecInst<ValueType vectype>:
625 ADDXInst<(outs VECREG:$rT),
626 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
627 [(set (vectype VECREG:$rT),
628 (SPUaddx (vectype VECREG:$rA), (vectype VECREG:$rB),
629 (vectype VECREG:$rCarry)))]>,
630 RegConstraint<"$rCarry = $rT">,
633 class ADDXRegInst<RegisterClass rclass>:
634 ADDXInst<(outs rclass:$rT),
635 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
637 (SPUaddx rclass:$rA, rclass:$rB, rclass:$rCarry))]>,
638 RegConstraint<"$rCarry = $rT">,
641 multiclass AddExtended {
642 def v2i64 : ADDXVecInst<v2i64>;
643 def v4i32 : ADDXVecInst<v4i32>;
644 def r64 : ADDXRegInst<R64C>;
645 def r32 : ADDXRegInst<R32C>;
648 defm ADDX : AddExtended;
650 // CG: Generate carry for add
651 class CGInst<dag OOL, dag IOL, list<dag> pattern>:
652 RRForm<0b01000011000, OOL, IOL,
656 class CGVecInst<ValueType vectype>:
657 CGInst<(outs VECREG:$rT),
658 (ins VECREG:$rA, VECREG:$rB),
659 [(set (vectype VECREG:$rT),
660 (SPUcarry_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
662 class CGRegInst<RegisterClass rclass>:
663 CGInst<(outs rclass:$rT),
664 (ins rclass:$rA, rclass:$rB),
666 (SPUcarry_gen rclass:$rA, rclass:$rB))]>;
668 multiclass CarryGenerate {
669 def v2i64 : CGVecInst<v2i64>;
670 def v4i32 : CGVecInst<v4i32>;
671 def r64 : CGRegInst<R64C>;
672 def r32 : CGRegInst<R32C>;
675 defm CG : CarryGenerate;
677 // SFX: Subract from, extended. This is used in conjunction with BG to subtract
678 // with carry (borrow, in this case)
679 class SFXInst<dag OOL, dag IOL, list<dag> pattern>:
680 RRForm<0b10000010110, OOL, IOL,
681 "sfx\t$rT, $rA, $rB",
684 class SFXVecInst<ValueType vectype>:
685 SFXInst<(outs VECREG:$rT),
686 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
687 [(set (vectype VECREG:$rT),
688 (SPUsubx (vectype VECREG:$rA), (vectype VECREG:$rB),
689 (vectype VECREG:$rCarry)))]>,
690 RegConstraint<"$rCarry = $rT">,
693 class SFXRegInst<RegisterClass rclass>:
694 SFXInst<(outs rclass:$rT),
695 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
697 (SPUsubx rclass:$rA, rclass:$rB, rclass:$rCarry))]>,
698 RegConstraint<"$rCarry = $rT">,
701 multiclass SubtractExtended {
702 def v2i64 : SFXVecInst<v2i64>;
703 def v4i32 : SFXVecInst<v4i32>;
704 def r64 : SFXRegInst<R64C>;
705 def r32 : SFXRegInst<R32C>;
708 defm SFX : SubtractExtended;
710 // BG: only available in vector form, doesn't match a pattern.
711 class BGInst<dag OOL, dag IOL, list<dag> pattern>:
712 RRForm<0b01000010000, OOL, IOL,
716 class BGVecInst<ValueType vectype>:
717 BGInst<(outs VECREG:$rT),
718 (ins VECREG:$rA, VECREG:$rB),
719 [(set (vectype VECREG:$rT),
720 (SPUborrow_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
722 class BGRegInst<RegisterClass rclass>:
723 BGInst<(outs rclass:$rT),
724 (ins rclass:$rA, rclass:$rB),
726 (SPUborrow_gen rclass:$rA, rclass:$rB))]>;
728 multiclass BorrowGenerate {
729 def v4i32 : BGVecInst<v4i32>;
730 def v2i64 : BGVecInst<v2i64>;
731 def r64 : BGRegInst<R64C>;
732 def r32 : BGRegInst<R32C>;
735 defm BG : BorrowGenerate;
737 // BGX: Borrow generate, extended.
739 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
741 "bgx\t$rT, $rA, $rB", IntegerOp,
743 RegConstraint<"$rCarry = $rT">,
746 // Halfword multiply variants:
747 // N.B: These can be used to build up larger quantities (16x16 -> 32)
750 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
751 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
752 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
753 (v8i16 VECREG:$rB)))]>;
756 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
757 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
758 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
761 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
762 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
763 [(set (v4i32 VECREG:$rT),
764 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
767 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
768 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
769 [(set R32C:$rT, (mul (zext R16C:$rA),
773 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
774 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
775 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
777 // mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
778 // this only produces the lower 16 bits)
780 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
781 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
782 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
785 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
786 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
787 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
789 // mpyui: same issues as other multiplies, plus, this doesn't match a
790 // pattern... but may be used during target DAG selection or lowering
792 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
793 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
797 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
798 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
801 // mpya: 16 x 16 + 16 -> 32 bit result
803 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
804 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
805 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
806 (v8i16 VECREG:$rB)))),
807 (v4i32 VECREG:$rC)))]>;
810 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
811 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
812 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
815 def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
816 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
818 def MPYAr32_sextinreg:
819 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
820 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
821 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
822 (sext_inreg R32C:$rB, i16)),
826 // RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
827 // "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
828 // [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
831 // mpyh: multiply high, used to synthesize 32-bit multiplies
833 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
834 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
835 [(set (v4i32 VECREG:$rT),
836 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
839 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
840 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
841 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
843 // mpys: multiply high and shift right (returns the top half of
844 // a 16-bit multiply, sign extended to 32 bits.)
846 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
847 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
851 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
852 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
855 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
856 // the top 16 bits of the $rA, $rB)
858 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
859 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
860 [(set (v8i16 VECREG:$rT),
861 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
864 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
865 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
868 // mpyhha: Multiply high-high, add to $rT:
870 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
871 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
875 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
876 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
879 // mpyhhu: Multiply high-high, unsigned
881 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
882 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
886 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
887 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
890 // mpyhhau: Multiply high-high, unsigned
892 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
893 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
897 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
898 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
901 // clz: Count leading zeroes
903 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
904 "clz\t$rT, $rA", IntegerOp,
908 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
909 "clz\t$rT, $rA", IntegerOp,
910 [(set R32C:$rT, (ctlz R32C:$rA))]>;
912 // cntb: Count ones in bytes (aka "population count")
913 // NOTE: This instruction is really a vector instruction, but the custom
914 // lowering code uses it in unorthodox ways to support CTPOP for other
917 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
918 "cntb\t$rT, $rA", IntegerOp,
919 [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>;
922 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
923 "cntb\t$rT, $rA", IntegerOp,
924 [(set (v8i16 VECREG:$rT), (SPUcntb (v8i16 VECREG:$rA)))]>;
927 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
928 "cntb\t$rT, $rA", IntegerOp,
929 [(set (v4i32 VECREG:$rT), (SPUcntb (v4i32 VECREG:$rA)))]>;
931 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
932 // quantity stored into $rT
934 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
935 "gbb\t$rT, $rA", GatherOp,
938 // gbh: Gather all low order bits from each halfword in $rA into a single
939 // 8-bit quantity stored in $rT
941 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
942 "gbh\t$rT, $rA", GatherOp,
945 // gb: Gather all low order bits from each word in $rA into a single
946 // 4-bit quantity stored in $rT
948 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
949 "gb\t$rT, $rA", GatherOp,
952 // avgb: average bytes
954 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
955 "avgb\t$rT, $rA, $rB", ByteOp,
958 // absdb: absolute difference of bytes
960 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
961 "absdb\t$rT, $rA, $rB", ByteOp,
964 // sumb: sum bytes into halfwords
966 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
967 "sumb\t$rT, $rA, $rB", ByteOp,
970 // Sign extension operations:
971 class XSBHInst<dag OOL, dag IOL, list<dag> pattern>:
972 RRForm_1<0b01101101010, OOL, IOL,
973 "xsbh\t$rDst, $rSrc",
976 class XSBHVecInst<ValueType vectype>:
977 XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
978 [(set (v8i16 VECREG:$rDst), (sext (vectype VECREG:$rSrc)))]>;
980 class XSBHRegInst<RegisterClass rclass>:
981 XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc),
982 [(set rclass:$rDst, (sext_inreg rclass:$rSrc, i8))]>;
984 multiclass ExtendByteHalfword {
985 def v16i8: XSBHVecInst<v8i16>;
986 def r16: XSBHRegInst<R16C>;
988 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
989 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
990 // pattern below). Intentionally doesn't match a pattern because we want the
991 // sext 8->32 pattern to do the work for us, namely because we need the extra
993 def r32: XSBHRegInst<R32C>;
996 defm XSBH : ExtendByteHalfword;
998 // Sign-extend, but take an 8-bit register to a 16-bit register (not done as
1001 XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc),
1002 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
1004 // Sign extend halfwords to words:
1006 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
1007 "xshw\t$rDest, $rSrc", IntegerOp,
1008 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
1011 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
1012 "xshw\t$rDst, $rSrc", IntegerOp,
1013 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
1016 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
1017 "xshw\t$rDst, $rSrc", IntegerOp,
1018 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
1021 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
1022 "xswd\t$rDst, $rSrc", IntegerOp,
1023 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
1026 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
1027 "xswd\t$rDst, $rSrc", IntegerOp,
1028 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
1031 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
1032 "xswd\t$rDst, $rSrc", IntegerOp,
1033 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
1035 def : Pat<(sext R32C:$inp),
1036 (XSWDr32 R32C:$inp)>;
1040 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
1041 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
1042 IntegerOp, pattern>;
1044 class ANDVecInst<ValueType vectype>:
1045 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1046 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1047 (vectype VECREG:$rB)))]>;
1049 class ANDRegInst<RegisterClass rclass>:
1050 ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1051 [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>;
1053 multiclass BitwiseAnd
1055 def v16i8: ANDVecInst<v16i8>;
1056 def v8i16: ANDVecInst<v8i16>;
1057 def v4i32: ANDVecInst<v4i32>;
1058 def v2i64: ANDVecInst<v2i64>;
1060 def r128: ANDRegInst<GPRC>;
1061 def r64: ANDRegInst<R64C>;
1062 def r32: ANDRegInst<R32C>;
1063 def r16: ANDRegInst<R16C>;
1064 def r8: ANDRegInst<R8C>;
1066 //===---------------------------------------------
1067 // Special instructions to perform the fabs instruction
1068 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1069 [/* Intentionally does not match a pattern */]>;
1071 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1072 [/* Intentionally does not match a pattern */]>;
1074 // Could use v4i32, but won't for clarity
1075 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1076 [/* Intentionally does not match a pattern */]>;
1078 //===---------------------------------------------
1080 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
1081 // quantities -- see 16->32 zext pattern.
1083 // This pattern is somewhat artificial, since it might match some
1084 // compiler generated pattern but it is unlikely to do so.
1086 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
1087 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
1090 defm AND : BitwiseAnd;
1092 // N.B.: vnot_conv is one of those special target selection pattern fragments,
1093 // in which we expect there to be a bit_convert on the constant. Bear in mind
1094 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
1095 // constant -1 vector.)
1097 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
1098 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
1099 IntegerOp, pattern>;
1101 class ANDCVecInst<ValueType vectype>:
1102 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1103 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1104 (vnot (vectype VECREG:$rB))))]>;
1106 class ANDCRegInst<RegisterClass rclass>:
1107 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1108 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
1110 multiclass AndComplement
1112 def v16i8: ANDCVecInst<v16i8>;
1113 def v8i16: ANDCVecInst<v8i16>;
1114 def v4i32: ANDCVecInst<v4i32>;
1115 def v2i64: ANDCVecInst<v2i64>;
1117 def r128: ANDCRegInst<GPRC>;
1118 def r64: ANDCRegInst<R64C>;
1119 def r32: ANDCRegInst<R32C>;
1120 def r16: ANDCRegInst<R16C>;
1121 def r8: ANDCRegInst<R8C>;
1124 defm ANDC : AndComplement;
1126 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1127 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1128 IntegerOp, pattern>;
1130 multiclass AndByteImm
1132 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1133 [(set (v16i8 VECREG:$rT),
1134 (and (v16i8 VECREG:$rA),
1135 (v16i8 v16i8U8Imm:$val)))]>;
1137 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1138 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1141 defm ANDBI : AndByteImm;
1143 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1144 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1145 IntegerOp, pattern>;
1147 multiclass AndHalfwordImm
1149 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1150 [(set (v8i16 VECREG:$rT),
1151 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1153 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1154 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1156 // Zero-extend i8 to i16:
1157 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1158 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1161 defm ANDHI : AndHalfwordImm;
1163 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1164 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1165 IntegerOp, pattern>;
1167 multiclass AndWordImm
1169 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1170 [(set (v4i32 VECREG:$rT),
1171 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1173 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1174 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1176 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1178 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1180 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1182 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1183 // zext 16->32 pattern below.
1185 // Note that this pattern is somewhat artificial, since it might match
1186 // something the compiler generates but is unlikely to occur in practice.
1187 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1189 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1192 defm ANDI : AndWordImm;
1194 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1195 // Bitwise OR group:
1196 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1198 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1199 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1200 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1201 IntegerOp, pattern>;
1203 class ORVecInst<ValueType vectype>:
1204 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1205 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1206 (vectype VECREG:$rB)))]>;
1208 class ORRegInst<RegisterClass rclass>:
1209 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1210 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1212 class ORPromoteScalar<RegisterClass rclass>:
1213 ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB),
1214 [/* no pattern */]>;
1216 class ORExtractElt<RegisterClass rclass>:
1217 ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB),
1218 [/* no pattern */]>;
1220 multiclass BitwiseOr
1222 def v16i8: ORVecInst<v16i8>;
1223 def v8i16: ORVecInst<v8i16>;
1224 def v4i32: ORVecInst<v4i32>;
1225 def v2i64: ORVecInst<v2i64>;
1227 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1228 [(set (v4f32 VECREG:$rT),
1229 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1230 (v4i32 VECREG:$rB)))))]>;
1232 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1233 [(set (v2f64 VECREG:$rT),
1234 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1235 (v2i64 VECREG:$rB)))))]>;
1237 def r64: ORRegInst<R64C>;
1238 def r32: ORRegInst<R32C>;
1239 def r16: ORRegInst<R16C>;
1240 def r8: ORRegInst<R8C>;
1242 // OR instructions used to copy f32 and f64 registers.
1243 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1244 [/* no pattern */]>;
1246 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1247 [/* no pattern */]>;
1249 // scalar->vector promotion:
1250 def v16i8_i8: ORPromoteScalar<R8C>;
1251 def v8i16_i16: ORPromoteScalar<R16C>;
1252 def v4i32_i32: ORPromoteScalar<R32C>;
1253 def v2i64_i64: ORPromoteScalar<R64C>;
1254 def v4f32_f32: ORPromoteScalar<R32FP>;
1255 def v2f64_f64: ORPromoteScalar<R64FP>;
1257 // extract element 0:
1258 def i8_v16i8: ORExtractElt<R8C>;
1259 def i16_v8i16: ORExtractElt<R16C>;
1260 def i32_v4i32: ORExtractElt<R32C>;
1261 def i64_v2i64: ORExtractElt<R64C>;
1262 def f32_v4f32: ORExtractElt<R32FP>;
1263 def f64_v2f64: ORExtractElt<R64FP>;
1266 defm OR : BitwiseOr;
1268 // scalar->vector promotion patterns:
1269 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
1270 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
1272 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1273 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1275 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1276 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1278 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1279 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1281 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1282 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1284 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1285 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1287 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1289 def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)),
1290 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1292 def : Pat<(SPUextract_elt0_chained (v16i8 VECREG:$rA)),
1293 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1295 def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
1296 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1298 def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
1299 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1301 def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
1302 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1304 def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
1305 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1307 def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
1308 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1310 def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
1311 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1313 def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
1314 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1316 def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
1317 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1319 def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
1320 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1322 def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
1323 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1325 // ORC: Bitwise "or" with complement (c = a | ~b)
1327 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1328 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1329 IntegerOp, pattern>;
1331 class ORCVecInst<ValueType vectype>:
1332 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1333 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1334 (vnot (vectype VECREG:$rB))))]>;
1336 class ORCRegInst<RegisterClass rclass>:
1337 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1338 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1340 multiclass BitwiseOrComplement
1342 def v16i8: ORCVecInst<v16i8>;
1343 def v8i16: ORCVecInst<v8i16>;
1344 def v4i32: ORCVecInst<v4i32>;
1345 def v2i64: ORCVecInst<v2i64>;
1347 def r64: ORCRegInst<R64C>;
1348 def r32: ORCRegInst<R32C>;
1349 def r16: ORCRegInst<R16C>;
1350 def r8: ORCRegInst<R8C>;
1353 defm ORC : BitwiseOrComplement;
1355 // OR byte immediate
1356 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1357 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1358 IntegerOp, pattern>;
1360 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1361 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1362 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1363 (vectype immpred:$val)))]>;
1365 multiclass BitwiseOrByteImm
1367 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1369 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1370 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1373 defm ORBI : BitwiseOrByteImm;
1375 // OR halfword immediate
1376 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1377 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1378 IntegerOp, pattern>;
1380 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1381 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1382 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1385 multiclass BitwiseOrHalfwordImm
1387 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1389 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1390 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1392 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1393 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1394 [(set R16C:$rT, (or (anyext R8C:$rA),
1395 i16ImmSExt10:$val))]>;
1398 defm ORHI : BitwiseOrHalfwordImm;
1400 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1401 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1402 IntegerOp, pattern>;
1404 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1405 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1406 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1409 // Bitwise "or" with immediate
1410 multiclass BitwiseOrImm
1412 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1414 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1415 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1417 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1418 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1419 // infra "anyext 16->32" pattern.)
1420 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1421 [(set R32C:$rT, (or (anyext R16C:$rA),
1422 i32ImmSExt10:$val))]>;
1424 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1425 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1426 // infra "anyext 16->32" pattern.)
1427 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1428 [(set R32C:$rT, (or (anyext R8C:$rA),
1429 i32ImmSExt10:$val))]>;
1432 defm ORI : BitwiseOrImm;
1434 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1435 // $rT[0], slots 1-3 are zeroed.
1437 // FIXME: Needs to match an intrinsic pattern.
1439 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1440 "orx\t$rT, $rA, $rB", IntegerOp,
1445 class XORInst<dag OOL, dag IOL, list<dag> pattern> :
1446 RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB",
1447 IntegerOp, pattern>;
1449 class XORVecInst<ValueType vectype>:
1450 XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1451 [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA),
1452 (vectype VECREG:$rB)))]>;
1454 class XORRegInst<RegisterClass rclass>:
1455 XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1456 [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>;
1458 multiclass BitwiseExclusiveOr
1460 def v16i8: XORVecInst<v16i8>;
1461 def v8i16: XORVecInst<v8i16>;
1462 def v4i32: XORVecInst<v4i32>;
1463 def v2i64: XORVecInst<v2i64>;
1465 def r128: XORRegInst<GPRC>;
1466 def r64: XORRegInst<R64C>;
1467 def r32: XORRegInst<R32C>;
1468 def r16: XORRegInst<R16C>;
1469 def r8: XORRegInst<R8C>;
1471 // Special forms for floating point instructions.
1472 // fneg and fabs require bitwise logical ops to manipulate the sign bit.
1474 def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1475 [/* no pattern */]>;
1477 def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1478 [/* no pattern */]>;
1480 def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1481 [/* no pattern, see fneg{32,64} */]>;
1484 defm XOR : BitwiseExclusiveOr;
1486 //==----------------------------------------------------------
1488 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1489 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1490 IntegerOp, pattern>;
1492 multiclass XorByteImm
1495 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1496 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1499 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1500 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1503 defm XORBI : XorByteImm;
1506 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1507 "xorhi\t$rT, $rA, $val", IntegerOp,
1508 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1509 v8i16SExt10Imm:$val))]>;
1512 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1513 "xorhi\t$rT, $rA, $val", IntegerOp,
1514 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1517 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
1518 "xori\t$rT, $rA, $val", IntegerOp,
1519 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1520 v4i32SExt10Imm:$val))]>;
1523 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1524 "xori\t$rT, $rA, $val", IntegerOp,
1525 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1529 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1530 "nand\t$rT, $rA, $rB", IntegerOp,
1531 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1532 (v16i8 VECREG:$rB))))]>;
1535 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1536 "nand\t$rT, $rA, $rB", IntegerOp,
1537 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1538 (v8i16 VECREG:$rB))))]>;
1541 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1542 "nand\t$rT, $rA, $rB", IntegerOp,
1543 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1544 (v4i32 VECREG:$rB))))]>;
1547 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1548 "nand\t$rT, $rA, $rB", IntegerOp,
1549 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1552 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1553 "nand\t$rT, $rA, $rB", IntegerOp,
1554 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1557 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1558 "nand\t$rT, $rA, $rB", IntegerOp,
1559 [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
1563 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1564 "nor\t$rT, $rA, $rB", IntegerOp,
1565 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1566 (v16i8 VECREG:$rB))))]>;
1569 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1570 "nor\t$rT, $rA, $rB", IntegerOp,
1571 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1572 (v8i16 VECREG:$rB))))]>;
1575 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1576 "nor\t$rT, $rA, $rB", IntegerOp,
1577 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1578 (v4i32 VECREG:$rB))))]>;
1581 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1582 "nor\t$rT, $rA, $rB", IntegerOp,
1583 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1586 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1587 "nor\t$rT, $rA, $rB", IntegerOp,
1588 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1591 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1592 "nor\t$rT, $rA, $rB", IntegerOp,
1593 [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
1596 class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
1597 RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC",
1598 IntegerOp, pattern>;
1600 class SELBVecInst<ValueType vectype>:
1601 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1602 [(set (vectype VECREG:$rT),
1603 (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)),
1604 (and (vnot (vectype VECREG:$rC)),
1605 (vectype VECREG:$rA))))]>;
1607 class SELBRegInst<RegisterClass rclass>:
1608 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
1610 (or (and rclass:$rA, rclass:$rC),
1611 (and rclass:$rB, (not rclass:$rC))))]>;
1613 multiclass SelectBits
1615 def v16i8: SELBVecInst<v16i8>;
1616 def v8i16: SELBVecInst<v8i16>;
1617 def v4i32: SELBVecInst<v4i32>;
1618 def v2i64: SELBVecInst<v2i64>;
1620 def r128: SELBRegInst<GPRC>;
1621 def r64: SELBRegInst<R64C>;
1622 def r32: SELBRegInst<R32C>;
1623 def r16: SELBRegInst<R16C>;
1624 def r8: SELBRegInst<R8C>;
1627 defm SELB : SelectBits;
1629 class SPUselbPat<ValueType vectype, SPUInstr inst>:
1630 Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)),
1631 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1633 def : SPUselbPat<v16i8, SELBv16i8>;
1634 def : SPUselbPat<v8i16, SELBv8i16>;
1635 def : SPUselbPat<v4i32, SELBv4i32>;
1636 def : SPUselbPat<v2i64, SELBv2i64>;
1638 class SelectConditional<RegisterClass rclass, SPUInstr inst>:
1639 Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse),
1640 (inst rclass:$rFalse, rclass:$rTrue, rclass:$rCond)>;
1642 def : SelectConditional<R32C, SELBr32>;
1643 def : SelectConditional<R16C, SELBr16>;
1644 def : SelectConditional<R8C, SELBr8>;
1646 // EQV: Equivalence (1 for each same bit, otherwise 0)
1648 // Note: There are a lot of ways to match this bit operator and these patterns
1649 // attempt to be as exhaustive as possible.
1651 class EQVInst<dag OOL, dag IOL, list<dag> pattern>:
1652 RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB",
1653 IntegerOp, pattern>;
1655 class EQVVecInst<ValueType vectype>:
1656 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1657 [(set (vectype VECREG:$rT),
1658 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1659 (and (vnot (vectype VECREG:$rA)),
1660 (vnot (vectype VECREG:$rB)))))]>;
1662 class EQVRegInst<RegisterClass rclass>:
1663 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1664 [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB),
1665 (and (not rclass:$rA), (not rclass:$rB))))]>;
1667 class EQVVecPattern1<ValueType vectype>:
1668 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1669 [(set (vectype VECREG:$rT),
1670 (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>;
1672 class EQVRegPattern1<RegisterClass rclass>:
1673 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1674 [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>;
1676 class EQVVecPattern2<ValueType vectype>:
1677 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1678 [(set (vectype VECREG:$rT),
1679 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1680 (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>;
1682 class EQVRegPattern2<RegisterClass rclass>:
1683 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1685 (or (and rclass:$rA, rclass:$rB),
1686 (not (or rclass:$rA, rclass:$rB))))]>;
1688 class EQVVecPattern3<ValueType vectype>:
1689 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1690 [(set (vectype VECREG:$rT),
1691 (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>;
1693 class EQVRegPattern3<RegisterClass rclass>:
1694 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1695 [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>;
1697 multiclass BitEquivalence
1699 def v16i8: EQVVecInst<v16i8>;
1700 def v8i16: EQVVecInst<v8i16>;
1701 def v4i32: EQVVecInst<v4i32>;
1702 def v2i64: EQVVecInst<v2i64>;
1704 def v16i8_1: EQVVecPattern1<v16i8>;
1705 def v8i16_1: EQVVecPattern1<v8i16>;
1706 def v4i32_1: EQVVecPattern1<v4i32>;
1707 def v2i64_1: EQVVecPattern1<v2i64>;
1709 def v16i8_2: EQVVecPattern2<v16i8>;
1710 def v8i16_2: EQVVecPattern2<v8i16>;
1711 def v4i32_2: EQVVecPattern2<v4i32>;
1712 def v2i64_2: EQVVecPattern2<v2i64>;
1714 def v16i8_3: EQVVecPattern3<v16i8>;
1715 def v8i16_3: EQVVecPattern3<v8i16>;
1716 def v4i32_3: EQVVecPattern3<v4i32>;
1717 def v2i64_3: EQVVecPattern3<v2i64>;
1719 def r128: EQVRegInst<GPRC>;
1720 def r64: EQVRegInst<R64C>;
1721 def r32: EQVRegInst<R32C>;
1722 def r16: EQVRegInst<R16C>;
1723 def r8: EQVRegInst<R8C>;
1725 def r128_1: EQVRegPattern1<GPRC>;
1726 def r64_1: EQVRegPattern1<R64C>;
1727 def r32_1: EQVRegPattern1<R32C>;
1728 def r16_1: EQVRegPattern1<R16C>;
1729 def r8_1: EQVRegPattern1<R8C>;
1731 def r128_2: EQVRegPattern2<GPRC>;
1732 def r64_2: EQVRegPattern2<R64C>;
1733 def r32_2: EQVRegPattern2<R32C>;
1734 def r16_2: EQVRegPattern2<R16C>;
1735 def r8_2: EQVRegPattern2<R8C>;
1737 def r128_3: EQVRegPattern3<GPRC>;
1738 def r64_3: EQVRegPattern3<R64C>;
1739 def r32_3: EQVRegPattern3<R32C>;
1740 def r16_3: EQVRegPattern3<R16C>;
1741 def r8_3: EQVRegPattern3<R8C>;
1744 defm EQV: BitEquivalence;
1746 //===----------------------------------------------------------------------===//
1747 // Vector shuffle...
1748 //===----------------------------------------------------------------------===//
1749 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
1750 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
1751 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
1752 // the SPUISD::SHUFB opcode.
1753 //===----------------------------------------------------------------------===//
1755 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
1756 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
1757 IntegerOp, pattern>;
1759 class SHUFBVecInst<ValueType vectype>:
1760 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1761 [(set (vectype VECREG:$rT), (SPUshuffle (vectype VECREG:$rA),
1762 (vectype VECREG:$rB),
1763 (vectype VECREG:$rC)))]>;
1765 // It's this pattern that's probably the most useful, since SPUISelLowering
1766 // methods create a v16i8 vector for $rC:
1767 class SHUFBVecPat1<ValueType vectype, ValueType masktype, SPUInstr inst>:
1768 Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB),
1769 (masktype VECREG:$rC)),
1770 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1772 multiclass ShuffleBytes
1774 def v16i8 : SHUFBVecInst<v16i8>;
1775 def v8i16 : SHUFBVecInst<v8i16>;
1776 def v4i32 : SHUFBVecInst<v4i32>;
1777 def v2i64 : SHUFBVecInst<v2i64>;
1779 def v4f32 : SHUFBVecInst<v4f32>;
1780 def v2f64 : SHUFBVecInst<v2f64>;
1783 defm SHUFB : ShuffleBytes;
1785 // Shuffle mask is a v16i8 vector
1786 def : SHUFBVecPat1<v8i16, v16i8, SHUFBv16i8>;
1787 def : SHUFBVecPat1<v4i32, v16i8, SHUFBv16i8>;
1788 def : SHUFBVecPat1<v2i64, v16i8, SHUFBv16i8>;
1789 def : SHUFBVecPat1<v4f32, v16i8, SHUFBv16i8>;
1790 def : SHUFBVecPat1<v2f64, v16i8, SHUFBv16i8>;
1792 // Shuffle mask is a v4i32 vector:
1793 def : SHUFBVecPat1<v8i16, v4i32, SHUFBv4i32>;
1794 def : SHUFBVecPat1<v4i32, v4i32, SHUFBv4i32>;
1795 def : SHUFBVecPat1<v2i64, v4i32, SHUFBv4i32>;
1796 def : SHUFBVecPat1<v4f32, v4i32, SHUFBv4i32>;
1797 def : SHUFBVecPat1<v2f64, v4i32, SHUFBv4i32>;
1799 //===----------------------------------------------------------------------===//
1800 // Shift and rotate group:
1801 //===----------------------------------------------------------------------===//
1803 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
1804 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
1805 RotateShift, pattern>;
1807 class SHLHVecInst<ValueType vectype>:
1808 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1809 [(set (vectype VECREG:$rT),
1810 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
1812 // $rB gets promoted to 32-bit register type when confronted with
1813 // this llvm assembly code:
1815 // define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
1816 // %A = shl i16 %arg1, %arg2
1820 multiclass ShiftLeftHalfword
1822 def v8i16: SHLHVecInst<v8i16>;
1823 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1824 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1825 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1826 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1829 defm SHLH : ShiftLeftHalfword;
1831 //===----------------------------------------------------------------------===//
1833 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
1834 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
1835 RotateShift, pattern>;
1837 class SHLHIVecInst<ValueType vectype>:
1838 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1839 [(set (vectype VECREG:$rT),
1840 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
1842 multiclass ShiftLeftHalfwordImm
1844 def v8i16: SHLHIVecInst<v8i16>;
1845 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
1846 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
1849 defm SHLHI : ShiftLeftHalfwordImm;
1851 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
1852 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
1854 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
1855 (SHLHIr16 R16C:$rA, uimm7:$val)>;
1857 //===----------------------------------------------------------------------===//
1859 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
1860 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
1861 RotateShift, pattern>;
1863 multiclass ShiftLeftWord
1866 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1867 [(set (v4i32 VECREG:$rT),
1868 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
1870 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1871 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
1874 defm SHL: ShiftLeftWord;
1876 //===----------------------------------------------------------------------===//
1878 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
1879 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
1880 RotateShift, pattern>;
1882 multiclass ShiftLeftWordImm
1885 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1886 [(set (v4i32 VECREG:$rT),
1887 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
1890 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
1891 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
1894 defm SHLI : ShiftLeftWordImm;
1896 //===----------------------------------------------------------------------===//
1897 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
1898 // register) to the left. Vector form is here to ensure type correctness.
1900 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
1901 // of 7 bits is actually possible.
1903 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
1904 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
1905 // bytes with SHLQBY.
1907 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
1908 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
1909 RotateShift, pattern>;
1911 class SHLQBIVecInst<ValueType vectype>:
1912 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1913 [(set (vectype VECREG:$rT),
1914 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
1916 multiclass ShiftLeftQuadByBits
1918 def v16i8: SHLQBIVecInst<v16i8>;
1919 def v8i16: SHLQBIVecInst<v8i16>;
1920 def v4i32: SHLQBIVecInst<v4i32>;
1921 def v2i64: SHLQBIVecInst<v2i64>;
1924 defm SHLQBI : ShiftLeftQuadByBits;
1926 // See note above on SHLQBI. In this case, the predicate actually does then
1927 // enforcement, whereas with SHLQBI, we have to "take it on faith."
1928 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
1929 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
1930 RotateShift, pattern>;
1932 class SHLQBIIVecInst<ValueType vectype>:
1933 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1934 [(set (vectype VECREG:$rT),
1935 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
1937 multiclass ShiftLeftQuadByBitsImm
1939 def v16i8 : SHLQBIIVecInst<v16i8>;
1940 def v8i16 : SHLQBIIVecInst<v8i16>;
1941 def v4i32 : SHLQBIIVecInst<v4i32>;
1942 def v2i64 : SHLQBIIVecInst<v2i64>;
1945 defm SHLQBII : ShiftLeftQuadByBitsImm;
1947 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
1948 // not by bits. See notes above on SHLQBI.
1950 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
1951 RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB",
1952 RotateShift, pattern>;
1954 class SHLQBYVecInst<ValueType vectype>:
1955 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1956 [(set (vectype VECREG:$rT),
1957 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
1959 multiclass ShiftLeftQuadBytes
1961 def v16i8: SHLQBYVecInst<v16i8>;
1962 def v8i16: SHLQBYVecInst<v8i16>;
1963 def v4i32: SHLQBYVecInst<v4i32>;
1964 def v2i64: SHLQBYVecInst<v2i64>;
1965 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
1966 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
1969 defm SHLQBY: ShiftLeftQuadBytes;
1971 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
1972 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
1973 RotateShift, pattern>;
1975 class SHLQBYIVecInst<ValueType vectype>:
1976 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1977 [(set (vectype VECREG:$rT),
1978 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
1980 multiclass ShiftLeftQuadBytesImm
1982 def v16i8: SHLQBYIVecInst<v16i8>;
1983 def v8i16: SHLQBYIVecInst<v8i16>;
1984 def v4i32: SHLQBYIVecInst<v4i32>;
1985 def v2i64: SHLQBYIVecInst<v2i64>;
1986 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
1988 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
1991 defm SHLQBYI : ShiftLeftQuadBytesImm;
1993 // Special form for truncating i64 to i32:
1994 def SHLQBYItrunc64: SHLQBYIInst<(outs R32C:$rT), (ins R64C:$rA, u7imm_i32:$val),
1995 [/* no pattern, see below */]>;
1997 def : Pat<(trunc R64C:$rSrc),
1998 (SHLQBYItrunc64 R64C:$rSrc, 4)>;
2000 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2002 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2003 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
2004 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
2005 RotateShift, pattern>;
2007 class ROTHVecInst<ValueType vectype>:
2008 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2009 [(set (vectype VECREG:$rT),
2010 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
2012 class ROTHRegInst<RegisterClass rclass>:
2013 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2014 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
2016 multiclass RotateLeftHalfword
2018 def v8i16: ROTHVecInst<v8i16>;
2019 def r16: ROTHRegInst<R16C>;
2022 defm ROTH: RotateLeftHalfword;
2024 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2025 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2027 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2028 // Rotate halfword, immediate:
2029 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2030 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
2031 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
2032 RotateShift, pattern>;
2034 class ROTHIVecInst<ValueType vectype>:
2035 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2036 [(set (vectype VECREG:$rT),
2037 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
2039 multiclass RotateLeftHalfwordImm
2041 def v8i16: ROTHIVecInst<v8i16>;
2042 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2043 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2044 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2045 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2048 defm ROTHI: RotateLeftHalfwordImm;
2050 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
2051 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2053 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2055 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2057 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
2058 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
2059 RotateShift, pattern>;
2061 class ROTVecInst<ValueType vectype>:
2062 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2063 [(set (vectype VECREG:$rT),
2064 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
2066 class ROTRegInst<RegisterClass rclass>:
2067 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2069 (rotl rclass:$rA, R32C:$rB))]>;
2071 multiclass RotateLeftWord
2073 def v4i32: ROTVecInst<v4i32>;
2074 def r32: ROTRegInst<R32C>;
2077 defm ROT: RotateLeftWord;
2079 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2081 def ROTr32_r16_anyext:
2082 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2083 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2085 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
2086 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2088 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
2089 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2091 def ROTr32_r8_anyext:
2092 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2093 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2095 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
2096 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2098 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
2099 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2101 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2102 // Rotate word, immediate
2103 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2105 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
2106 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
2107 RotateShift, pattern>;
2109 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
2110 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2111 [(set (vectype VECREG:$rT),
2112 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2114 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2115 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2116 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2118 multiclass RotateLeftWordImm
2120 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2121 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
2122 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
2124 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
2125 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
2126 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
2129 defm ROTI : RotateLeftWordImm;
2131 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2132 // Rotate quad by byte (count)
2133 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2135 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2136 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2137 RotateShift, pattern>;
2139 class ROTQBYVecInst<ValueType vectype>:
2140 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2141 [(set (vectype VECREG:$rT),
2142 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2144 multiclass RotateQuadLeftByBytes
2146 def v16i8: ROTQBYVecInst<v16i8>;
2147 def v8i16: ROTQBYVecInst<v8i16>;
2148 def v4i32: ROTQBYVecInst<v4i32>;
2149 def v2i64: ROTQBYVecInst<v2i64>;
2152 defm ROTQBY: RotateQuadLeftByBytes;
2154 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
2155 (ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
2156 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
2157 (ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
2158 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
2159 (ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
2160 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
2161 (ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
2163 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2164 // Rotate quad by byte (count), immediate
2165 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2167 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2168 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2169 RotateShift, pattern>;
2171 class ROTQBYIVecInst<ValueType vectype>:
2172 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2173 [(set (vectype VECREG:$rT),
2174 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2176 multiclass RotateQuadByBytesImm
2178 def v16i8: ROTQBYIVecInst<v16i8>;
2179 def v8i16: ROTQBYIVecInst<v8i16>;
2180 def v4i32: ROTQBYIVecInst<v4i32>;
2181 def v2i64: ROTQBYIVecInst<v2i64>;
2184 defm ROTQBYI: RotateQuadByBytesImm;
2186 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2187 (ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
2188 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2189 (ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
2190 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2191 (ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
2192 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
2193 (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
2195 // See ROTQBY note above.
2196 class ROTQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2197 RI7Form<0b00110011100, OOL, IOL,
2198 "rotqbybi\t$rT, $rA, $shift",
2199 RotateShift, pattern>;
2201 class ROTQBYBIVecInst<ValueType vectype, RegisterClass rclass>:
2202 ROTQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, rclass:$shift),
2203 [(set (vectype VECREG:$rT),
2204 (SPUrotbytes_left_bits (vectype VECREG:$rA), rclass:$shift))]>;
2206 multiclass RotateQuadByBytesByBitshift {
2207 def v16i8_r32: ROTQBYBIVecInst<v16i8, R32C>;
2208 def v8i16_r32: ROTQBYBIVecInst<v8i16, R32C>;
2209 def v4i32_r32: ROTQBYBIVecInst<v4i32, R32C>;
2210 def v2i64_r32: ROTQBYBIVecInst<v2i64, R32C>;
2213 defm ROTQBYBI : RotateQuadByBytesByBitshift;
2215 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2216 // See ROTQBY note above.
2218 // Assume that the user of this instruction knows to shift the rotate count
2220 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2222 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2223 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2224 RotateShift, pattern>;
2226 class ROTQBIVecInst<ValueType vectype>:
2227 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2228 [/* no pattern yet */]>;
2230 class ROTQBIRegInst<RegisterClass rclass>:
2231 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2232 [/* no pattern yet */]>;
2234 multiclass RotateQuadByBitCount
2236 def v16i8: ROTQBIVecInst<v16i8>;
2237 def v8i16: ROTQBIVecInst<v8i16>;
2238 def v4i32: ROTQBIVecInst<v4i32>;
2239 def v2i64: ROTQBIVecInst<v2i64>;
2241 def r128: ROTQBIRegInst<GPRC>;
2242 def r64: ROTQBIRegInst<R64C>;
2245 defm ROTQBI: RotateQuadByBitCount;
2247 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2248 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2249 RotateShift, pattern>;
2251 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2253 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2254 [/* no pattern yet */]>;
2256 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2258 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2259 [/* no pattern yet */]>;
2261 multiclass RotateQuadByBitCountImm
2263 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2264 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2265 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2266 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2268 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2269 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2272 defm ROTQBII : RotateQuadByBitCountImm;
2274 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2275 // ROTHM v8i16 form:
2276 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2277 // so this only matches a synthetically generated/lowered code
2279 // NOTE(2): $rB must be negated before the right rotate!
2280 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2282 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2283 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2284 RotateShift, pattern>;
2287 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2288 [/* see patterns below - $rB must be negated */]>;
2290 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2291 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2293 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2294 (ROTHMv8i16 VECREG:$rA,
2295 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2297 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2298 (ROTHMv8i16 VECREG:$rA,
2299 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2301 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2302 // Note: This instruction doesn't match a pattern because rB must be negated
2303 // for the instruction to work. Thus, the pattern below the instruction!
2306 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2307 [/* see patterns below - $rB must be negated! */]>;
2309 def : Pat<(srl R16C:$rA, R32C:$rB),
2310 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2312 def : Pat<(srl R16C:$rA, R16C:$rB),
2314 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2316 def : Pat<(srl R16C:$rA, R8C:$rB),
2318 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2320 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2321 // that the immediate can be complemented, so that the user doesn't have to
2324 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2325 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2326 RotateShift, pattern>;
2329 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2330 [/* no pattern */]>;
2332 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2333 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2335 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2336 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2338 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2339 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2342 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2343 [/* no pattern */]>;
2345 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2346 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2348 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2349 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2351 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2352 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2354 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2355 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2356 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2357 RotateShift, pattern>;
2360 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2361 [/* see patterns below - $rB must be negated */]>;
2363 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
2364 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2366 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
2367 (ROTMv4i32 VECREG:$rA,
2368 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2370 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
2371 (ROTMv4i32 VECREG:$rA,
2372 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2375 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2376 [/* see patterns below - $rB must be negated */]>;
2378 def : Pat<(srl R32C:$rA, R32C:$rB),
2379 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2381 def : Pat<(srl R32C:$rA, R16C:$rB),
2383 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2385 def : Pat<(srl R32C:$rA, R8C:$rB),
2387 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2389 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2391 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2392 "rotmi\t$rT, $rA, $val", RotateShift,
2393 [(set (v4i32 VECREG:$rT),
2394 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2396 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
2397 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2399 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
2400 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2402 // ROTMI r32 form: know how to complement the immediate value.
2404 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2405 "rotmi\t$rT, $rA, $val", RotateShift,
2406 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2408 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2409 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2411 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2412 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2414 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2415 // ROTQMBYvec: This is a vector form merely so that when used in an
2416 // instruction pattern, type checking will succeed. This instruction assumes
2417 // that the user knew to negate $rB.
2419 // Using the SPUrotquad_rz_bytes target-specific DAG node, the patterns
2420 // ensure that $rB is negated.
2421 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2423 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2424 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2425 RotateShift, pattern>;
2427 class ROTQMBYVecInst<ValueType vectype>:
2428 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2429 [/* no pattern, $rB must be negated */]>;
2431 class ROTQMBYRegInst<RegisterClass rclass>:
2432 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2434 (SPUrotquad_rz_bytes rclass:$rA, R32C:$rB))]>;
2436 multiclass RotateQuadBytes
2438 def v16i8: ROTQMBYVecInst<v16i8>;
2439 def v8i16: ROTQMBYVecInst<v8i16>;
2440 def v4i32: ROTQMBYVecInst<v4i32>;
2441 def v2i64: ROTQMBYVecInst<v2i64>;
2443 def r128: ROTQMBYRegInst<GPRC>;
2444 def r64: ROTQMBYRegInst<R64C>;
2447 defm ROTQMBY : RotateQuadBytes;
2449 def : Pat<(SPUrotquad_rz_bytes (v16i8 VECREG:$rA), R32C:$rB),
2450 (ROTQMBYv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2451 def : Pat<(SPUrotquad_rz_bytes (v8i16 VECREG:$rA), R32C:$rB),
2452 (ROTQMBYv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2453 def : Pat<(SPUrotquad_rz_bytes (v4i32 VECREG:$rA), R32C:$rB),
2454 (ROTQMBYv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2455 def : Pat<(SPUrotquad_rz_bytes (v2i64 VECREG:$rA), R32C:$rB),
2456 (ROTQMBYv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2457 def : Pat<(SPUrotquad_rz_bytes GPRC:$rA, R32C:$rB),
2458 (ROTQMBYr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2459 def : Pat<(SPUrotquad_rz_bytes R64C:$rA, R32C:$rB),
2460 (ROTQMBYr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2462 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2463 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2464 RotateShift, pattern>;
2466 class ROTQMBYIVecInst<ValueType vectype>:
2467 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2468 [(set (vectype VECREG:$rT),
2469 (SPUrotquad_rz_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2471 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2472 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2474 (SPUrotquad_rz_bytes rclass:$rA, (inttype pred:$val)))]>;
2476 multiclass RotateQuadBytesImm
2478 def v16i8: ROTQMBYIVecInst<v16i8>;
2479 def v8i16: ROTQMBYIVecInst<v8i16>;
2480 def v4i32: ROTQMBYIVecInst<v4i32>;
2481 def v2i64: ROTQMBYIVecInst<v2i64>;
2483 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2484 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2487 defm ROTQMBYI : RotateQuadBytesImm;
2489 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2490 // Rotate right and mask by bit count
2491 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2493 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2494 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2495 RotateShift, pattern>;
2497 class ROTQMBYBIVecInst<ValueType vectype>:
2498 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2499 [/* no pattern, intrinsic? */]>;
2501 multiclass RotateMaskQuadByBitCount
2503 def v16i8: ROTQMBYBIVecInst<v16i8>;
2504 def v8i16: ROTQMBYBIVecInst<v8i16>;
2505 def v4i32: ROTQMBYBIVecInst<v4i32>;
2506 def v2i64: ROTQMBYBIVecInst<v2i64>;
2509 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2511 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2512 // Rotate quad and mask by bits
2513 // Note that the rotate amount has to be negated
2514 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2516 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2517 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2518 RotateShift, pattern>;
2520 class ROTQMBIVecInst<ValueType vectype>:
2521 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2522 [/* no pattern */]>;
2524 class ROTQMBIRegInst<RegisterClass rclass>:
2525 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2526 [/* no pattern */]>;
2528 multiclass RotateMaskQuadByBits
2530 def v16i8: ROTQMBIVecInst<v16i8>;
2531 def v8i16: ROTQMBIVecInst<v8i16>;
2532 def v4i32: ROTQMBIVecInst<v4i32>;
2533 def v2i64: ROTQMBIVecInst<v2i64>;
2535 def r128: ROTQMBIRegInst<GPRC>;
2536 def r64: ROTQMBIRegInst<R64C>;
2539 defm ROTQMBI: RotateMaskQuadByBits;
2541 def : Pat<(SPUrotquad_rz_bits (v16i8 VECREG:$rA), R32C:$rB),
2542 (ROTQMBIv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2543 def : Pat<(SPUrotquad_rz_bits (v8i16 VECREG:$rA), R32C:$rB),
2544 (ROTQMBIv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2545 def : Pat<(SPUrotquad_rz_bits (v4i32 VECREG:$rA), R32C:$rB),
2546 (ROTQMBIv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2547 def : Pat<(SPUrotquad_rz_bits (v2i64 VECREG:$rA), R32C:$rB),
2548 (ROTQMBIv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2549 def : Pat<(SPUrotquad_rz_bits GPRC:$rA, R32C:$rB),
2550 (ROTQMBIr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2551 def : Pat<(SPUrotquad_rz_bits R64C:$rA, R32C:$rB),
2552 (ROTQMBIr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2554 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2555 // Rotate quad and mask by bits, immediate
2556 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2558 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2559 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2560 RotateShift, pattern>;
2562 class ROTQMBIIVecInst<ValueType vectype>:
2563 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2564 [(set (vectype VECREG:$rT),
2565 (SPUrotquad_rz_bits (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2567 class ROTQMBIIRegInst<RegisterClass rclass>:
2568 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2570 (SPUrotquad_rz_bits rclass:$rA, (i32 uimm7:$val)))]>;
2572 multiclass RotateMaskQuadByBitsImm
2574 def v16i8: ROTQMBIIVecInst<v16i8>;
2575 def v8i16: ROTQMBIIVecInst<v8i16>;
2576 def v4i32: ROTQMBIIVecInst<v4i32>;
2577 def v2i64: ROTQMBIIVecInst<v2i64>;
2579 def r128: ROTQMBIIRegInst<GPRC>;
2580 def r64: ROTQMBIIRegInst<R64C>;
2583 defm ROTQMBII: RotateMaskQuadByBitsImm;
2585 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2586 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2589 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2590 "rotmah\t$rT, $rA, $rB", RotateShift,
2591 [/* see patterns below - $rB must be negated */]>;
2593 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2594 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2596 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2597 (ROTMAHv8i16 VECREG:$rA,
2598 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2600 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2601 (ROTMAHv8i16 VECREG:$rA,
2602 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2605 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2606 "rotmah\t$rT, $rA, $rB", RotateShift,
2607 [/* see patterns below - $rB must be negated */]>;
2609 def : Pat<(sra R16C:$rA, R32C:$rB),
2610 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2612 def : Pat<(sra R16C:$rA, R16C:$rB),
2613 (ROTMAHr16 R16C:$rA,
2614 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2616 def : Pat<(sra R16C:$rA, R8C:$rB),
2617 (ROTMAHr16 R16C:$rA,
2618 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2621 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2622 "rotmahi\t$rT, $rA, $val", RotateShift,
2623 [(set (v8i16 VECREG:$rT),
2624 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2626 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2627 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2629 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2630 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2633 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2634 "rotmahi\t$rT, $rA, $val", RotateShift,
2635 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2637 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2638 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2640 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2641 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2644 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2645 "rotma\t$rT, $rA, $rB", RotateShift,
2646 [/* see patterns below - $rB must be negated */]>;
2648 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2649 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2651 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2652 (ROTMAv4i32 (v4i32 VECREG:$rA),
2653 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2655 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2656 (ROTMAv4i32 (v4i32 VECREG:$rA),
2657 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2660 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2661 "rotma\t$rT, $rA, $rB", RotateShift,
2662 [/* see patterns below - $rB must be negated */]>;
2664 def : Pat<(sra R32C:$rA, R32C:$rB),
2665 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2667 def : Pat<(sra R32C:$rA, R16C:$rB),
2669 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2671 def : Pat<(sra R32C:$rA, R8C:$rB),
2673 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2675 class ROTMAIInst<dag OOL, dag IOL, list<dag> pattern>:
2676 RRForm<0b01011110000, OOL, IOL,
2677 "rotmai\t$rT, $rA, $val",
2678 RotateShift, pattern>;
2680 class ROTMAIVecInst<ValueType vectype, Operand intop, ValueType inttype>:
2681 ROTMAIInst<(outs VECREG:$rT), (ins VECREG:$rA, intop:$val),
2682 [(set (vectype VECREG:$rT),
2683 (SPUvec_sra VECREG:$rA, (inttype uimm7:$val)))]>;
2685 class ROTMAIRegInst<RegisterClass rclass, Operand intop, ValueType inttype>:
2686 ROTMAIInst<(outs rclass:$rT), (ins rclass:$rA, intop:$val),
2687 [(set rclass:$rT, (sra rclass:$rA, (inttype uimm7:$val)))]>;
2689 multiclass RotateMaskAlgebraicImm {
2690 def v2i64_i32 : ROTMAIVecInst<v2i64, rotNeg7imm, i32>;
2691 def v4i32_i32 : ROTMAIVecInst<v4i32, rotNeg7imm, i32>;
2692 def r64_i32 : ROTMAIRegInst<R64C, rotNeg7imm, i32>;
2693 def r32_i32 : ROTMAIRegInst<R32C, rotNeg7imm, i32>;
2696 defm ROTMAI : RotateMaskAlgebraicImm;
2698 //===----------------------------------------------------------------------===//
2699 // Branch and conditionals:
2700 //===----------------------------------------------------------------------===//
2702 let isTerminator = 1, isBarrier = 1 in {
2703 // Halt If Equal (r32 preferred slot only, no vector form)
2705 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2706 "heq\t$rA, $rB", BranchResolv,
2707 [/* no pattern to match */]>;
2710 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2711 "heqi\t$rA, $val", BranchResolv,
2712 [/* no pattern to match */]>;
2714 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2715 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2717 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2718 "hgt\t$rA, $rB", BranchResolv,
2719 [/* no pattern to match */]>;
2722 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2723 "hgti\t$rA, $val", BranchResolv,
2724 [/* no pattern to match */]>;
2727 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2728 "hlgt\t$rA, $rB", BranchResolv,
2729 [/* no pattern to match */]>;
2732 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2733 "hlgti\t$rA, $val", BranchResolv,
2734 [/* no pattern to match */]>;
2737 //------------------------------------------------------------------------
2738 // Comparison operators:
2739 //------------------------------------------------------------------------
2741 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
2742 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
2745 multiclass CmpEqualByte
2748 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2749 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2750 (v8i16 VECREG:$rB)))]>;
2753 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2754 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
2757 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
2758 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
2761 multiclass CmpEqualByteImm
2764 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2765 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
2766 v16i8SExt8Imm:$val))]>;
2768 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2769 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
2772 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
2773 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
2776 multiclass CmpEqualHalfword
2778 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2779 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2780 (v8i16 VECREG:$rB)))]>;
2782 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2783 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
2786 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
2787 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
2790 multiclass CmpEqualHalfwordImm
2792 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2793 [(set (v8i16 VECREG:$rT),
2794 (seteq (v8i16 VECREG:$rA),
2795 (v8i16 v8i16SExt10Imm:$val)))]>;
2796 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2797 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
2800 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
2801 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
2804 multiclass CmpEqualWord
2806 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2807 [(set (v4i32 VECREG:$rT),
2808 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2810 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2811 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2814 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
2815 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
2818 multiclass CmpEqualWordImm
2820 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2821 [(set (v4i32 VECREG:$rT),
2822 (seteq (v4i32 VECREG:$rA),
2823 (v4i32 v4i32SExt16Imm:$val)))]>;
2825 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2826 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2829 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2830 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
2833 multiclass CmpGtrByte
2836 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2837 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2838 (v8i16 VECREG:$rB)))]>;
2841 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2842 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
2845 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2846 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
2849 multiclass CmpGtrByteImm
2852 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2853 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
2854 v16i8SExt8Imm:$val))]>;
2856 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2857 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
2860 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2861 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
2864 multiclass CmpGtrHalfword
2866 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2867 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2868 (v8i16 VECREG:$rB)))]>;
2870 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2871 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
2874 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2875 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
2878 multiclass CmpGtrHalfwordImm
2880 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2881 [(set (v8i16 VECREG:$rT),
2882 (setgt (v8i16 VECREG:$rA),
2883 (v8i16 v8i16SExt10Imm:$val)))]>;
2884 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2885 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
2888 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
2889 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
2892 multiclass CmpGtrWord
2894 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2895 [(set (v4i32 VECREG:$rT),
2896 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2898 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2899 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
2902 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2903 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
2906 multiclass CmpGtrWordImm
2908 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2909 [(set (v4i32 VECREG:$rT),
2910 (setgt (v4i32 VECREG:$rA),
2911 (v4i32 v4i32SExt16Imm:$val)))]>;
2913 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2914 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
2917 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2918 RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB",
2921 multiclass CmpLGtrByte
2924 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2925 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2926 (v8i16 VECREG:$rB)))]>;
2929 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2930 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
2933 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2934 RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val",
2937 multiclass CmpLGtrByteImm
2940 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2941 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
2942 v16i8SExt8Imm:$val))]>;
2944 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2945 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
2948 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2949 RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB",
2952 multiclass CmpLGtrHalfword
2954 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2955 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2956 (v8i16 VECREG:$rB)))]>;
2958 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2959 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
2962 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2963 RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val",
2966 multiclass CmpLGtrHalfwordImm
2968 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2969 [(set (v8i16 VECREG:$rT),
2970 (setugt (v8i16 VECREG:$rA),
2971 (v8i16 v8i16SExt10Imm:$val)))]>;
2972 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2973 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
2976 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
2977 RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB",
2980 multiclass CmpLGtrWord
2982 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2983 [(set (v4i32 VECREG:$rT),
2984 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2986 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2987 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
2990 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2991 RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val",
2994 multiclass CmpLGtrWordImm
2996 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2997 [(set (v4i32 VECREG:$rT),
2998 (setugt (v4i32 VECREG:$rA),
2999 (v4i32 v4i32SExt16Imm:$val)))]>;
3001 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3002 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
3005 defm CEQB : CmpEqualByte;
3006 defm CEQBI : CmpEqualByteImm;
3007 defm CEQH : CmpEqualHalfword;
3008 defm CEQHI : CmpEqualHalfwordImm;
3009 defm CEQ : CmpEqualWord;
3010 defm CEQI : CmpEqualWordImm;
3011 defm CGTB : CmpGtrByte;
3012 defm CGTBI : CmpGtrByteImm;
3013 defm CGTH : CmpGtrHalfword;
3014 defm CGTHI : CmpGtrHalfwordImm;
3015 defm CGT : CmpGtrWord;
3016 defm CGTI : CmpGtrWordImm;
3017 defm CLGTB : CmpLGtrByte;
3018 defm CLGTBI : CmpLGtrByteImm;
3019 defm CLGTH : CmpLGtrHalfword;
3020 defm CLGTHI : CmpLGtrHalfwordImm;
3021 defm CLGT : CmpLGtrWord;
3022 defm CLGTI : CmpLGtrWordImm;
3024 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3025 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
3026 // define a pattern to generate the right code, as a binary operator
3027 // (in a manner of speaking.)
3029 // N.B.: This only matches the setcc set of conditionals. Special pattern
3030 // matching is used for select conditionals.
3031 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3033 class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3034 SPUInstr xorinst, SPUInstr cmpare>:
3035 Pat<(cond rclass:$rA, rclass:$rB),
3036 (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
3038 class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3039 PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
3040 Pat<(cond rclass:$rA, (inttype immpred:$imm)),
3041 (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
3043 def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
3044 def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
3046 def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
3047 def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
3049 def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
3050 def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
3052 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
3053 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3054 Pat<(cond rclass:$rA, rclass:$rB),
3055 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3056 (cmpOp2 rclass:$rA, rclass:$rB))>;
3058 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3060 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3061 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
3062 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
3063 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
3065 def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
3066 def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
3067 def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
3068 def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
3069 def : Pat<(setle R8C:$rA, R8C:$rB),
3070 (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3071 def : Pat<(setle R8C:$rA, immU8:$imm),
3072 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3074 def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
3075 def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
3076 ORr16, CGTHIr16, CEQHIr16>;
3077 def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
3078 def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
3079 def : Pat<(setle R16C:$rA, R16C:$rB),
3080 (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3081 def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
3082 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3084 def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
3085 def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
3086 ORr32, CGTIr32, CEQIr32>;
3087 def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
3088 def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
3089 def : Pat<(setle R32C:$rA, R32C:$rB),
3090 (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3091 def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
3092 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3094 def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
3095 def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
3096 def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
3097 def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
3098 def : Pat<(setule R8C:$rA, R8C:$rB),
3099 (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3100 def : Pat<(setule R8C:$rA, immU8:$imm),
3101 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3103 def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
3104 def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
3105 ORr16, CLGTHIr16, CEQHIr16>;
3106 def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
3107 def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
3108 CLGTHIr16, CEQHIr16>;
3109 def : Pat<(setule R16C:$rA, R16C:$rB),
3110 (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3111 def : Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
3112 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3114 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
3115 def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
3116 ORr32, CLGTIr32, CEQIr32>;
3117 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
3118 def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
3119 def : Pat<(setule R32C:$rA, R32C:$rB),
3120 (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3121 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
3122 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3124 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3125 // select conditional patterns:
3126 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3128 class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3129 SPUInstr selinstr, SPUInstr cmpare>:
3130 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3131 rclass:$rTrue, rclass:$rFalse),
3132 (selinstr rclass:$rTrue, rclass:$rFalse,
3133 (cmpare rclass:$rA, rclass:$rB))>;
3135 class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3136 PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
3137 Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
3138 rclass:$rTrue, rclass:$rFalse),
3139 (selinstr rclass:$rTrue, rclass:$rFalse,
3140 (cmpare rclass:$rA, immpred:$imm))>;
3142 def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
3143 def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
3144 def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
3145 def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
3146 def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
3147 def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
3149 def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
3150 def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
3151 def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
3152 def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
3153 def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
3154 def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
3156 def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
3157 def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
3158 def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
3159 def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
3160 def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
3161 def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
3163 class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3164 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3166 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3167 rclass:$rFalse, rclass:$rTrue),
3168 (selinstr rclass:$rTrue, rclass:$rFalse,
3169 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3170 (cmpOp2 rclass:$rA, rclass:$rB)))>;
3172 class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3174 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3176 Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
3177 rclass:$rTrue, rclass:$rFalse),
3178 (selinstr rclass:$rFalse, rclass:$rTrue,
3179 (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
3180 (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
3182 def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
3183 def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
3184 SELBr8, ORr8, CGTBIr8, CEQBIr8>;
3186 def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
3187 def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
3188 SELBr16, ORr16, CGTHIr16, CEQHIr16>;
3190 def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
3191 def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
3192 SELBr32, ORr32, CGTIr32, CEQIr32>;
3194 def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
3195 def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
3196 SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
3198 def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
3199 def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
3200 SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
3202 def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
3203 def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
3204 SELBr32, ORr32, CLGTIr32, CEQIr32>;
3206 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3209 // All calls clobber the non-callee-saved registers:
3210 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
3211 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
3212 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
3213 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
3214 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
3215 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
3216 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
3217 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
3218 // All of these instructions use $lr (aka $0)
3220 // Branch relative and set link: Used if we actually know that the target
3221 // is within [-32768, 32767] bytes of the target
3223 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
3224 "brsl\t$$lr, $func",
3225 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
3227 // Branch absolute and set link: Used if we actually know that the target
3228 // is an absolute address
3230 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
3231 "brasl\t$$lr, $func",
3232 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
3234 // Branch indirect and set link if external data. These instructions are not
3235 // actually generated, matched by an intrinsic:
3236 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
3237 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
3238 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
3239 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
3241 // Branch indirect and set link. This is the "X-form" address version of a
3244 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
3247 // Unconditional branches:
3248 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
3250 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3254 // Unconditional, absolute address branch
3256 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3258 [/* no pattern */]>;
3262 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3264 // Various branches:
3266 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
3267 "brnz\t$rCond,$dest",
3269 [(brcond R32C:$rCond, bb:$dest)]>;
3272 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
3275 [/* no pattern */]>;
3278 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
3279 "brhnz\t$rCond,$dest",
3281 [(brcond R16C:$rCond, bb:$dest)]>;
3284 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
3287 [/* no pattern */]>;
3291 BICondForm<0b10010100100, "binz\t$rA, $func",
3292 [(SPUbinz R32C:$rA, R32C:$func)]>;
3295 BICondForm<0b00010100100, "biz\t$rA, $func",
3296 [(SPUbiz R32C:$rA, R32C:$func)]>;
3300 //===----------------------------------------------------------------------===//
3301 // setcc and brcond patterns:
3302 //===----------------------------------------------------------------------===//
3304 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3305 (BRHZ R16C:$rA, bb:$dest)>;
3306 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3307 (BRHNZ R16C:$rA, bb:$dest)>;
3309 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3310 (BRZ R32C:$rA, bb:$dest)>;
3311 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3312 (BRNZ R32C:$rA, bb:$dest)>;
3314 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3316 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3317 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3319 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3320 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3322 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3323 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3325 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3326 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3329 defm BRCONDeq : BranchCondEQ<seteq, BRHZ, BRZ>;
3330 defm BRCONDne : BranchCondEQ<setne, BRHNZ, BRNZ>;
3332 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3334 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3335 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3337 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3338 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3340 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3341 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3343 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3344 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3347 defm BRCONDugt : BranchCondLGT<setugt, BRHNZ, BRNZ>;
3348 defm BRCONDule : BranchCondLGT<setule, BRHZ, BRZ>;
3350 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3351 SPUInstr orinst32, SPUInstr brinst32>
3353 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3354 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3355 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3358 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3359 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3360 (CEQHr16 R16C:$rA, R16:$rB)),
3363 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3364 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3365 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3368 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3369 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3370 (CEQr32 R32C:$rA, R32C:$rB)),
3374 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZ, ORr32, BRNZ>;
3375 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZ, ORr32, BRZ>;
3377 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3379 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3380 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3382 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3383 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3385 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3386 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3388 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3389 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3392 defm BRCONDgt : BranchCondGT<setgt, BRHNZ, BRNZ>;
3393 defm BRCONDle : BranchCondGT<setle, BRHZ, BRZ>;
3395 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3396 SPUInstr orinst32, SPUInstr brinst32>
3398 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3399 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3400 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3403 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3404 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3405 (CEQHr16 R16C:$rA, R16:$rB)),
3408 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3409 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3410 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3413 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3414 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3415 (CEQr32 R32C:$rA, R32C:$rB)),
3419 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZ, ORr32, BRNZ>;
3420 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZ, ORr32, BRZ>;
3422 let isTerminator = 1, isBarrier = 1 in {
3423 let isReturn = 1 in {
3425 RETForm<"bi\t$$lr", [(retflag)]>;
3429 //===----------------------------------------------------------------------===//
3430 // Single precision floating point instructions
3431 //===----------------------------------------------------------------------===//
3434 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3435 "fa\t$rT, $rA, $rB", SPrecFP,
3436 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3439 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3440 "fa\t$rT, $rA, $rB", SPrecFP,
3441 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3444 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3445 "fs\t$rT, $rA, $rB", SPrecFP,
3446 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3449 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3450 "fs\t$rT, $rA, $rB", SPrecFP,
3451 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3453 // Floating point reciprocal estimate
3455 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
3456 "frest\t$rT, $rA", SPrecFP,
3457 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
3460 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
3461 "frest\t$rT, $rA", SPrecFP,
3462 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
3464 // Floating point interpolate (used in conjunction with reciprocal estimate)
3466 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3467 "fi\t$rT, $rA, $rB", SPrecFP,
3468 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
3469 (v4f32 VECREG:$rB)))]>;
3472 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3473 "fi\t$rT, $rA, $rB", SPrecFP,
3474 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
3476 // Floating Compare Equal
3478 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3479 "fceq\t$rT, $rA, $rB", SPrecFP,
3480 [(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
3483 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3484 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3485 [(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3488 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3489 "fcgt\t$rT, $rA, $rB", SPrecFP,
3490 [(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
3493 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3494 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3495 [(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3497 // FP Status and Control Register Write
3498 // Why isn't rT a don't care in the ISA?
3499 // Should we create a special RRForm_3 for this guy and zero out the rT?
3501 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3502 "fscrwr\t$rA", SPrecFP,
3503 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3505 // FP Status and Control Register Read
3507 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3508 "fscrrd\t$rT", SPrecFP,
3509 [/* This instruction requires an intrinsic */]>;
3511 // llvm instruction space
3512 // How do these map onto cell instructions?
3514 // frest rC rB # c = 1/b (both lines)
3516 // fm rD rA rC # d = a * 1/b
3517 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3518 // fma rB rB rC rD # b = b * c + d
3519 // = -(d *b -a) * c + d
3520 // = a * c - c ( a *b *c - a)
3525 // These llvm instructions will actually map to library calls.
3526 // All that's needed, then, is to check that the appropriate library is
3527 // imported and do a brsl to the proper function name.
3528 // frem # fmod(x, y): x - (x/y) * y
3529 // (Note: fmod(double, double), fmodf(float,float)
3533 // Unimplemented SPU instruction space
3534 // floating reciprocal absolute square root estimate (frsqest)
3536 // The following are probably just intrinsics
3537 // status and control register write
3538 // status and control register read
3540 //--------------------------------------
3541 // Floating point multiply instructions
3542 //--------------------------------------
3545 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3546 "fm\t$rT, $rA, $rB", SPrecFP,
3547 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
3548 (v4f32 VECREG:$rB)))]>;
3551 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3552 "fm\t$rT, $rA, $rB", SPrecFP,
3553 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
3555 // Floating point multiply and add
3556 // e.g. d = c + (a * b)
3558 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3559 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3560 [(set (v4f32 VECREG:$rT),
3561 (fadd (v4f32 VECREG:$rC),
3562 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
3565 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3566 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3567 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3569 // FP multiply and subtract
3570 // Subtracts value in rC from product
3573 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3574 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3575 [(set (v4f32 VECREG:$rT),
3576 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
3577 (v4f32 VECREG:$rC)))]>;
3580 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3581 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3583 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
3585 // Floating Negative Mulitply and Subtract
3586 // Subtracts product from value in rC
3587 // res = fneg(fms a b c)
3590 // NOTE: subtraction order
3594 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3595 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3596 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3599 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3600 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3601 [(set (v4f32 VECREG:$rT),
3602 (fsub (v4f32 VECREG:$rC),
3603 (fmul (v4f32 VECREG:$rA),
3604 (v4f32 VECREG:$rB))))]>;
3606 //--------------------------------------
3607 // Floating Point Conversions
3608 // Signed conversions:
3610 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3611 "csflt\t$rT, $rA, 0", SPrecFP,
3612 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
3614 // Convert signed integer to floating point
3616 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
3617 "csflt\t$rT, $rA, 0", SPrecFP,
3618 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
3620 // Convert unsigned into to float
3622 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3623 "cuflt\t$rT, $rA, 0", SPrecFP,
3624 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
3627 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
3628 "cuflt\t$rT, $rA, 0", SPrecFP,
3629 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
3631 // Convert float to unsigned int
3632 // Assume that scale = 0
3635 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3636 "cfltu\t$rT, $rA, 0", SPrecFP,
3637 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
3640 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3641 "cfltu\t$rT, $rA, 0", SPrecFP,
3642 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
3644 // Convert float to signed int
3645 // Assume that scale = 0
3648 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3649 "cflts\t$rT, $rA, 0", SPrecFP,
3650 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
3653 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3654 "cflts\t$rT, $rA, 0", SPrecFP,
3655 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
3657 //===----------------------------------------------------------------------==//
3658 // Single<->Double precision conversions
3659 //===----------------------------------------------------------------------==//
3661 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
3662 // v4f32, output is v2f64--which goes in the name?)
3664 // Floating point extend single to double
3665 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
3666 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
3669 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3670 "fesd\t$rT, $rA", SPrecFP,
3671 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
3674 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
3675 "fesd\t$rT, $rA", SPrecFP,
3676 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
3678 // Floating point round double to single
3680 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3681 // "frds\t$rT, $rA,", SPrecFP,
3682 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
3685 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
3686 "frds\t$rT, $rA", SPrecFP,
3687 [(set R32FP:$rT, (fround R64FP:$rA))]>;
3689 //ToDo include anyextend?
3691 //===----------------------------------------------------------------------==//
3692 // Double precision floating point instructions
3693 //===----------------------------------------------------------------------==//
3695 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3696 "dfa\t$rT, $rA, $rB", DPrecFP,
3697 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
3700 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3701 "dfa\t$rT, $rA, $rB", DPrecFP,
3702 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3705 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3706 "dfs\t$rT, $rA, $rB", DPrecFP,
3707 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
3710 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3711 "dfs\t$rT, $rA, $rB", DPrecFP,
3712 [(set (v2f64 VECREG:$rT),
3713 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3716 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3717 "dfm\t$rT, $rA, $rB", DPrecFP,
3718 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
3721 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3722 "dfm\t$rT, $rA, $rB", DPrecFP,
3723 [(set (v2f64 VECREG:$rT),
3724 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3727 RRForm<0b00111010110, (outs R64FP:$rT),
3728 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3729 "dfma\t$rT, $rA, $rB", DPrecFP,
3730 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3731 RegConstraint<"$rC = $rT">,
3735 RRForm<0b00111010110, (outs VECREG:$rT),
3736 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3737 "dfma\t$rT, $rA, $rB", DPrecFP,
3738 [(set (v2f64 VECREG:$rT),
3739 (fadd (v2f64 VECREG:$rC),
3740 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
3741 RegConstraint<"$rC = $rT">,
3745 RRForm<0b10111010110, (outs R64FP:$rT),
3746 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3747 "dfms\t$rT, $rA, $rB", DPrecFP,
3748 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
3749 RegConstraint<"$rC = $rT">,
3753 RRForm<0b10111010110, (outs VECREG:$rT),
3754 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3755 "dfms\t$rT, $rA, $rB", DPrecFP,
3756 [(set (v2f64 VECREG:$rT),
3757 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3758 (v2f64 VECREG:$rC)))]>;
3760 // FNMS: - (a * b - c)
3761 // - (a * b) + c => c - (a * b)
3763 RRForm<0b01111010110, (outs R64FP:$rT),
3764 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3765 "dfnms\t$rT, $rA, $rB", DPrecFP,
3766 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3767 RegConstraint<"$rC = $rT">,
3770 def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
3771 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
3774 RRForm<0b01111010110, (outs VECREG:$rT),
3775 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3776 "dfnms\t$rT, $rA, $rB", DPrecFP,
3777 [(set (v2f64 VECREG:$rT),
3778 (fsub (v2f64 VECREG:$rC),
3779 (fmul (v2f64 VECREG:$rA),
3780 (v2f64 VECREG:$rB))))]>,
3781 RegConstraint<"$rC = $rT">,
3784 def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3785 (v2f64 VECREG:$rC))),
3786 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
3791 RRForm<0b11111010110, (outs R64FP:$rT),
3792 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3793 "dfnma\t$rT, $rA, $rB", DPrecFP,
3794 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
3795 RegConstraint<"$rC = $rT">,
3799 RRForm<0b11111010110, (outs VECREG:$rT),
3800 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3801 "dfnma\t$rT, $rA, $rB", DPrecFP,
3802 [(set (v2f64 VECREG:$rT),
3803 (fneg (fadd (v2f64 VECREG:$rC),
3804 (fmul (v2f64 VECREG:$rA),
3805 (v2f64 VECREG:$rB)))))]>,
3806 RegConstraint<"$rC = $rT">,
3809 //===----------------------------------------------------------------------==//
3810 // Floating point negation and absolute value
3811 //===----------------------------------------------------------------------==//
3813 def : Pat<(fneg (v4f32 VECREG:$rA)),
3814 (XORfnegvec (v4f32 VECREG:$rA),
3815 (v4f32 (ILHUv4i32 0x8000)))>;
3817 def : Pat<(fneg R32FP:$rA),
3818 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
3820 def : Pat<(fneg (v2f64 VECREG:$rA)),
3821 (XORfnegvec (v2f64 VECREG:$rA),
3822 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
3824 def : Pat<(fneg R64FP:$rA),
3825 (XORfneg64 R64FP:$rA,
3826 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
3828 // Floating point absolute value
3830 def : Pat<(fabs R32FP:$rA),
3831 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
3833 def : Pat<(fabs (v4f32 VECREG:$rA)),
3834 (ANDfabsvec (v4f32 VECREG:$rA),
3835 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3837 def : Pat<(fabs R64FP:$rA),
3838 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
3840 def : Pat<(fabs (v2f64 VECREG:$rA)),
3841 (ANDfabsvec (v2f64 VECREG:$rA),
3842 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3844 //===----------------------------------------------------------------------===//
3845 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
3846 // in the odd pipeline)
3847 //===----------------------------------------------------------------------===//
3849 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
3852 let Inst{0-10} = 0b10000000010;
3853 let Inst{11-17} = 0;
3854 let Inst{18-24} = 0;
3855 let Inst{25-31} = 0;
3858 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
3861 let Inst{0-10} = 0b10000000000;
3862 let Inst{11-17} = 0;
3863 let Inst{18-24} = 0;
3864 let Inst{25-31} = 0;
3867 //===----------------------------------------------------------------------===//
3868 // Bit conversions (type conversions between vector/packed types)
3869 // NOTE: Promotions are handled using the XS* instructions. Truncation
3871 //===----------------------------------------------------------------------===//
3872 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3873 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3874 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3875 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3876 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3878 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3879 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3880 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3881 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3882 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3884 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3885 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3886 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3887 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3888 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3890 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3891 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3892 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3893 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3894 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3896 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3897 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3898 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3899 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3900 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3902 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3903 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3904 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3905 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3906 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3908 def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3909 def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
3911 //===----------------------------------------------------------------------===//
3912 // Instruction patterns:
3913 //===----------------------------------------------------------------------===//
3915 // General 32-bit constants:
3916 def : Pat<(i32 imm:$imm),
3917 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3919 // Single precision float constants:
3920 def : Pat<(f32 fpimm:$imm),
3921 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3923 // General constant 32-bit vectors
3924 def : Pat<(v4i32 v4i32Imm:$imm),
3925 (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
3926 (LO16_vec v4i32Imm:$imm))>;
3929 def : Pat<(i8 imm:$imm),
3932 //===----------------------------------------------------------------------===//
3933 // Call instruction patterns:
3934 //===----------------------------------------------------------------------===//
3939 //===----------------------------------------------------------------------===//
3940 // Zero/Any/Sign extensions
3941 //===----------------------------------------------------------------------===//
3943 // zext 1->32: Zero extend i1 to i32
3944 def : Pat<(SPUextract_i1_zext R32C:$rSrc),
3945 (ANDIr32 R32C:$rSrc, 0x1)>;
3947 // sext 8->32: Sign extend bytes to words
3948 def : Pat<(sext_inreg R32C:$rSrc, i8),
3949 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
3951 def : Pat<(i32 (sext R8C:$rSrc)),
3952 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
3954 def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
3955 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
3956 (v4i32 VECREG:$rSrc))))>;
3958 // zext 8->16: Zero extend bytes to halfwords
3959 def : Pat<(i16 (zext R8C:$rSrc)),
3960 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
3962 // zext 8->32 from preferred slot in load/store
3963 def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
3964 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
3967 // zext 8->32: Zero extend bytes to words
3968 def : Pat<(i32 (zext R8C:$rSrc)),
3969 (ANDIi8i32 R8C:$rSrc, 0xff)>;
3971 // anyext 8->16: Extend 8->16 bits, irrespective of sign
3972 def : Pat<(i16 (anyext R8C:$rSrc)),
3973 (ORHIi8i16 R8C:$rSrc, 0)>;
3975 // anyext 8->32: Extend 8->32 bits, irrespective of sign
3976 def : Pat<(i32 (anyext R8C:$rSrc)),
3977 (ORIi8i32 R8C:$rSrc, 0)>;
3979 // zext 16->32: Zero extend halfwords to words
3980 def : Pat<(i32 (zext R16C:$rSrc)),
3981 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
3983 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
3984 (ANDIi16i32 R16C:$rSrc, 0xf)>;
3986 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
3987 (ANDIi16i32 R16C:$rSrc, 0xff)>;
3989 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
3990 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
3992 // anyext 16->32: Extend 16->32 bits, irrespective of sign
3993 def : Pat<(i32 (anyext R16C:$rSrc)),
3994 (ORIi16i32 R16C:$rSrc, 0)>;
3996 //===----------------------------------------------------------------------===//
3997 // Address generation: SPU, like PPC, has to split addresses into high and
3998 // low parts in order to load them into a register.
3999 //===----------------------------------------------------------------------===//
4001 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
4002 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
4003 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
4004 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
4006 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
4007 (SPUlo tglobaladdr:$in, 0)),
4008 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4010 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
4011 (SPUlo texternalsym:$in, 0)),
4012 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4014 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
4015 (SPUlo tjumptable:$in, 0)),
4016 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4018 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
4019 (SPUlo tconstpool:$in, 0)),
4020 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4022 def : Pat<(SPUindirect R32C:$sp, i32ImmSExt10:$imm),
4023 (AIr32 R32C:$sp, i32ImmSExt10:$imm)>;
4025 def : Pat<(SPUindirect R32C:$sp, imm:$imm),
4027 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm)))>;
4029 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
4030 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4032 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
4033 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4035 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
4036 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4038 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
4039 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4042 include "CellSDKIntrinsics.td"