1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start timm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end timm:$amt)]>;
33 //===----------------------------------------------------------------------===//
35 // NB: The ordering is actually important, since the instruction selection
36 // will try each of the instructions in sequence, i.e., the D-form first with
37 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
38 // finally the X-form with the register-register.
39 //===----------------------------------------------------------------------===//
41 let canFoldAsLoad = 1 in {
42 class LoadDFormVec<ValueType vectype>
43 : RI10Form<0b00101100, (outs VECREG:$rT), (ins dformaddr:$src),
46 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
49 class LoadDForm<RegisterClass rclass>
50 : RI10Form<0b00101100, (outs rclass:$rT), (ins dformaddr:$src),
53 [(set rclass:$rT, (load dform_addr:$src))]>
58 def v16i8: LoadDFormVec<v16i8>;
59 def v8i16: LoadDFormVec<v8i16>;
60 def v4i32: LoadDFormVec<v4i32>;
61 def v2i64: LoadDFormVec<v2i64>;
62 def v4f32: LoadDFormVec<v4f32>;
63 def v2f64: LoadDFormVec<v2f64>;
65 def v2i32: LoadDFormVec<v2i32>;
67 def r128: LoadDForm<GPRC>;
68 def r64: LoadDForm<R64C>;
69 def r32: LoadDForm<R32C>;
70 def f32: LoadDForm<R32FP>;
71 def f64: LoadDForm<R64FP>;
72 def r16: LoadDForm<R16C>;
73 def r8: LoadDForm<R8C>;
76 class LoadAFormVec<ValueType vectype>
77 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
80 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
83 class LoadAForm<RegisterClass rclass>
84 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
87 [(set rclass:$rT, (load aform_addr:$src))]>
92 def v16i8: LoadAFormVec<v16i8>;
93 def v8i16: LoadAFormVec<v8i16>;
94 def v4i32: LoadAFormVec<v4i32>;
95 def v2i64: LoadAFormVec<v2i64>;
96 def v4f32: LoadAFormVec<v4f32>;
97 def v2f64: LoadAFormVec<v2f64>;
99 def v2i32: LoadAFormVec<v2i32>;
101 def r128: LoadAForm<GPRC>;
102 def r64: LoadAForm<R64C>;
103 def r32: LoadAForm<R32C>;
104 def f32: LoadAForm<R32FP>;
105 def f64: LoadAForm<R64FP>;
106 def r16: LoadAForm<R16C>;
107 def r8: LoadAForm<R8C>;
110 class LoadXFormVec<ValueType vectype>
111 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
114 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
117 class LoadXForm<RegisterClass rclass>
118 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
121 [(set rclass:$rT, (load xform_addr:$src))]>
124 multiclass LoadXForms
126 def v16i8: LoadXFormVec<v16i8>;
127 def v8i16: LoadXFormVec<v8i16>;
128 def v4i32: LoadXFormVec<v4i32>;
129 def v2i64: LoadXFormVec<v2i64>;
130 def v4f32: LoadXFormVec<v4f32>;
131 def v2f64: LoadXFormVec<v2f64>;
133 def v2i32: LoadXFormVec<v2i32>;
135 def r128: LoadXForm<GPRC>;
136 def r64: LoadXForm<R64C>;
137 def r32: LoadXForm<R32C>;
138 def f32: LoadXForm<R32FP>;
139 def f64: LoadXForm<R64FP>;
140 def r16: LoadXForm<R16C>;
141 def r8: LoadXForm<R8C>;
144 defm LQA : LoadAForms;
145 defm LQD : LoadDForms;
146 defm LQX : LoadXForms;
148 /* Load quadword, PC relative: Not much use at this point in time.
149 Might be of use later for relocatable code. It's effectively the
150 same as LQA, but uses PC-relative addressing.
151 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
152 "lqr\t$rT, $disp", LoadStore,
153 [(set VECREG:$rT, (load iaddr:$disp))]>;
157 //===----------------------------------------------------------------------===//
159 //===----------------------------------------------------------------------===//
160 class StoreDFormVec<ValueType vectype>
161 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, dformaddr:$src),
164 [(store (vectype VECREG:$rT), dform_addr:$src)]>
167 class StoreDForm<RegisterClass rclass>
168 : RI10Form<0b00100100, (outs), (ins rclass:$rT, dformaddr:$src),
171 [(store rclass:$rT, dform_addr:$src)]>
174 multiclass StoreDForms
176 def v16i8: StoreDFormVec<v16i8>;
177 def v8i16: StoreDFormVec<v8i16>;
178 def v4i32: StoreDFormVec<v4i32>;
179 def v2i64: StoreDFormVec<v2i64>;
180 def v4f32: StoreDFormVec<v4f32>;
181 def v2f64: StoreDFormVec<v2f64>;
183 def v2i32: StoreDFormVec<v2i32>;
185 def r128: StoreDForm<GPRC>;
186 def r64: StoreDForm<R64C>;
187 def r32: StoreDForm<R32C>;
188 def f32: StoreDForm<R32FP>;
189 def f64: StoreDForm<R64FP>;
190 def r16: StoreDForm<R16C>;
191 def r8: StoreDForm<R8C>;
194 class StoreAFormVec<ValueType vectype>
195 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
198 [(store (vectype VECREG:$rT), aform_addr:$src)]>;
200 class StoreAForm<RegisterClass rclass>
201 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
204 [(store rclass:$rT, aform_addr:$src)]>;
206 multiclass StoreAForms
208 def v16i8: StoreAFormVec<v16i8>;
209 def v8i16: StoreAFormVec<v8i16>;
210 def v4i32: StoreAFormVec<v4i32>;
211 def v2i64: StoreAFormVec<v2i64>;
212 def v4f32: StoreAFormVec<v4f32>;
213 def v2f64: StoreAFormVec<v2f64>;
215 def v2i32: StoreAFormVec<v2i32>;
217 def r128: StoreAForm<GPRC>;
218 def r64: StoreAForm<R64C>;
219 def r32: StoreAForm<R32C>;
220 def f32: StoreAForm<R32FP>;
221 def f64: StoreAForm<R64FP>;
222 def r16: StoreAForm<R16C>;
223 def r8: StoreAForm<R8C>;
226 class StoreXFormVec<ValueType vectype>
227 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
230 [(store (vectype VECREG:$rT), xform_addr:$src)]>
233 class StoreXForm<RegisterClass rclass>
234 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
237 [(store rclass:$rT, xform_addr:$src)]>
240 multiclass StoreXForms
242 def v16i8: StoreXFormVec<v16i8>;
243 def v8i16: StoreXFormVec<v8i16>;
244 def v4i32: StoreXFormVec<v4i32>;
245 def v2i64: StoreXFormVec<v2i64>;
246 def v4f32: StoreXFormVec<v4f32>;
247 def v2f64: StoreXFormVec<v2f64>;
249 def v2i32: StoreXFormVec<v2i32>;
251 def r128: StoreXForm<GPRC>;
252 def r64: StoreXForm<R64C>;
253 def r32: StoreXForm<R32C>;
254 def f32: StoreXForm<R32FP>;
255 def f64: StoreXForm<R64FP>;
256 def r16: StoreXForm<R16C>;
257 def r8: StoreXForm<R8C>;
260 defm STQD : StoreDForms;
261 defm STQA : StoreAForms;
262 defm STQX : StoreXForms;
264 /* Store quadword, PC relative: Not much use at this point in time. Might
265 be useful for relocatable code.
266 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
267 "stqr\t$rT, $disp", LoadStore,
268 [(store VECREG:$rT, iaddr:$disp)]>;
271 //===----------------------------------------------------------------------===//
272 // Generate Controls for Insertion:
273 //===----------------------------------------------------------------------===//
275 def CBD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins shufaddr:$src),
276 "cbd\t$rT, $src", ShuffleOp,
277 [(set (v16i8 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
279 def CBX: RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
280 "cbx\t$rT, $src", ShuffleOp,
281 [(set (v16i8 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
283 def CHD: RI7Form<0b10101111100, (outs VECREG:$rT), (ins shufaddr:$src),
284 "chd\t$rT, $src", ShuffleOp,
285 [(set (v8i16 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
287 def CHX: RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
288 "chx\t$rT, $src", ShuffleOp,
289 [(set (v8i16 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
291 def CWD: RI7Form<0b01101111100, (outs VECREG:$rT), (ins shufaddr:$src),
292 "cwd\t$rT, $src", ShuffleOp,
293 [(set (v4i32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
295 def CWX: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
296 "cwx\t$rT, $src", ShuffleOp,
297 [(set (v4i32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
299 def CWDf32: RI7Form<0b01101111100, (outs VECREG:$rT), (ins shufaddr:$src),
300 "cwd\t$rT, $src", ShuffleOp,
301 [(set (v4f32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
303 def CWXf32: RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
304 "cwx\t$rT, $src", ShuffleOp,
305 [(set (v4f32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
307 def CDD: RI7Form<0b11101111100, (outs VECREG:$rT), (ins shufaddr:$src),
308 "cdd\t$rT, $src", ShuffleOp,
309 [(set (v2i64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
311 def CDX: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
312 "cdx\t$rT, $src", ShuffleOp,
313 [(set (v2i64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
315 def CDDf64: RI7Form<0b11101111100, (outs VECREG:$rT), (ins shufaddr:$src),
316 "cdd\t$rT, $src", ShuffleOp,
317 [(set (v2f64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
319 def CDXf64: RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
320 "cdx\t$rT, $src", ShuffleOp,
321 [(set (v2f64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
323 //===----------------------------------------------------------------------===//
324 // Constant formation:
325 //===----------------------------------------------------------------------===//
328 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
329 "ilh\t$rT, $val", ImmLoad,
330 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
333 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
334 "ilh\t$rT, $val", ImmLoad,
335 [(set R16C:$rT, immSExt16:$val)]>;
337 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
338 // the right constant")
340 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
341 "ilh\t$rT, $val", ImmLoad,
342 [(set R8C:$rT, immSExt8:$val)]>;
344 // IL does sign extension!
346 class ILInst<dag OOL, dag IOL, list<dag> pattern>:
347 RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val",
350 class ILVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
351 ILInst<(outs VECREG:$rT), (ins immtype:$val),
352 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
354 class ILRegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
355 ILInst<(outs rclass:$rT), (ins immtype:$val),
356 [(set rclass:$rT, xform:$val)]>;
358 multiclass ImmediateLoad
360 def v2i64: ILVecInst<v2i64, s16imm_i64, v2i64SExt16Imm>;
361 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
363 // TODO: Need v2f64, v4f32
365 def r64: ILRegInst<R64C, s16imm_i64, immSExt16>;
366 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
367 def f32: ILRegInst<R32FP, s16imm_f32, fpimmSExt16>;
368 def f64: ILRegInst<R64FP, s16imm_f64, fpimmSExt16>;
371 defm IL : ImmediateLoad;
373 class ILHUInst<dag OOL, dag IOL, list<dag> pattern>:
374 RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val",
377 class ILHUVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
378 ILHUInst<(outs VECREG:$rT), (ins immtype:$val),
379 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
381 class ILHURegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
382 ILHUInst<(outs rclass:$rT), (ins immtype:$val),
383 [(set rclass:$rT, xform:$val)]>;
385 multiclass ImmLoadHalfwordUpper
387 def v2i64: ILHUVecInst<v2i64, u16imm_i64, immILHUvec_i64>;
388 def v4i32: ILHUVecInst<v4i32, u16imm_i32, immILHUvec>;
390 def r64: ILHURegInst<R64C, u16imm_i64, hi16>;
391 def r32: ILHURegInst<R32C, u16imm_i32, hi16>;
393 // Loads the high portion of an address
394 def hi: ILHURegInst<R32C, symbolHi, hi16>;
396 // Used in custom lowering constant SFP loads:
397 def f32: ILHURegInst<R32FP, f16imm, hi16_f32>;
400 defm ILHU : ImmLoadHalfwordUpper;
402 // Immediate load address (can also be used to load 18-bit unsigned constants,
403 // see the zext 16->32 pattern)
405 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
406 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
409 class ILAVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
410 ILAInst<(outs VECREG:$rT), (ins immtype:$val),
411 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
413 class ILARegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
414 ILAInst<(outs rclass:$rT), (ins immtype:$val),
415 [(set rclass:$rT, xform:$val)]>;
417 multiclass ImmLoadAddress
419 def v2i64: ILAVecInst<v2i64, u18imm, v2i64Uns18Imm>;
420 def v4i32: ILAVecInst<v4i32, u18imm, v4i32Uns18Imm>;
422 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
423 def r32: ILARegInst<R32C, u18imm, imm18>;
424 def f32: ILARegInst<R32FP, f18imm, fpimm18>;
425 def f64: ILARegInst<R64FP, f18imm_f64, fpimm18>;
427 def hi: ILARegInst<R32C, symbolHi, imm18>;
428 def lo: ILARegInst<R32C, symbolLo, imm18>;
430 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
434 defm ILA : ImmLoadAddress;
436 // Immediate OR, Halfword Lower: The "other" part of loading large constants
437 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
438 // Note that these are really two operand instructions, but they're encoded
439 // as three operands with the first two arguments tied-to each other.
441 class IOHLInst<dag OOL, dag IOL, list<dag> pattern>:
442 RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val",
444 RegConstraint<"$rS = $rT">,
447 class IOHLVecInst<ValueType vectype, Operand immtype /* , PatLeaf xform */>:
448 IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val),
451 class IOHLRegInst<RegisterClass rclass, Operand immtype /* , PatLeaf xform */>:
452 IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val),
455 multiclass ImmOrHalfwordLower
457 def v2i64: IOHLVecInst<v2i64, u16imm_i64>;
458 def v4i32: IOHLVecInst<v4i32, u16imm_i32>;
460 def r32: IOHLRegInst<R32C, i32imm>;
461 def f32: IOHLRegInst<R32FP, f32imm>;
463 def lo: IOHLRegInst<R32C, symbolLo>;
466 defm IOHL: ImmOrHalfwordLower;
468 // Form select mask for bytes using immediate, used in conjunction with the
471 class FSMBIVec<ValueType vectype>:
472 RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
475 [(set (vectype VECREG:$rT), (SPUselmask (i16 immU16:$val)))]>;
477 multiclass FormSelectMaskBytesImm
479 def v16i8: FSMBIVec<v16i8>;
480 def v8i16: FSMBIVec<v8i16>;
481 def v4i32: FSMBIVec<v4i32>;
482 def v2i64: FSMBIVec<v2i64>;
485 defm FSMBI : FormSelectMaskBytesImm;
487 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
488 class FSMBInst<dag OOL, dag IOL, list<dag> pattern>:
489 RRForm_1<0b01101101100, OOL, IOL, "fsmb\t$rT, $rA", SelectOp,
492 class FSMBRegInst<RegisterClass rclass, ValueType vectype>:
493 FSMBInst<(outs VECREG:$rT), (ins rclass:$rA),
494 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
496 class FSMBVecInst<ValueType vectype>:
497 FSMBInst<(outs VECREG:$rT), (ins VECREG:$rA),
498 [(set (vectype VECREG:$rT),
499 (SPUselmask (vectype VECREG:$rA)))]>;
501 multiclass FormSelectMaskBits {
502 def v16i8_r16: FSMBRegInst<R16C, v16i8>;
503 def v16i8: FSMBVecInst<v16i8>;
506 defm FSMB: FormSelectMaskBits;
508 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
509 // only 8-bits wide (even though it's input as 16-bits here)
511 class FSMHInst<dag OOL, dag IOL, list<dag> pattern>:
512 RRForm_1<0b10101101100, OOL, IOL, "fsmh\t$rT, $rA", SelectOp,
515 class FSMHRegInst<RegisterClass rclass, ValueType vectype>:
516 FSMHInst<(outs VECREG:$rT), (ins rclass:$rA),
517 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
519 class FSMHVecInst<ValueType vectype>:
520 FSMHInst<(outs VECREG:$rT), (ins VECREG:$rA),
521 [(set (vectype VECREG:$rT),
522 (SPUselmask (vectype VECREG:$rA)))]>;
524 multiclass FormSelectMaskHalfword {
525 def v8i16_r16: FSMHRegInst<R16C, v8i16>;
526 def v8i16: FSMHVecInst<v8i16>;
529 defm FSMH: FormSelectMaskHalfword;
531 // fsm: Form select mask for words. Like the other fsm* instructions,
532 // only the lower 4 bits of $rA are significant.
534 class FSMInst<dag OOL, dag IOL, list<dag> pattern>:
535 RRForm_1<0b00101101100, OOL, IOL, "fsm\t$rT, $rA", SelectOp,
538 class FSMRegInst<ValueType vectype, RegisterClass rclass>:
539 FSMInst<(outs VECREG:$rT), (ins rclass:$rA),
540 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
542 class FSMVecInst<ValueType vectype>:
543 FSMInst<(outs VECREG:$rT), (ins VECREG:$rA),
544 [(set (vectype VECREG:$rT), (SPUselmask (vectype VECREG:$rA)))]>;
546 multiclass FormSelectMaskWord {
547 def v4i32: FSMVecInst<v4i32>;
549 def r32 : FSMRegInst<v4i32, R32C>;
550 def r16 : FSMRegInst<v4i32, R16C>;
553 defm FSM : FormSelectMaskWord;
555 // Special case when used for i64 math operations
556 multiclass FormSelectMaskWord64 {
557 def r32 : FSMRegInst<v2i64, R32C>;
558 def r16 : FSMRegInst<v2i64, R16C>;
561 defm FSM64 : FormSelectMaskWord64;
563 //===----------------------------------------------------------------------===//
564 // Integer and Logical Operations:
565 //===----------------------------------------------------------------------===//
568 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
569 "ah\t$rT, $rA, $rB", IntegerOp,
570 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
572 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
573 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
576 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
577 "ah\t$rT, $rA, $rB", IntegerOp,
578 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
581 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
582 "ahi\t$rT, $rA, $val", IntegerOp,
583 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
584 v8i16SExt10Imm:$val))]>;
587 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
588 "ahi\t$rT, $rA, $val", IntegerOp,
589 [(set R16C:$rT, (add R16C:$rA, i16ImmSExt10:$val))]>;
591 // v4i32, i32 add instruction:
593 class AInst<dag OOL, dag IOL, list<dag> pattern>:
594 RRForm<0b00000011000, OOL, IOL,
595 "a\t$rT, $rA, $rB", IntegerOp,
598 class AVecInst<ValueType vectype>:
599 AInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
600 [(set (vectype VECREG:$rT), (add (vectype VECREG:$rA),
601 (vectype VECREG:$rB)))]>;
603 class ARegInst<RegisterClass rclass>:
604 AInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
605 [(set rclass:$rT, (add rclass:$rA, rclass:$rB))]>;
607 multiclass AddInstruction {
608 def v4i32: AVecInst<v4i32>;
609 def v16i8: AVecInst<v16i8>;
611 def r32: ARegInst<R32C>;
614 defm A : AddInstruction;
616 class AIInst<dag OOL, dag IOL, list<dag> pattern>:
617 RI10Form<0b00111000, OOL, IOL,
618 "ai\t$rT, $rA, $val", IntegerOp,
621 class AIVecInst<ValueType vectype, PatLeaf immpred>:
622 AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
623 [(set (vectype VECREG:$rT), (add (vectype VECREG:$rA), immpred:$val))]>;
625 class AIFPVecInst<ValueType vectype, PatLeaf immpred>:
626 AIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
629 class AIRegInst<RegisterClass rclass, PatLeaf immpred>:
630 AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val),
631 [(set rclass:$rT, (add rclass:$rA, immpred:$val))]>;
633 // This is used to add epsilons to floating point numbers in the f32 fdiv code:
634 class AIFPInst<RegisterClass rclass, PatLeaf immpred>:
635 AIInst<(outs rclass:$rT), (ins rclass:$rA, s10imm_i32:$val),
638 multiclass AddImmediate {
639 def v4i32: AIVecInst<v4i32, v4i32SExt10Imm>;
641 def r32: AIRegInst<R32C, i32ImmSExt10>;
643 def v4f32: AIFPVecInst<v4f32, v4i32SExt10Imm>;
644 def f32: AIFPInst<R32FP, i32ImmSExt10>;
647 defm AI : AddImmediate;
650 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
651 "sfh\t$rT, $rA, $rB", IntegerOp,
652 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
653 (v8i16 VECREG:$rB)))]>;
656 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
657 "sfh\t$rT, $rA, $rB", IntegerOp,
658 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
661 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
662 "sfhi\t$rT, $rA, $val", IntegerOp,
663 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
664 (v8i16 VECREG:$rA)))]>;
666 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
667 "sfhi\t$rT, $rA, $val", IntegerOp,
668 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
670 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
671 (ins VECREG:$rA, VECREG:$rB),
672 "sf\t$rT, $rA, $rB", IntegerOp,
673 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
675 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
676 "sf\t$rT, $rA, $rB", IntegerOp,
677 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
680 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
681 "sfi\t$rT, $rA, $val", IntegerOp,
682 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
683 (v4i32 VECREG:$rA)))]>;
685 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
686 (ins R32C:$rA, s10imm_i32:$val),
687 "sfi\t$rT, $rA, $val", IntegerOp,
688 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
690 // ADDX: only available in vector form, doesn't match a pattern.
691 class ADDXInst<dag OOL, dag IOL, list<dag> pattern>:
692 RRForm<0b00000010110, OOL, IOL,
693 "addx\t$rT, $rA, $rB",
696 class ADDXVecInst<ValueType vectype>:
697 ADDXInst<(outs VECREG:$rT),
698 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
700 RegConstraint<"$rCarry = $rT">,
703 class ADDXRegInst<RegisterClass rclass>:
704 ADDXInst<(outs rclass:$rT),
705 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
707 RegConstraint<"$rCarry = $rT">,
710 multiclass AddExtended {
711 def v2i64 : ADDXVecInst<v2i64>;
712 def v4i32 : ADDXVecInst<v4i32>;
713 def r64 : ADDXRegInst<R64C>;
714 def r32 : ADDXRegInst<R32C>;
717 defm ADDX : AddExtended;
719 // CG: Generate carry for add
720 class CGInst<dag OOL, dag IOL, list<dag> pattern>:
721 RRForm<0b01000011000, OOL, IOL,
725 class CGVecInst<ValueType vectype>:
726 CGInst<(outs VECREG:$rT),
727 (ins VECREG:$rA, VECREG:$rB),
730 class CGRegInst<RegisterClass rclass>:
731 CGInst<(outs rclass:$rT),
732 (ins rclass:$rA, rclass:$rB),
735 multiclass CarryGenerate {
736 def v2i64 : CGVecInst<v2i64>;
737 def v4i32 : CGVecInst<v4i32>;
738 def r64 : CGRegInst<R64C>;
739 def r32 : CGRegInst<R32C>;
742 defm CG : CarryGenerate;
744 // SFX: Subract from, extended. This is used in conjunction with BG to subtract
745 // with carry (borrow, in this case)
746 class SFXInst<dag OOL, dag IOL, list<dag> pattern>:
747 RRForm<0b10000010110, OOL, IOL,
748 "sfx\t$rT, $rA, $rB",
751 class SFXVecInst<ValueType vectype>:
752 SFXInst<(outs VECREG:$rT),
753 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
755 RegConstraint<"$rCarry = $rT">,
758 class SFXRegInst<RegisterClass rclass>:
759 SFXInst<(outs rclass:$rT),
760 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
762 RegConstraint<"$rCarry = $rT">,
765 multiclass SubtractExtended {
766 def v2i64 : SFXVecInst<v2i64>;
767 def v4i32 : SFXVecInst<v4i32>;
768 def r64 : SFXRegInst<R64C>;
769 def r32 : SFXRegInst<R32C>;
772 defm SFX : SubtractExtended;
774 // BG: only available in vector form, doesn't match a pattern.
775 class BGInst<dag OOL, dag IOL, list<dag> pattern>:
776 RRForm<0b01000010000, OOL, IOL,
780 class BGVecInst<ValueType vectype>:
781 BGInst<(outs VECREG:$rT),
782 (ins VECREG:$rA, VECREG:$rB),
785 class BGRegInst<RegisterClass rclass>:
786 BGInst<(outs rclass:$rT),
787 (ins rclass:$rA, rclass:$rB),
790 multiclass BorrowGenerate {
791 def v4i32 : BGVecInst<v4i32>;
792 def v2i64 : BGVecInst<v2i64>;
793 def r64 : BGRegInst<R64C>;
794 def r32 : BGRegInst<R32C>;
797 defm BG : BorrowGenerate;
799 // BGX: Borrow generate, extended.
801 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
803 "bgx\t$rT, $rA, $rB", IntegerOp,
805 RegConstraint<"$rCarry = $rT">,
808 // Halfword multiply variants:
809 // N.B: These can be used to build up larger quantities (16x16 -> 32)
812 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
813 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
817 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
818 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
819 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
821 // Unsigned 16-bit multiply:
823 class MPYUInst<dag OOL, dag IOL, list<dag> pattern>:
824 RRForm<0b00110011110, OOL, IOL,
825 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
829 MPYUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
833 MPYUInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
834 [(set R32C:$rT, (mul (zext R16C:$rA), (zext R16C:$rB)))]>;
837 MPYUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
840 // mpyi: multiply 16 x s10imm -> 32 result.
842 class MPYIInst<dag OOL, dag IOL, list<dag> pattern>:
843 RI10Form<0b00101110, OOL, IOL,
844 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
848 MPYIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
849 [(set (v8i16 VECREG:$rT),
850 (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
853 MPYIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
854 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
856 // mpyui: same issues as other multiplies, plus, this doesn't match a
857 // pattern... but may be used during target DAG selection or lowering
859 class MPYUIInst<dag OOL, dag IOL, list<dag> pattern>:
860 RI10Form<0b10101110, OOL, IOL,
861 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
865 MPYUIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
869 MPYUIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
872 // mpya: 16 x 16 + 16 -> 32 bit result
873 class MPYAInst<dag OOL, dag IOL, list<dag> pattern>:
874 RRRForm<0b0011, OOL, IOL,
875 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
879 MPYAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
880 [(set (v4i32 VECREG:$rT),
881 (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
882 (v8i16 VECREG:$rB)))),
883 (v4i32 VECREG:$rC)))]>;
886 MPYAInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
887 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
891 MPYAInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
892 [(set R32C:$rT, (add (mul (sext R16C:$rA), (sext R16C:$rB)),
895 def MPYAr32_sextinreg:
896 MPYAInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
897 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
898 (sext_inreg R32C:$rB, i16)),
901 // mpyh: multiply high, used to synthesize 32-bit multiplies
902 class MPYHInst<dag OOL, dag IOL, list<dag> pattern>:
903 RRForm<0b10100011110, OOL, IOL,
904 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
908 MPYHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
912 MPYHInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
915 // mpys: multiply high and shift right (returns the top half of
916 // a 16-bit multiply, sign extended to 32 bits.)
918 class MPYSInst<dag OOL, dag IOL>:
919 RRForm<0b11100011110, OOL, IOL,
920 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
924 MPYSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
927 MPYSInst<(outs R32C:$rT), (ins R16C:$rA, R16C:$rB)>;
929 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
930 // the top 16 bits of the $rA, $rB)
932 class MPYHHInst<dag OOL, dag IOL>:
933 RRForm<0b01100011110, OOL, IOL,
934 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
938 MPYHHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
941 MPYHHInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>;
943 // mpyhha: Multiply high-high, add to $rT:
945 class MPYHHAInst<dag OOL, dag IOL>:
946 RRForm<0b01100010110, OOL, IOL,
947 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
951 MPYHHAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
954 MPYHHAInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>;
956 // mpyhhu: Multiply high-high, unsigned, e.g.:
958 // +-------+-------+ +-------+-------+ +---------+
959 // | a0 . a1 | x | b0 . b1 | = | a0 x b0 |
960 // +-------+-------+ +-------+-------+ +---------+
962 // where a0, b0 are the upper 16 bits of the 32-bit word
964 class MPYHHUInst<dag OOL, dag IOL>:
965 RRForm<0b01110011110, OOL, IOL,
966 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
970 MPYHHUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
973 MPYHHUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>;
975 // mpyhhau: Multiply high-high, unsigned
977 class MPYHHAUInst<dag OOL, dag IOL>:
978 RRForm<0b01110010110, OOL, IOL,
979 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
983 MPYHHAUInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB)>;
986 MPYHHAUInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB)>;
988 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
989 // clz: Count leading zeroes
990 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
991 class CLZInst<dag OOL, dag IOL, list<dag> pattern>:
992 RRForm_1<0b10100101010, OOL, IOL, "clz\t$rT, $rA",
995 class CLZRegInst<RegisterClass rclass>:
996 CLZInst<(outs rclass:$rT), (ins rclass:$rA),
997 [(set rclass:$rT, (ctlz rclass:$rA))]>;
999 class CLZVecInst<ValueType vectype>:
1000 CLZInst<(outs VECREG:$rT), (ins VECREG:$rA),
1001 [(set (vectype VECREG:$rT), (ctlz (vectype VECREG:$rA)))]>;
1003 multiclass CountLeadingZeroes {
1004 def v4i32 : CLZVecInst<v4i32>;
1005 def r32 : CLZRegInst<R32C>;
1008 defm CLZ : CountLeadingZeroes;
1010 // cntb: Count ones in bytes (aka "population count")
1012 // NOTE: This instruction is really a vector instruction, but the custom
1013 // lowering code uses it in unorthodox ways to support CTPOP for other
1017 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
1018 "cntb\t$rT, $rA", IntegerOp,
1019 [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>;
1022 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
1023 "cntb\t$rT, $rA", IntegerOp,
1024 [(set (v8i16 VECREG:$rT), (SPUcntb (v8i16 VECREG:$rA)))]>;
1027 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
1028 "cntb\t$rT, $rA", IntegerOp,
1029 [(set (v4i32 VECREG:$rT), (SPUcntb (v4i32 VECREG:$rA)))]>;
1031 // gbb: Gather the low order bits from each byte in $rA into a single 16-bit
1032 // quantity stored into $rT's slot 0, upper 16 bits are zeroed, as are
1035 // Note: This instruction "pairs" with the fsmb instruction for all of the
1036 // various types defined here.
1038 // Note 2: The "VecInst" and "RegInst" forms refer to the result being either
1039 // a vector or register.
1041 class GBBInst<dag OOL, dag IOL, list<dag> pattern>:
1042 RRForm_1<0b01001101100, OOL, IOL, "gbb\t$rT, $rA", GatherOp, pattern>;
1044 class GBBRegInst<RegisterClass rclass, ValueType vectype>:
1045 GBBInst<(outs rclass:$rT), (ins VECREG:$rA),
1046 [/* no pattern */]>;
1048 class GBBVecInst<ValueType vectype>:
1049 GBBInst<(outs VECREG:$rT), (ins VECREG:$rA),
1050 [/* no pattern */]>;
1052 multiclass GatherBitsFromBytes {
1053 def v16i8_r32: GBBRegInst<R32C, v16i8>;
1054 def v16i8_r16: GBBRegInst<R16C, v16i8>;
1055 def v16i8: GBBVecInst<v16i8>;
1058 defm GBB: GatherBitsFromBytes;
1060 // gbh: Gather all low order bits from each halfword in $rA into a single
1061 // 8-bit quantity stored in $rT's slot 0, with the upper bits of $rT set to 0
1062 // and slots 1-3 also set to 0.
1064 // See notes for GBBInst, above.
1066 class GBHInst<dag OOL, dag IOL, list<dag> pattern>:
1067 RRForm_1<0b10001101100, OOL, IOL, "gbh\t$rT, $rA", GatherOp,
1070 class GBHRegInst<RegisterClass rclass, ValueType vectype>:
1071 GBHInst<(outs rclass:$rT), (ins VECREG:$rA),
1072 [/* no pattern */]>;
1074 class GBHVecInst<ValueType vectype>:
1075 GBHInst<(outs VECREG:$rT), (ins VECREG:$rA),
1076 [/* no pattern */]>;
1078 multiclass GatherBitsHalfword {
1079 def v8i16_r32: GBHRegInst<R32C, v8i16>;
1080 def v8i16_r16: GBHRegInst<R16C, v8i16>;
1081 def v8i16: GBHVecInst<v8i16>;
1084 defm GBH: GatherBitsHalfword;
1086 // gb: Gather all low order bits from each word in $rA into a single
1087 // 4-bit quantity stored in $rT's slot 0, upper bits in $rT set to 0,
1088 // as well as slots 1-3.
1090 // See notes for gbb, above.
1092 class GBInst<dag OOL, dag IOL, list<dag> pattern>:
1093 RRForm_1<0b00001101100, OOL, IOL, "gb\t$rT, $rA", GatherOp,
1096 class GBRegInst<RegisterClass rclass, ValueType vectype>:
1097 GBInst<(outs rclass:$rT), (ins VECREG:$rA),
1098 [/* no pattern */]>;
1100 class GBVecInst<ValueType vectype>:
1101 GBInst<(outs VECREG:$rT), (ins VECREG:$rA),
1102 [/* no pattern */]>;
1104 multiclass GatherBitsWord {
1105 def v4i32_r32: GBRegInst<R32C, v4i32>;
1106 def v4i32_r16: GBRegInst<R16C, v4i32>;
1107 def v4i32: GBVecInst<v4i32>;
1110 defm GB: GatherBitsWord;
1112 // avgb: average bytes
1114 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1115 "avgb\t$rT, $rA, $rB", ByteOp,
1118 // absdb: absolute difference of bytes
1120 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1121 "absdb\t$rT, $rA, $rB", ByteOp,
1124 // sumb: sum bytes into halfwords
1126 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1127 "sumb\t$rT, $rA, $rB", ByteOp,
1130 // Sign extension operations:
1131 class XSBHInst<dag OOL, dag IOL, list<dag> pattern>:
1132 RRForm_1<0b01101101010, OOL, IOL,
1133 "xsbh\t$rDst, $rSrc",
1134 IntegerOp, pattern>;
1136 class XSBHVecInst<ValueType vectype>:
1137 XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
1138 [(set (v8i16 VECREG:$rDst), (sext (vectype VECREG:$rSrc)))]>;
1140 class XSBHInRegInst<RegisterClass rclass, list<dag> pattern>:
1141 XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc),
1144 multiclass ExtendByteHalfword {
1145 def v16i8: XSBHVecInst<v8i16>;
1146 def r8: XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc),
1147 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
1148 def r16: XSBHInRegInst<R16C,
1149 [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>;
1151 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
1152 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
1153 // pattern below). Intentionally doesn't match a pattern because we want the
1154 // sext 8->32 pattern to do the work for us, namely because we need the extra
1156 def r32: XSBHInRegInst<R32C, [/* no pattern */]>;
1158 // Same as the 32-bit version, but for i64
1159 def r64: XSBHInRegInst<R64C, [/* no pattern */]>;
1162 defm XSBH : ExtendByteHalfword;
1164 // Sign extend halfwords to words:
1166 class XSHWInst<dag OOL, dag IOL, list<dag> pattern>:
1167 RRForm_1<0b01101101010, OOL, IOL, "xshw\t$rDest, $rSrc",
1168 IntegerOp, pattern>;
1170 class XSHWVecInst<ValueType in_vectype, ValueType out_vectype>:
1171 XSHWInst<(outs VECREG:$rDest), (ins VECREG:$rSrc),
1172 [(set (out_vectype VECREG:$rDest),
1173 (sext (in_vectype VECREG:$rSrc)))]>;
1175 class XSHWInRegInst<RegisterClass rclass, list<dag> pattern>:
1176 XSHWInst<(outs rclass:$rDest), (ins rclass:$rSrc),
1179 class XSHWRegInst<RegisterClass rclass>:
1180 XSHWInst<(outs rclass:$rDest), (ins R16C:$rSrc),
1181 [(set rclass:$rDest, (sext R16C:$rSrc))]>;
1183 multiclass ExtendHalfwordWord {
1184 def v4i32: XSHWVecInst<v4i32, v8i16>;
1186 def r16: XSHWRegInst<R32C>;
1188 def r32: XSHWInRegInst<R32C,
1189 [(set R32C:$rDest, (sext_inreg R32C:$rSrc, i16))]>;
1190 def r64: XSHWInRegInst<R64C, [/* no pattern */]>;
1193 defm XSHW : ExtendHalfwordWord;
1195 // Sign-extend words to doublewords (32->64 bits)
1197 class XSWDInst<dag OOL, dag IOL, list<dag> pattern>:
1198 RRForm_1<0b01100101010, OOL, IOL, "xswd\t$rDst, $rSrc",
1199 IntegerOp, pattern>;
1201 class XSWDVecInst<ValueType in_vectype, ValueType out_vectype>:
1202 XSWDInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
1203 [(set (out_vectype VECREG:$rDst),
1204 (sext (out_vectype VECREG:$rSrc)))]>;
1206 class XSWDRegInst<RegisterClass in_rclass, RegisterClass out_rclass>:
1207 XSWDInst<(outs out_rclass:$rDst), (ins in_rclass:$rSrc),
1208 [(set out_rclass:$rDst, (sext in_rclass:$rSrc))]>;
1210 multiclass ExtendWordToDoubleWord {
1211 def v2i64: XSWDVecInst<v4i32, v2i64>;
1212 def r64: XSWDRegInst<R32C, R64C>;
1214 def r64_inreg: XSWDInst<(outs R64C:$rDst), (ins R64C:$rSrc),
1215 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
1218 defm XSWD : ExtendWordToDoubleWord;
1222 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
1223 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
1224 IntegerOp, pattern>;
1226 class ANDVecInst<ValueType vectype>:
1227 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1228 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1229 (vectype VECREG:$rB)))]>;
1231 class ANDRegInst<RegisterClass rclass>:
1232 ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1233 [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>;
1235 multiclass BitwiseAnd
1237 def v16i8: ANDVecInst<v16i8>;
1238 def v8i16: ANDVecInst<v8i16>;
1239 def v4i32: ANDVecInst<v4i32>;
1240 def v2i64: ANDVecInst<v2i64>;
1242 def r128: ANDRegInst<GPRC>;
1243 def r64: ANDRegInst<R64C>;
1244 def r32: ANDRegInst<R32C>;
1245 def r16: ANDRegInst<R16C>;
1246 def r8: ANDRegInst<R8C>;
1248 //===---------------------------------------------
1249 // Special instructions to perform the fabs instruction
1250 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1251 [/* Intentionally does not match a pattern */]>;
1253 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB),
1254 [/* Intentionally does not match a pattern */]>;
1256 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1257 [/* Intentionally does not match a pattern */]>;
1259 //===---------------------------------------------
1261 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
1262 // quantities -- see 16->32 zext pattern.
1264 // This pattern is somewhat artificial, since it might match some
1265 // compiler generated pattern but it is unlikely to do so.
1267 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
1268 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
1271 defm AND : BitwiseAnd;
1273 // N.B.: vnot_conv is one of those special target selection pattern fragments,
1274 // in which we expect there to be a bit_convert on the constant. Bear in mind
1275 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
1276 // constant -1 vector.)
1278 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
1279 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
1280 IntegerOp, pattern>;
1282 class ANDCVecInst<ValueType vectype, PatFrag vnot_frag = vnot>:
1283 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1284 [(set (vectype VECREG:$rT),
1285 (and (vectype VECREG:$rA),
1286 (vnot_frag (vectype VECREG:$rB))))]>;
1288 class ANDCRegInst<RegisterClass rclass>:
1289 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1290 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
1292 multiclass AndComplement
1294 def v16i8: ANDCVecInst<v16i8>;
1295 def v8i16: ANDCVecInst<v8i16>;
1296 def v4i32: ANDCVecInst<v4i32>;
1297 def v2i64: ANDCVecInst<v2i64>;
1299 def r128: ANDCRegInst<GPRC>;
1300 def r64: ANDCRegInst<R64C>;
1301 def r32: ANDCRegInst<R32C>;
1302 def r16: ANDCRegInst<R16C>;
1303 def r8: ANDCRegInst<R8C>;
1305 // Sometimes, the xor pattern has a bitcast constant:
1306 def v16i8_conv: ANDCVecInst<v16i8, vnot_conv>;
1309 defm ANDC : AndComplement;
1311 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1312 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1315 multiclass AndByteImm
1317 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1318 [(set (v16i8 VECREG:$rT),
1319 (and (v16i8 VECREG:$rA),
1320 (v16i8 v16i8U8Imm:$val)))]>;
1322 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1323 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1326 defm ANDBI : AndByteImm;
1328 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1329 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1332 multiclass AndHalfwordImm
1334 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1335 [(set (v8i16 VECREG:$rT),
1336 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1338 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1339 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1341 // Zero-extend i8 to i16:
1342 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1343 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1346 defm ANDHI : AndHalfwordImm;
1348 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1349 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1350 IntegerOp, pattern>;
1352 multiclass AndWordImm
1354 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1355 [(set (v4i32 VECREG:$rT),
1356 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1358 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1359 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1361 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1363 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1365 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1367 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1368 // zext 16->32 pattern below.
1370 // Note that this pattern is somewhat artificial, since it might match
1371 // something the compiler generates but is unlikely to occur in practice.
1372 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1374 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1377 defm ANDI : AndWordImm;
1379 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1380 // Bitwise OR group:
1381 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1383 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1384 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1385 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1386 IntegerOp, pattern>;
1388 class ORVecInst<ValueType vectype>:
1389 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1390 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1391 (vectype VECREG:$rB)))]>;
1393 class ORRegInst<RegisterClass rclass>:
1394 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1395 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1397 // ORCvtForm: OR conversion form
1399 // This is used to "convert" the preferred slot to its vector equivalent, as
1400 // well as convert a vector back to its preferred slot.
1402 // These are effectively no-ops, but need to exist for proper type conversion
1403 // and type coercion.
1405 class ORCvtForm<dag OOL, dag IOL, list<dag> pattern = [/* no pattern */]>
1406 : SPUInstr<OOL, IOL, "or\t$rT, $rA, $rA", IntegerOp> {
1410 let Pattern = pattern;
1412 let Inst{0-10} = 0b10000010000;
1413 let Inst{11-17} = RA;
1414 let Inst{18-24} = RA;
1415 let Inst{25-31} = RT;
1418 class ORPromoteScalar<RegisterClass rclass>:
1419 ORCvtForm<(outs VECREG:$rT), (ins rclass:$rA)>;
1421 class ORExtractElt<RegisterClass rclass>:
1422 ORCvtForm<(outs rclass:$rT), (ins VECREG:$rA)>;
1424 /* class ORCvtRegGPRC<RegisterClass rclass>:
1425 ORCvtForm<(outs GPRC:$rT), (ins rclass:$rA)>; */
1427 /* class ORCvtGPRCReg<RegisterClass rclass>:
1428 ORCvtForm<(outs rclass:$rT), (ins GPRC:$rA)>; */
1430 class ORCvtFormR32Reg<RegisterClass rclass, list<dag> pattern = [ ]>:
1431 ORCvtForm<(outs rclass:$rT), (ins R32C:$rA), pattern>;
1433 class ORCvtFormRegR32<RegisterClass rclass, list<dag> pattern = [ ]>:
1434 ORCvtForm<(outs R32C:$rT), (ins rclass:$rA), pattern>;
1436 class ORCvtFormR64Reg<RegisterClass rclass, list<dag> pattern = [ ]>:
1437 ORCvtForm<(outs rclass:$rT), (ins R64C:$rA), pattern>;
1439 class ORCvtFormRegR64<RegisterClass rclass, list<dag> pattern = [ ]>:
1440 ORCvtForm<(outs R64C:$rT), (ins rclass:$rA), pattern>;
1443 ORCvtForm<(outs VECREG:$rT), (ins GPRC:$rA)>;
1446 ORCvtForm<(outs GPRC:$rT), (ins VECREG:$rA)>;
1448 multiclass BitwiseOr
1450 def v16i8: ORVecInst<v16i8>;
1451 def v8i16: ORVecInst<v8i16>;
1452 def v4i32: ORVecInst<v4i32>;
1453 def v2i64: ORVecInst<v2i64>;
1455 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1456 [(set (v4f32 VECREG:$rT),
1457 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1458 (v4i32 VECREG:$rB)))))]>;
1460 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1461 [(set (v2f64 VECREG:$rT),
1462 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1463 (v2i64 VECREG:$rB)))))]>;
1465 def r128: ORRegInst<GPRC>;
1466 def r64: ORRegInst<R64C>;
1467 def r32: ORRegInst<R32C>;
1468 def r16: ORRegInst<R16C>;
1469 def r8: ORRegInst<R8C>;
1471 // OR instructions used to copy f32 and f64 registers.
1472 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1473 [/* no pattern */]>;
1475 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1476 [/* no pattern */]>;
1478 // scalar->vector promotion, prefslot2vec:
1479 def v16i8_i8: ORPromoteScalar<R8C>;
1480 def v8i16_i16: ORPromoteScalar<R16C>;
1481 def v4i32_i32: ORPromoteScalar<R32C>;
1482 def v2i64_i64: ORPromoteScalar<R64C>;
1483 def v4f32_f32: ORPromoteScalar<R32FP>;
1484 def v2f64_f64: ORPromoteScalar<R64FP>;
1486 // vector->scalar demotion, vec2prefslot:
1487 def i8_v16i8: ORExtractElt<R8C>;
1488 def i16_v8i16: ORExtractElt<R16C>;
1489 def i32_v4i32: ORExtractElt<R32C>;
1490 def i64_v2i64: ORExtractElt<R64C>;
1491 def f32_v4f32: ORExtractElt<R32FP>;
1492 def f64_v2f64: ORExtractElt<R64FP>;
1494 // Conversion from vector to GPRC
1495 def i128_vec: ORCvtVecGPRC;
1497 // Conversion from GPRC to vector
1498 def vec_i128: ORCvtGPRCVec;
1501 // Conversion from register to GPRC
1502 def i128_r64: ORCvtRegGPRC<R64C>;
1503 def i128_f64: ORCvtRegGPRC<R64FP>;
1504 def i128_r32: ORCvtRegGPRC<R32C>;
1505 def i128_f32: ORCvtRegGPRC<R32FP>;
1506 def i128_r16: ORCvtRegGPRC<R16C>;
1507 def i128_r8: ORCvtRegGPRC<R8C>;
1509 // Conversion from GPRC to register
1510 def r64_i128: ORCvtGPRCReg<R64C>;
1511 def f64_i128: ORCvtGPRCReg<R64FP>;
1512 def r32_i128: ORCvtGPRCReg<R32C>;
1513 def f32_i128: ORCvtGPRCReg<R32FP>;
1514 def r16_i128: ORCvtGPRCReg<R16C>;
1515 def r8_i128: ORCvtGPRCReg<R8C>;
1518 // Conversion from register to R32C:
1519 def r32_r16: ORCvtFormRegR32<R16C>;
1520 def r32_r8: ORCvtFormRegR32<R8C>;
1522 // Conversion from R32C to register
1523 def r32_r16: ORCvtFormR32Reg<R16C>;
1524 def r32_r8: ORCvtFormR32Reg<R8C>;
1527 // Conversion from R64C to register:
1528 def r32_r64: ORCvtFormR64Reg<R32C>;
1529 // def r16_r64: ORCvtFormR64Reg<R16C>;
1530 // def r8_r64: ORCvtFormR64Reg<R8C>;
1532 // Conversion to R64C from register:
1533 def r64_r32: ORCvtFormRegR64<R32C>;
1534 // def r64_r16: ORCvtFormRegR64<R16C>;
1535 // def r64_r8: ORCvtFormRegR64<R8C>;
1537 // bitconvert patterns:
1538 def r32_f32: ORCvtFormR32Reg<R32FP,
1539 [(set R32FP:$rT, (bitconvert R32C:$rA))]>;
1540 def f32_r32: ORCvtFormRegR32<R32FP,
1541 [(set R32C:$rT, (bitconvert R32FP:$rA))]>;
1543 def r64_f64: ORCvtFormR64Reg<R64FP,
1544 [(set R64FP:$rT, (bitconvert R64C:$rA))]>;
1545 def f64_r64: ORCvtFormRegR64<R64FP,
1546 [(set R64C:$rT, (bitconvert R64FP:$rA))]>;
1549 defm OR : BitwiseOr;
1551 // scalar->vector promotion patterns (preferred slot to vector):
1552 def : Pat<(v16i8 (SPUprefslot2vec R8C:$rA)),
1553 (ORv16i8_i8 R8C:$rA)>;
1555 def : Pat<(v8i16 (SPUprefslot2vec R16C:$rA)),
1556 (ORv8i16_i16 R16C:$rA)>;
1558 def : Pat<(v4i32 (SPUprefslot2vec R32C:$rA)),
1559 (ORv4i32_i32 R32C:$rA)>;
1561 def : Pat<(v2i64 (SPUprefslot2vec R64C:$rA)),
1562 (ORv2i64_i64 R64C:$rA)>;
1564 def : Pat<(v4f32 (SPUprefslot2vec R32FP:$rA)),
1565 (ORv4f32_f32 R32FP:$rA)>;
1567 def : Pat<(v2f64 (SPUprefslot2vec R64FP:$rA)),
1568 (ORv2f64_f64 R64FP:$rA)>;
1570 // ORi*_v*: Used to extract vector element 0 (the preferred slot), otherwise
1571 // known as converting the vector back to its preferred slot
1573 def : Pat<(SPUvec2prefslot (v16i8 VECREG:$rA)),
1574 (ORi8_v16i8 VECREG:$rA)>;
1576 def : Pat<(SPUvec2prefslot (v8i16 VECREG:$rA)),
1577 (ORi16_v8i16 VECREG:$rA)>;
1579 def : Pat<(SPUvec2prefslot (v4i32 VECREG:$rA)),
1580 (ORi32_v4i32 VECREG:$rA)>;
1582 def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)),
1583 (ORi64_v2i64 VECREG:$rA)>;
1585 def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)),
1586 (ORf32_v4f32 VECREG:$rA)>;
1588 def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)),
1589 (ORf64_v2f64 VECREG:$rA)>;
1591 // Load Register: This is an assembler alias for a bitwise OR of a register
1592 // against itself. It's here because it brings some clarity to assembly
1595 let hasCtrlDep = 1 in {
1596 class LRInst<dag OOL, dag IOL>
1597 : SPUInstr<OOL, IOL, "lr\t$rT, $rA", IntegerOp> {
1601 let Pattern = [/*no pattern*/];
1603 let Inst{0-10} = 0b10000010000; /* It's an OR operation */
1604 let Inst{11-17} = RA;
1605 let Inst{18-24} = RA;
1606 let Inst{25-31} = RT;
1609 class LRVecInst<ValueType vectype>:
1610 LRInst<(outs VECREG:$rT), (ins VECREG:$rA)>;
1612 class LRRegInst<RegisterClass rclass>:
1613 LRInst<(outs rclass:$rT), (ins rclass:$rA)>;
1615 multiclass LoadRegister {
1616 def v2i64: LRVecInst<v2i64>;
1617 def v2f64: LRVecInst<v2f64>;
1618 def v4i32: LRVecInst<v4i32>;
1619 def v4f32: LRVecInst<v4f32>;
1620 def v8i16: LRVecInst<v8i16>;
1621 def v16i8: LRVecInst<v16i8>;
1623 def r128: LRRegInst<GPRC>;
1624 def r64: LRRegInst<R64C>;
1625 def f64: LRRegInst<R64FP>;
1626 def r32: LRRegInst<R32C>;
1627 def f32: LRRegInst<R32FP>;
1628 def r16: LRRegInst<R16C>;
1629 def r8: LRRegInst<R8C>;
1632 defm LR: LoadRegister;
1635 // ORC: Bitwise "or" with complement (c = a | ~b)
1637 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1638 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1639 IntegerOp, pattern>;
1641 class ORCVecInst<ValueType vectype>:
1642 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1643 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1644 (vnot (vectype VECREG:$rB))))]>;
1646 class ORCRegInst<RegisterClass rclass>:
1647 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1648 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1650 multiclass BitwiseOrComplement
1652 def v16i8: ORCVecInst<v16i8>;
1653 def v8i16: ORCVecInst<v8i16>;
1654 def v4i32: ORCVecInst<v4i32>;
1655 def v2i64: ORCVecInst<v2i64>;
1657 def r128: ORCRegInst<GPRC>;
1658 def r64: ORCRegInst<R64C>;
1659 def r32: ORCRegInst<R32C>;
1660 def r16: ORCRegInst<R16C>;
1661 def r8: ORCRegInst<R8C>;
1664 defm ORC : BitwiseOrComplement;
1666 // OR byte immediate
1667 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1668 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1669 IntegerOp, pattern>;
1671 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1672 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1673 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1674 (vectype immpred:$val)))]>;
1676 multiclass BitwiseOrByteImm
1678 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1680 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1681 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1684 defm ORBI : BitwiseOrByteImm;
1686 // OR halfword immediate
1687 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1688 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1689 IntegerOp, pattern>;
1691 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1692 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1693 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1696 multiclass BitwiseOrHalfwordImm
1698 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1700 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1701 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1703 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1704 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1705 [(set R16C:$rT, (or (anyext R8C:$rA),
1706 i16ImmSExt10:$val))]>;
1709 defm ORHI : BitwiseOrHalfwordImm;
1711 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1712 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1713 IntegerOp, pattern>;
1715 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1716 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1717 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1720 // Bitwise "or" with immediate
1721 multiclass BitwiseOrImm
1723 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1725 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1726 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1728 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1729 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1730 // infra "anyext 16->32" pattern.)
1731 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1732 [(set R32C:$rT, (or (anyext R16C:$rA),
1733 i32ImmSExt10:$val))]>;
1735 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1736 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1737 // infra "anyext 16->32" pattern.)
1738 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1739 [(set R32C:$rT, (or (anyext R8C:$rA),
1740 i32ImmSExt10:$val))]>;
1743 defm ORI : BitwiseOrImm;
1745 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1746 // $rT[0], slots 1-3 are zeroed.
1748 // FIXME: Needs to match an intrinsic pattern.
1750 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1751 "orx\t$rT, $rA, $rB", IntegerOp,
1756 class XORInst<dag OOL, dag IOL, list<dag> pattern> :
1757 RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB",
1758 IntegerOp, pattern>;
1760 class XORVecInst<ValueType vectype>:
1761 XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1762 [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA),
1763 (vectype VECREG:$rB)))]>;
1765 class XORRegInst<RegisterClass rclass>:
1766 XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1767 [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>;
1769 multiclass BitwiseExclusiveOr
1771 def v16i8: XORVecInst<v16i8>;
1772 def v8i16: XORVecInst<v8i16>;
1773 def v4i32: XORVecInst<v4i32>;
1774 def v2i64: XORVecInst<v2i64>;
1776 def r128: XORRegInst<GPRC>;
1777 def r64: XORRegInst<R64C>;
1778 def r32: XORRegInst<R32C>;
1779 def r16: XORRegInst<R16C>;
1780 def r8: XORRegInst<R8C>;
1782 // XOR instructions used to negate f32 and f64 quantities.
1784 def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1785 [/* no pattern */]>;
1787 def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64C:$rB),
1788 [/* no pattern */]>;
1790 def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1791 [/* no pattern, see fneg{32,64} */]>;
1794 defm XOR : BitwiseExclusiveOr;
1796 //==----------------------------------------------------------
1798 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1799 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1800 IntegerOp, pattern>;
1802 multiclass XorByteImm
1805 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1806 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1809 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1810 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1813 defm XORBI : XorByteImm;
1816 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1817 "xorhi\t$rT, $rA, $val", IntegerOp,
1818 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1819 v8i16SExt10Imm:$val))]>;
1822 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1823 "xorhi\t$rT, $rA, $val", IntegerOp,
1824 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1827 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
1828 "xori\t$rT, $rA, $val", IntegerOp,
1829 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1830 v4i32SExt10Imm:$val))]>;
1833 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1834 "xori\t$rT, $rA, $val", IntegerOp,
1835 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1839 class NANDInst<dag OOL, dag IOL, list<dag> pattern>:
1840 RRForm<0b10010011000, OOL, IOL, "nand\t$rT, $rA, $rB",
1841 IntegerOp, pattern>;
1843 class NANDVecInst<ValueType vectype>:
1844 NANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1845 [(set (vectype VECREG:$rT), (vnot (and (vectype VECREG:$rA),
1846 (vectype VECREG:$rB))))]>;
1847 class NANDRegInst<RegisterClass rclass>:
1848 NANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1849 [(set rclass:$rT, (not (and rclass:$rA, rclass:$rB)))]>;
1851 multiclass BitwiseNand
1853 def v16i8: NANDVecInst<v16i8>;
1854 def v8i16: NANDVecInst<v8i16>;
1855 def v4i32: NANDVecInst<v4i32>;
1856 def v2i64: NANDVecInst<v2i64>;
1858 def r128: NANDRegInst<GPRC>;
1859 def r64: NANDRegInst<R64C>;
1860 def r32: NANDRegInst<R32C>;
1861 def r16: NANDRegInst<R16C>;
1862 def r8: NANDRegInst<R8C>;
1865 defm NAND : BitwiseNand;
1869 class NORInst<dag OOL, dag IOL, list<dag> pattern>:
1870 RRForm<0b10010010000, OOL, IOL, "nor\t$rT, $rA, $rB",
1871 IntegerOp, pattern>;
1873 class NORVecInst<ValueType vectype>:
1874 NORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1875 [(set (vectype VECREG:$rT), (vnot (or (vectype VECREG:$rA),
1876 (vectype VECREG:$rB))))]>;
1877 class NORRegInst<RegisterClass rclass>:
1878 NORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1879 [(set rclass:$rT, (not (or rclass:$rA, rclass:$rB)))]>;
1881 multiclass BitwiseNor
1883 def v16i8: NORVecInst<v16i8>;
1884 def v8i16: NORVecInst<v8i16>;
1885 def v4i32: NORVecInst<v4i32>;
1886 def v2i64: NORVecInst<v2i64>;
1888 def r128: NORRegInst<GPRC>;
1889 def r64: NORRegInst<R64C>;
1890 def r32: NORRegInst<R32C>;
1891 def r16: NORRegInst<R16C>;
1892 def r8: NORRegInst<R8C>;
1895 defm NOR : BitwiseNor;
1898 class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
1899 RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC",
1900 IntegerOp, pattern>;
1902 class SELBVecInst<ValueType vectype, PatFrag vnot_frag = vnot>:
1903 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1904 [(set (vectype VECREG:$rT),
1905 (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)),
1906 (and (vnot_frag (vectype VECREG:$rC)),
1907 (vectype VECREG:$rA))))]>;
1909 class SELBVecVCondInst<ValueType vectype>:
1910 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1911 [(set (vectype VECREG:$rT),
1912 (select (vectype VECREG:$rC),
1913 (vectype VECREG:$rB),
1914 (vectype VECREG:$rA)))]>;
1916 class SELBVecCondInst<ValueType vectype>:
1917 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, R32C:$rC),
1918 [(set (vectype VECREG:$rT),
1920 (vectype VECREG:$rB),
1921 (vectype VECREG:$rA)))]>;
1923 class SELBRegInst<RegisterClass rclass>:
1924 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
1926 (or (and rclass:$rB, rclass:$rC),
1927 (and rclass:$rA, (not rclass:$rC))))]>;
1929 class SELBRegCondInst<RegisterClass rcond, RegisterClass rclass>:
1930 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rcond:$rC),
1932 (select rcond:$rC, rclass:$rB, rclass:$rA))]>;
1934 multiclass SelectBits
1936 def v16i8: SELBVecInst<v16i8>;
1937 def v8i16: SELBVecInst<v8i16>;
1938 def v4i32: SELBVecInst<v4i32>;
1939 def v2i64: SELBVecInst<v2i64, vnot_conv>;
1941 def r128: SELBRegInst<GPRC>;
1942 def r64: SELBRegInst<R64C>;
1943 def r32: SELBRegInst<R32C>;
1944 def r16: SELBRegInst<R16C>;
1945 def r8: SELBRegInst<R8C>;
1947 def v16i8_cond: SELBVecCondInst<v16i8>;
1948 def v8i16_cond: SELBVecCondInst<v8i16>;
1949 def v4i32_cond: SELBVecCondInst<v4i32>;
1950 def v2i64_cond: SELBVecCondInst<v2i64>;
1952 def v16i8_vcond: SELBVecCondInst<v16i8>;
1953 def v8i16_vcond: SELBVecCondInst<v8i16>;
1954 def v4i32_vcond: SELBVecCondInst<v4i32>;
1955 def v2i64_vcond: SELBVecCondInst<v2i64>;
1958 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1959 [(set (v4f32 VECREG:$rT),
1960 (select (v4i32 VECREG:$rC),
1962 (v4f32 VECREG:$rA)))]>;
1964 // SELBr64_cond is defined in SPU64InstrInfo.td
1965 def r32_cond: SELBRegCondInst<R32C, R32C>;
1966 def f32_cond: SELBRegCondInst<R32C, R32FP>;
1967 def r16_cond: SELBRegCondInst<R16C, R16C>;
1968 def r8_cond: SELBRegCondInst<R8C, R8C>;
1971 defm SELB : SelectBits;
1973 class SPUselbPatVec<ValueType vectype, SPUInstr inst>:
1974 Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)),
1975 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1977 def : SPUselbPatVec<v16i8, SELBv16i8>;
1978 def : SPUselbPatVec<v8i16, SELBv8i16>;
1979 def : SPUselbPatVec<v4i32, SELBv4i32>;
1980 def : SPUselbPatVec<v2i64, SELBv2i64>;
1982 class SPUselbPatReg<RegisterClass rclass, SPUInstr inst>:
1983 Pat<(SPUselb rclass:$rA, rclass:$rB, rclass:$rC),
1984 (inst rclass:$rA, rclass:$rB, rclass:$rC)>;
1986 def : SPUselbPatReg<R8C, SELBr8>;
1987 def : SPUselbPatReg<R16C, SELBr16>;
1988 def : SPUselbPatReg<R32C, SELBr32>;
1989 def : SPUselbPatReg<R64C, SELBr64>;
1991 // EQV: Equivalence (1 for each same bit, otherwise 0)
1993 // Note: There are a lot of ways to match this bit operator and these patterns
1994 // attempt to be as exhaustive as possible.
1996 class EQVInst<dag OOL, dag IOL, list<dag> pattern>:
1997 RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB",
1998 IntegerOp, pattern>;
2000 class EQVVecInst<ValueType vectype>:
2001 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2002 [(set (vectype VECREG:$rT),
2003 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
2004 (and (vnot (vectype VECREG:$rA)),
2005 (vnot (vectype VECREG:$rB)))))]>;
2007 class EQVRegInst<RegisterClass rclass>:
2008 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2009 [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB),
2010 (and (not rclass:$rA), (not rclass:$rB))))]>;
2012 class EQVVecPattern1<ValueType vectype>:
2013 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2014 [(set (vectype VECREG:$rT),
2015 (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>;
2017 class EQVRegPattern1<RegisterClass rclass>:
2018 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2019 [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>;
2021 class EQVVecPattern2<ValueType vectype>:
2022 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2023 [(set (vectype VECREG:$rT),
2024 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
2025 (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>;
2027 class EQVRegPattern2<RegisterClass rclass>:
2028 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2030 (or (and rclass:$rA, rclass:$rB),
2031 (not (or rclass:$rA, rclass:$rB))))]>;
2033 class EQVVecPattern3<ValueType vectype>:
2034 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2035 [(set (vectype VECREG:$rT),
2036 (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>;
2038 class EQVRegPattern3<RegisterClass rclass>:
2039 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2040 [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>;
2042 multiclass BitEquivalence
2044 def v16i8: EQVVecInst<v16i8>;
2045 def v8i16: EQVVecInst<v8i16>;
2046 def v4i32: EQVVecInst<v4i32>;
2047 def v2i64: EQVVecInst<v2i64>;
2049 def v16i8_1: EQVVecPattern1<v16i8>;
2050 def v8i16_1: EQVVecPattern1<v8i16>;
2051 def v4i32_1: EQVVecPattern1<v4i32>;
2052 def v2i64_1: EQVVecPattern1<v2i64>;
2054 def v16i8_2: EQVVecPattern2<v16i8>;
2055 def v8i16_2: EQVVecPattern2<v8i16>;
2056 def v4i32_2: EQVVecPattern2<v4i32>;
2057 def v2i64_2: EQVVecPattern2<v2i64>;
2059 def v16i8_3: EQVVecPattern3<v16i8>;
2060 def v8i16_3: EQVVecPattern3<v8i16>;
2061 def v4i32_3: EQVVecPattern3<v4i32>;
2062 def v2i64_3: EQVVecPattern3<v2i64>;
2064 def r128: EQVRegInst<GPRC>;
2065 def r64: EQVRegInst<R64C>;
2066 def r32: EQVRegInst<R32C>;
2067 def r16: EQVRegInst<R16C>;
2068 def r8: EQVRegInst<R8C>;
2070 def r128_1: EQVRegPattern1<GPRC>;
2071 def r64_1: EQVRegPattern1<R64C>;
2072 def r32_1: EQVRegPattern1<R32C>;
2073 def r16_1: EQVRegPattern1<R16C>;
2074 def r8_1: EQVRegPattern1<R8C>;
2076 def r128_2: EQVRegPattern2<GPRC>;
2077 def r64_2: EQVRegPattern2<R64C>;
2078 def r32_2: EQVRegPattern2<R32C>;
2079 def r16_2: EQVRegPattern2<R16C>;
2080 def r8_2: EQVRegPattern2<R8C>;
2082 def r128_3: EQVRegPattern3<GPRC>;
2083 def r64_3: EQVRegPattern3<R64C>;
2084 def r32_3: EQVRegPattern3<R32C>;
2085 def r16_3: EQVRegPattern3<R16C>;
2086 def r8_3: EQVRegPattern3<R8C>;
2089 defm EQV: BitEquivalence;
2091 //===----------------------------------------------------------------------===//
2092 // Vector shuffle...
2093 //===----------------------------------------------------------------------===//
2094 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
2095 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
2096 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
2097 // the SPUISD::SHUFB opcode.
2098 //===----------------------------------------------------------------------===//
2100 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
2101 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
2102 IntegerOp, pattern>;
2104 class SHUFBVecInst<ValueType resultvec, ValueType maskvec>:
2105 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2106 [(set (resultvec VECREG:$rT),
2107 (SPUshuffle (resultvec VECREG:$rA),
2108 (resultvec VECREG:$rB),
2109 (maskvec VECREG:$rC)))]>;
2111 class SHUFBGPRCInst:
2112 SHUFBInst<(outs VECREG:$rT), (ins GPRC:$rA, GPRC:$rB, VECREG:$rC),
2113 [/* no pattern */]>;
2115 multiclass ShuffleBytes
2117 def v16i8 : SHUFBVecInst<v16i8, v16i8>;
2118 def v16i8_m32 : SHUFBVecInst<v16i8, v4i32>;
2119 def v8i16 : SHUFBVecInst<v8i16, v16i8>;
2120 def v8i16_m32 : SHUFBVecInst<v8i16, v4i32>;
2121 def v4i32 : SHUFBVecInst<v4i32, v16i8>;
2122 def v4i32_m32 : SHUFBVecInst<v4i32, v4i32>;
2123 def v2i64 : SHUFBVecInst<v2i64, v16i8>;
2124 def v2i64_m32 : SHUFBVecInst<v2i64, v4i32>;
2126 def v4f32 : SHUFBVecInst<v4f32, v16i8>;
2127 def v4f32_m32 : SHUFBVecInst<v4f32, v4i32>;
2129 def v2f64 : SHUFBVecInst<v2f64, v16i8>;
2130 def v2f64_m32 : SHUFBVecInst<v2f64, v4i32>;
2132 def gprc : SHUFBGPRCInst;
2135 defm SHUFB : ShuffleBytes;
2137 //===----------------------------------------------------------------------===//
2138 // Shift and rotate group:
2139 //===----------------------------------------------------------------------===//
2141 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
2142 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
2143 RotateShift, pattern>;
2145 class SHLHVecInst<ValueType vectype>:
2146 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2147 [(set (vectype VECREG:$rT),
2148 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
2150 multiclass ShiftLeftHalfword
2152 def v8i16: SHLHVecInst<v8i16>;
2153 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2154 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
2155 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2156 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
2159 defm SHLH : ShiftLeftHalfword;
2161 //===----------------------------------------------------------------------===//
2163 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
2164 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
2165 RotateShift, pattern>;
2167 class SHLHIVecInst<ValueType vectype>:
2168 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2169 [(set (vectype VECREG:$rT),
2170 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2172 multiclass ShiftLeftHalfwordImm
2174 def v8i16: SHLHIVecInst<v8i16>;
2175 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2176 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
2179 defm SHLHI : ShiftLeftHalfwordImm;
2181 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
2182 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
2184 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
2185 (SHLHIr16 R16C:$rA, uimm7:$val)>;
2187 //===----------------------------------------------------------------------===//
2189 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
2190 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
2191 RotateShift, pattern>;
2193 multiclass ShiftLeftWord
2196 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2197 [(set (v4i32 VECREG:$rT),
2198 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
2200 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2201 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
2204 defm SHL: ShiftLeftWord;
2206 //===----------------------------------------------------------------------===//
2208 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
2209 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
2210 RotateShift, pattern>;
2212 multiclass ShiftLeftWordImm
2215 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2216 [(set (v4i32 VECREG:$rT),
2217 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
2220 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2221 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
2224 defm SHLI : ShiftLeftWordImm;
2226 //===----------------------------------------------------------------------===//
2227 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
2228 // register) to the left. Vector form is here to ensure type correctness.
2230 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
2231 // of 7 bits is actually possible.
2233 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
2234 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
2235 // bytes with SHLQBY.
2237 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2238 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
2239 RotateShift, pattern>;
2241 class SHLQBIVecInst<ValueType vectype>:
2242 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2243 [(set (vectype VECREG:$rT),
2244 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
2246 class SHLQBIRegInst<RegisterClass rclass>:
2247 SHLQBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2248 [/* no pattern */]>;
2250 multiclass ShiftLeftQuadByBits
2252 def v16i8: SHLQBIVecInst<v16i8>;
2253 def v8i16: SHLQBIVecInst<v8i16>;
2254 def v4i32: SHLQBIVecInst<v4i32>;
2255 def v4f32: SHLQBIVecInst<v4f32>;
2256 def v2i64: SHLQBIVecInst<v2i64>;
2257 def v2f64: SHLQBIVecInst<v2f64>;
2259 def r128: SHLQBIRegInst<GPRC>;
2262 defm SHLQBI : ShiftLeftQuadByBits;
2264 // See note above on SHLQBI. In this case, the predicate actually does then
2265 // enforcement, whereas with SHLQBI, we have to "take it on faith."
2266 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2267 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
2268 RotateShift, pattern>;
2270 class SHLQBIIVecInst<ValueType vectype>:
2271 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2272 [(set (vectype VECREG:$rT),
2273 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
2275 multiclass ShiftLeftQuadByBitsImm
2277 def v16i8 : SHLQBIIVecInst<v16i8>;
2278 def v8i16 : SHLQBIIVecInst<v8i16>;
2279 def v4i32 : SHLQBIIVecInst<v4i32>;
2280 def v4f32 : SHLQBIIVecInst<v4f32>;
2281 def v2i64 : SHLQBIIVecInst<v2i64>;
2282 def v2f64 : SHLQBIIVecInst<v2f64>;
2285 defm SHLQBII : ShiftLeftQuadByBitsImm;
2287 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
2288 // not by bits. See notes above on SHLQBI.
2290 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2291 RI7Form<0b11111011100, OOL, IOL, "shlqby\t$rT, $rA, $rB",
2292 RotateShift, pattern>;
2294 class SHLQBYVecInst<ValueType vectype>:
2295 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2296 [(set (vectype VECREG:$rT),
2297 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
2299 multiclass ShiftLeftQuadBytes
2301 def v16i8: SHLQBYVecInst<v16i8>;
2302 def v8i16: SHLQBYVecInst<v8i16>;
2303 def v4i32: SHLQBYVecInst<v4i32>;
2304 def v4f32: SHLQBYVecInst<v4f32>;
2305 def v2i64: SHLQBYVecInst<v2i64>;
2306 def v2f64: SHLQBYVecInst<v2f64>;
2307 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
2308 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
2311 defm SHLQBY: ShiftLeftQuadBytes;
2313 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2314 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
2315 RotateShift, pattern>;
2317 class SHLQBYIVecInst<ValueType vectype>:
2318 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2319 [(set (vectype VECREG:$rT),
2320 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2322 multiclass ShiftLeftQuadBytesImm
2324 def v16i8: SHLQBYIVecInst<v16i8>;
2325 def v8i16: SHLQBYIVecInst<v8i16>;
2326 def v4i32: SHLQBYIVecInst<v4i32>;
2327 def v4f32: SHLQBYIVecInst<v4f32>;
2328 def v2i64: SHLQBYIVecInst<v2i64>;
2329 def v2f64: SHLQBYIVecInst<v2f64>;
2330 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
2332 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
2335 defm SHLQBYI : ShiftLeftQuadBytesImm;
2337 class SHLQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2338 RRForm<0b00111001111, OOL, IOL, "shlqbybi\t$rT, $rA, $rB",
2339 RotateShift, pattern>;
2341 class SHLQBYBIVecInst<ValueType vectype>:
2342 SHLQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2343 [/* no pattern */]>;
2345 class SHLQBYBIRegInst<RegisterClass rclass>:
2346 SHLQBYBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2347 [/* no pattern */]>;
2349 multiclass ShiftLeftQuadBytesBitCount
2351 def v16i8: SHLQBYBIVecInst<v16i8>;
2352 def v8i16: SHLQBYBIVecInst<v8i16>;
2353 def v4i32: SHLQBYBIVecInst<v4i32>;
2354 def v4f32: SHLQBYBIVecInst<v4f32>;
2355 def v2i64: SHLQBYBIVecInst<v2i64>;
2356 def v2f64: SHLQBYBIVecInst<v2f64>;
2358 def r128: SHLQBYBIRegInst<GPRC>;
2361 defm SHLQBYBI : ShiftLeftQuadBytesBitCount;
2363 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2365 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2366 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
2367 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
2368 RotateShift, pattern>;
2370 class ROTHVecInst<ValueType vectype>:
2371 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2372 [(set (vectype VECREG:$rT),
2373 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
2375 class ROTHRegInst<RegisterClass rclass>:
2376 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2377 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
2379 multiclass RotateLeftHalfword
2381 def v8i16: ROTHVecInst<v8i16>;
2382 def r16: ROTHRegInst<R16C>;
2385 defm ROTH: RotateLeftHalfword;
2387 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2388 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2390 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2391 // Rotate halfword, immediate:
2392 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2393 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
2394 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
2395 RotateShift, pattern>;
2397 class ROTHIVecInst<ValueType vectype>:
2398 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2399 [(set (vectype VECREG:$rT),
2400 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
2402 multiclass RotateLeftHalfwordImm
2404 def v8i16: ROTHIVecInst<v8i16>;
2405 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2406 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2407 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2408 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2411 defm ROTHI: RotateLeftHalfwordImm;
2413 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
2414 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2416 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2418 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2420 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
2421 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
2422 RotateShift, pattern>;
2424 class ROTVecInst<ValueType vectype>:
2425 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2426 [(set (vectype VECREG:$rT),
2427 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
2429 class ROTRegInst<RegisterClass rclass>:
2430 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2432 (rotl rclass:$rA, R32C:$rB))]>;
2434 multiclass RotateLeftWord
2436 def v4i32: ROTVecInst<v4i32>;
2437 def r32: ROTRegInst<R32C>;
2440 defm ROT: RotateLeftWord;
2442 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2444 def ROTr32_r16_anyext:
2445 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2446 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2448 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
2449 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2451 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
2452 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2454 def ROTr32_r8_anyext:
2455 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2456 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2458 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
2459 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2461 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
2462 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2464 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2465 // Rotate word, immediate
2466 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2468 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
2469 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
2470 RotateShift, pattern>;
2472 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
2473 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2474 [(set (vectype VECREG:$rT),
2475 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2477 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2478 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2479 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2481 multiclass RotateLeftWordImm
2483 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2484 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
2485 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
2487 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
2488 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
2489 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
2492 defm ROTI : RotateLeftWordImm;
2494 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2495 // Rotate quad by byte (count)
2496 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2498 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2499 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2500 RotateShift, pattern>;
2502 class ROTQBYVecInst<ValueType vectype>:
2503 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2504 [(set (vectype VECREG:$rT),
2505 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2507 multiclass RotateQuadLeftByBytes
2509 def v16i8: ROTQBYVecInst<v16i8>;
2510 def v8i16: ROTQBYVecInst<v8i16>;
2511 def v4i32: ROTQBYVecInst<v4i32>;
2512 def v4f32: ROTQBYVecInst<v4f32>;
2513 def v2i64: ROTQBYVecInst<v2i64>;
2514 def v2f64: ROTQBYVecInst<v2f64>;
2517 defm ROTQBY: RotateQuadLeftByBytes;
2519 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2520 // Rotate quad by byte (count), immediate
2521 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2523 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2524 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2525 RotateShift, pattern>;
2527 class ROTQBYIVecInst<ValueType vectype>:
2528 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2529 [(set (vectype VECREG:$rT),
2530 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2532 multiclass RotateQuadByBytesImm
2534 def v16i8: ROTQBYIVecInst<v16i8>;
2535 def v8i16: ROTQBYIVecInst<v8i16>;
2536 def v4i32: ROTQBYIVecInst<v4i32>;
2537 def v4f32: ROTQBYIVecInst<v4f32>;
2538 def v2i64: ROTQBYIVecInst<v2i64>;
2539 def vfi64: ROTQBYIVecInst<v2f64>;
2542 defm ROTQBYI: RotateQuadByBytesImm;
2544 // See ROTQBY note above.
2545 class ROTQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2546 RI7Form<0b00110011100, OOL, IOL,
2547 "rotqbybi\t$rT, $rA, $shift",
2548 RotateShift, pattern>;
2550 class ROTQBYBIVecInst<ValueType vectype, RegisterClass rclass>:
2551 ROTQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, rclass:$shift),
2552 [(set (vectype VECREG:$rT),
2553 (SPUrotbytes_left_bits (vectype VECREG:$rA), rclass:$shift))]>;
2555 multiclass RotateQuadByBytesByBitshift {
2556 def v16i8_r32: ROTQBYBIVecInst<v16i8, R32C>;
2557 def v8i16_r32: ROTQBYBIVecInst<v8i16, R32C>;
2558 def v4i32_r32: ROTQBYBIVecInst<v4i32, R32C>;
2559 def v2i64_r32: ROTQBYBIVecInst<v2i64, R32C>;
2562 defm ROTQBYBI : RotateQuadByBytesByBitshift;
2564 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2565 // See ROTQBY note above.
2567 // Assume that the user of this instruction knows to shift the rotate count
2569 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2571 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2572 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2573 RotateShift, pattern>;
2575 class ROTQBIVecInst<ValueType vectype>:
2576 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2577 [/* no pattern yet */]>;
2579 class ROTQBIRegInst<RegisterClass rclass>:
2580 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2581 [/* no pattern yet */]>;
2583 multiclass RotateQuadByBitCount
2585 def v16i8: ROTQBIVecInst<v16i8>;
2586 def v8i16: ROTQBIVecInst<v8i16>;
2587 def v4i32: ROTQBIVecInst<v4i32>;
2588 def v2i64: ROTQBIVecInst<v2i64>;
2590 def r128: ROTQBIRegInst<GPRC>;
2591 def r64: ROTQBIRegInst<R64C>;
2594 defm ROTQBI: RotateQuadByBitCount;
2596 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2597 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2598 RotateShift, pattern>;
2600 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2602 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2603 [/* no pattern yet */]>;
2605 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2607 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2608 [/* no pattern yet */]>;
2610 multiclass RotateQuadByBitCountImm
2612 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2613 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2614 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2615 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2617 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2618 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2621 defm ROTQBII : RotateQuadByBitCountImm;
2623 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2624 // ROTHM v8i16 form:
2625 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2626 // so this only matches a synthetically generated/lowered code
2628 // NOTE(2): $rB must be negated before the right rotate!
2629 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2631 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2632 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2633 RotateShift, pattern>;
2636 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2637 [/* see patterns below - $rB must be negated */]>;
2639 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2640 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2642 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2643 (ROTHMv8i16 VECREG:$rA,
2644 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2646 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2647 (ROTHMv8i16 VECREG:$rA,
2648 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2650 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2651 // Note: This instruction doesn't match a pattern because rB must be negated
2652 // for the instruction to work. Thus, the pattern below the instruction!
2655 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2656 [/* see patterns below - $rB must be negated! */]>;
2658 def : Pat<(srl R16C:$rA, R32C:$rB),
2659 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2661 def : Pat<(srl R16C:$rA, R16C:$rB),
2663 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2665 def : Pat<(srl R16C:$rA, R8C:$rB),
2667 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2669 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2670 // that the immediate can be complemented, so that the user doesn't have to
2673 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2674 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2675 RotateShift, pattern>;
2678 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2679 [/* no pattern */]>;
2681 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2682 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2684 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2685 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2687 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2688 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2691 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2692 [/* no pattern */]>;
2694 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2695 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2697 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2698 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2700 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2701 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2703 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2704 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2705 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2706 RotateShift, pattern>;
2709 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2710 [/* see patterns below - $rB must be negated */]>;
2712 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
2713 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2715 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
2716 (ROTMv4i32 VECREG:$rA,
2717 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2719 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
2720 (ROTMv4i32 VECREG:$rA,
2721 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2724 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2725 [/* see patterns below - $rB must be negated */]>;
2727 def : Pat<(srl R32C:$rA, R32C:$rB),
2728 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2730 def : Pat<(srl R32C:$rA, R16C:$rB),
2732 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2734 def : Pat<(srl R32C:$rA, R8C:$rB),
2736 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2738 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2740 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2741 "rotmi\t$rT, $rA, $val", RotateShift,
2742 [(set (v4i32 VECREG:$rT),
2743 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2745 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
2746 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2748 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
2749 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2751 // ROTMI r32 form: know how to complement the immediate value.
2753 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2754 "rotmi\t$rT, $rA, $val", RotateShift,
2755 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2757 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2758 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2760 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2761 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2763 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2764 // ROTQMBY: This is a vector form merely so that when used in an
2765 // instruction pattern, type checking will succeed. This instruction assumes
2766 // that the user knew to negate $rB.
2767 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2769 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2770 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2771 RotateShift, pattern>;
2773 class ROTQMBYVecInst<ValueType vectype>:
2774 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2775 [/* no pattern, $rB must be negated */]>;
2777 class ROTQMBYRegInst<RegisterClass rclass>:
2778 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2779 [/* no pattern */]>;
2781 multiclass RotateQuadBytes
2783 def v16i8: ROTQMBYVecInst<v16i8>;
2784 def v8i16: ROTQMBYVecInst<v8i16>;
2785 def v4i32: ROTQMBYVecInst<v4i32>;
2786 def v2i64: ROTQMBYVecInst<v2i64>;
2788 def r128: ROTQMBYRegInst<GPRC>;
2789 def r64: ROTQMBYRegInst<R64C>;
2792 defm ROTQMBY : RotateQuadBytes;
2794 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2795 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2796 RotateShift, pattern>;
2798 class ROTQMBYIVecInst<ValueType vectype>:
2799 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2800 [/* no pattern */]>;
2802 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2804 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2805 [/* no pattern */]>;
2807 // 128-bit zero extension form:
2808 class ROTQMBYIZExtInst<RegisterClass rclass, Operand optype, PatLeaf pred>:
2809 ROTQMBYIInst<(outs GPRC:$rT), (ins rclass:$rA, optype:$val),
2810 [/* no pattern */]>;
2812 multiclass RotateQuadBytesImm
2814 def v16i8: ROTQMBYIVecInst<v16i8>;
2815 def v8i16: ROTQMBYIVecInst<v8i16>;
2816 def v4i32: ROTQMBYIVecInst<v4i32>;
2817 def v2i64: ROTQMBYIVecInst<v2i64>;
2819 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2820 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2822 def r128_zext_r8: ROTQMBYIZExtInst<R8C, rotNeg7imm, uimm7>;
2823 def r128_zext_r16: ROTQMBYIZExtInst<R16C, rotNeg7imm, uimm7>;
2824 def r128_zext_r32: ROTQMBYIZExtInst<R32C, rotNeg7imm, uimm7>;
2825 def r128_zext_r64: ROTQMBYIZExtInst<R64C, rotNeg7imm, uimm7>;
2828 defm ROTQMBYI : RotateQuadBytesImm;
2830 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2831 // Rotate right and mask by bit count
2832 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2834 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2835 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2836 RotateShift, pattern>;
2838 class ROTQMBYBIVecInst<ValueType vectype>:
2839 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2840 [/* no pattern, */]>;
2842 multiclass RotateMaskQuadByBitCount
2844 def v16i8: ROTQMBYBIVecInst<v16i8>;
2845 def v8i16: ROTQMBYBIVecInst<v8i16>;
2846 def v4i32: ROTQMBYBIVecInst<v4i32>;
2847 def v2i64: ROTQMBYBIVecInst<v2i64>;
2850 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2852 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2853 // Rotate quad and mask by bits
2854 // Note that the rotate amount has to be negated
2855 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2857 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2858 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2859 RotateShift, pattern>;
2861 class ROTQMBIVecInst<ValueType vectype>:
2862 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2863 [/* no pattern */]>;
2865 class ROTQMBIRegInst<RegisterClass rclass>:
2866 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2867 [/* no pattern */]>;
2869 multiclass RotateMaskQuadByBits
2871 def v16i8: ROTQMBIVecInst<v16i8>;
2872 def v8i16: ROTQMBIVecInst<v8i16>;
2873 def v4i32: ROTQMBIVecInst<v4i32>;
2874 def v2i64: ROTQMBIVecInst<v2i64>;
2876 def r128: ROTQMBIRegInst<GPRC>;
2877 def r64: ROTQMBIRegInst<R64C>;
2880 defm ROTQMBI: RotateMaskQuadByBits;
2882 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2883 // Rotate quad and mask by bits, immediate
2884 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2886 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2887 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2888 RotateShift, pattern>;
2890 class ROTQMBIIVecInst<ValueType vectype>:
2891 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2892 [/* no pattern */]>;
2894 class ROTQMBIIRegInst<RegisterClass rclass>:
2895 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2896 [/* no pattern */]>;
2898 multiclass RotateMaskQuadByBitsImm
2900 def v16i8: ROTQMBIIVecInst<v16i8>;
2901 def v8i16: ROTQMBIIVecInst<v8i16>;
2902 def v4i32: ROTQMBIIVecInst<v4i32>;
2903 def v2i64: ROTQMBIIVecInst<v2i64>;
2905 def r128: ROTQMBIIRegInst<GPRC>;
2906 def r64: ROTQMBIIRegInst<R64C>;
2909 defm ROTQMBII: RotateMaskQuadByBitsImm;
2911 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2912 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2915 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2916 "rotmah\t$rT, $rA, $rB", RotateShift,
2917 [/* see patterns below - $rB must be negated */]>;
2919 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2920 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2922 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2923 (ROTMAHv8i16 VECREG:$rA,
2924 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2926 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2927 (ROTMAHv8i16 VECREG:$rA,
2928 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2931 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2932 "rotmah\t$rT, $rA, $rB", RotateShift,
2933 [/* see patterns below - $rB must be negated */]>;
2935 def : Pat<(sra R16C:$rA, R32C:$rB),
2936 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2938 def : Pat<(sra R16C:$rA, R16C:$rB),
2939 (ROTMAHr16 R16C:$rA,
2940 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2942 def : Pat<(sra R16C:$rA, R8C:$rB),
2943 (ROTMAHr16 R16C:$rA,
2944 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2947 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2948 "rotmahi\t$rT, $rA, $val", RotateShift,
2949 [(set (v8i16 VECREG:$rT),
2950 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2952 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2953 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2955 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2956 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2959 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2960 "rotmahi\t$rT, $rA, $val", RotateShift,
2961 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2963 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2964 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2966 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2967 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2970 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2971 "rotma\t$rT, $rA, $rB", RotateShift,
2972 [/* see patterns below - $rB must be negated */]>;
2974 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2975 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2977 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2978 (ROTMAv4i32 (v4i32 VECREG:$rA),
2979 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2981 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2982 (ROTMAv4i32 (v4i32 VECREG:$rA),
2983 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2986 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2987 "rotma\t$rT, $rA, $rB", RotateShift,
2988 [/* see patterns below - $rB must be negated */]>;
2990 def : Pat<(sra R32C:$rA, R32C:$rB),
2991 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2993 def : Pat<(sra R32C:$rA, R16C:$rB),
2995 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2997 def : Pat<(sra R32C:$rA, R8C:$rB),
2999 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
3001 class ROTMAIInst<dag OOL, dag IOL, list<dag> pattern>:
3002 RRForm<0b01011110000, OOL, IOL,
3003 "rotmai\t$rT, $rA, $val",
3004 RotateShift, pattern>;
3006 class ROTMAIVecInst<ValueType vectype, Operand intop, ValueType inttype>:
3007 ROTMAIInst<(outs VECREG:$rT), (ins VECREG:$rA, intop:$val),
3008 [(set (vectype VECREG:$rT),
3009 (SPUvec_sra VECREG:$rA, (inttype uimm7:$val)))]>;
3011 class ROTMAIRegInst<RegisterClass rclass, Operand intop, ValueType inttype>:
3012 ROTMAIInst<(outs rclass:$rT), (ins rclass:$rA, intop:$val),
3013 [(set rclass:$rT, (sra rclass:$rA, (inttype uimm7:$val)))]>;
3015 multiclass RotateMaskAlgebraicImm {
3016 def v2i64_i32 : ROTMAIVecInst<v2i64, rotNeg7imm, i32>;
3017 def v4i32_i32 : ROTMAIVecInst<v4i32, rotNeg7imm, i32>;
3018 def r64_i32 : ROTMAIRegInst<R64C, rotNeg7imm, i32>;
3019 def r32_i32 : ROTMAIRegInst<R32C, rotNeg7imm, i32>;
3022 defm ROTMAI : RotateMaskAlgebraicImm;
3024 //===----------------------------------------------------------------------===//
3025 // Branch and conditionals:
3026 //===----------------------------------------------------------------------===//
3028 let isTerminator = 1, isBarrier = 1 in {
3029 // Halt If Equal (r32 preferred slot only, no vector form)
3031 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
3032 "heq\t$rA, $rB", BranchResolv,
3033 [/* no pattern to match */]>;
3036 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
3037 "heqi\t$rA, $val", BranchResolv,
3038 [/* no pattern to match */]>;
3040 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
3041 // contrasting with HLGT/HLGTI, which use unsigned comparison:
3043 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
3044 "hgt\t$rA, $rB", BranchResolv,
3045 [/* no pattern to match */]>;
3048 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
3049 "hgti\t$rA, $val", BranchResolv,
3050 [/* no pattern to match */]>;
3053 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
3054 "hlgt\t$rA, $rB", BranchResolv,
3055 [/* no pattern to match */]>;
3058 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
3059 "hlgti\t$rA, $val", BranchResolv,
3060 [/* no pattern to match */]>;
3063 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3064 // Comparison operators for i8, i16 and i32:
3065 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3067 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
3068 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
3071 multiclass CmpEqualByte
3074 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3075 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
3076 (v8i16 VECREG:$rB)))]>;
3079 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
3080 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
3083 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
3084 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
3087 multiclass CmpEqualByteImm
3090 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3091 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
3092 v16i8SExt8Imm:$val))]>;
3094 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3095 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
3098 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
3099 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
3102 multiclass CmpEqualHalfword
3104 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3105 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
3106 (v8i16 VECREG:$rB)))]>;
3108 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3109 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
3112 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
3113 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
3116 multiclass CmpEqualHalfwordImm
3118 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3119 [(set (v8i16 VECREG:$rT),
3120 (seteq (v8i16 VECREG:$rA),
3121 (v8i16 v8i16SExt10Imm:$val)))]>;
3122 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3123 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
3126 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
3127 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
3130 multiclass CmpEqualWord
3132 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3133 [(set (v4i32 VECREG:$rT),
3134 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3136 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3137 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
3140 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
3141 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
3144 multiclass CmpEqualWordImm
3146 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3147 [(set (v4i32 VECREG:$rT),
3148 (seteq (v4i32 VECREG:$rA),
3149 (v4i32 v4i32SExt16Imm:$val)))]>;
3151 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3152 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
3155 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
3156 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
3159 multiclass CmpGtrByte
3162 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3163 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3164 (v8i16 VECREG:$rB)))]>;
3167 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
3168 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
3171 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
3172 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
3175 multiclass CmpGtrByteImm
3178 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3179 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
3180 v16i8SExt8Imm:$val))]>;
3182 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3183 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
3186 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
3187 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
3190 multiclass CmpGtrHalfword
3192 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3193 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3194 (v8i16 VECREG:$rB)))]>;
3196 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3197 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
3200 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
3201 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
3204 multiclass CmpGtrHalfwordImm
3206 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3207 [(set (v8i16 VECREG:$rT),
3208 (setgt (v8i16 VECREG:$rA),
3209 (v8i16 v8i16SExt10Imm:$val)))]>;
3210 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3211 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
3214 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
3215 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
3218 multiclass CmpGtrWord
3220 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3221 [(set (v4i32 VECREG:$rT),
3222 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3224 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3225 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
3228 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
3229 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
3232 multiclass CmpGtrWordImm
3234 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3235 [(set (v4i32 VECREG:$rT),
3236 (setgt (v4i32 VECREG:$rA),
3237 (v4i32 v4i32SExt16Imm:$val)))]>;
3239 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3240 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
3242 // CGTIv4f32, CGTIf32: These are used in the f32 fdiv instruction sequence:
3243 def v4f32: CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3244 [(set (v4i32 VECREG:$rT),
3245 (setgt (v4i32 (bitconvert (v4f32 VECREG:$rA))),
3246 (v4i32 v4i32SExt16Imm:$val)))]>;
3248 def f32: CGTIInst<(outs R32C:$rT), (ins R32FP:$rA, s10imm_i32:$val),
3249 [/* no pattern */]>;
3252 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
3253 RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB",
3256 multiclass CmpLGtrByte
3259 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3260 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3261 (v8i16 VECREG:$rB)))]>;
3264 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
3265 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
3268 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
3269 RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val",
3272 multiclass CmpLGtrByteImm
3275 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3276 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
3277 v16i8SExt8Imm:$val))]>;
3279 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3280 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
3283 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
3284 RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB",
3287 multiclass CmpLGtrHalfword
3289 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3290 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3291 (v8i16 VECREG:$rB)))]>;
3293 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3294 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
3297 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
3298 RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val",
3301 multiclass CmpLGtrHalfwordImm
3303 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3304 [(set (v8i16 VECREG:$rT),
3305 (setugt (v8i16 VECREG:$rA),
3306 (v8i16 v8i16SExt10Imm:$val)))]>;
3307 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3308 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
3311 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
3312 RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB",
3315 multiclass CmpLGtrWord
3317 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3318 [(set (v4i32 VECREG:$rT),
3319 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3321 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3322 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
3325 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
3326 RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val",
3329 multiclass CmpLGtrWordImm
3331 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3332 [(set (v4i32 VECREG:$rT),
3333 (setugt (v4i32 VECREG:$rA),
3334 (v4i32 v4i32SExt16Imm:$val)))]>;
3336 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3337 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
3340 defm CEQB : CmpEqualByte;
3341 defm CEQBI : CmpEqualByteImm;
3342 defm CEQH : CmpEqualHalfword;
3343 defm CEQHI : CmpEqualHalfwordImm;
3344 defm CEQ : CmpEqualWord;
3345 defm CEQI : CmpEqualWordImm;
3346 defm CGTB : CmpGtrByte;
3347 defm CGTBI : CmpGtrByteImm;
3348 defm CGTH : CmpGtrHalfword;
3349 defm CGTHI : CmpGtrHalfwordImm;
3350 defm CGT : CmpGtrWord;
3351 defm CGTI : CmpGtrWordImm;
3352 defm CLGTB : CmpLGtrByte;
3353 defm CLGTBI : CmpLGtrByteImm;
3354 defm CLGTH : CmpLGtrHalfword;
3355 defm CLGTHI : CmpLGtrHalfwordImm;
3356 defm CLGT : CmpLGtrWord;
3357 defm CLGTI : CmpLGtrWordImm;
3359 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3360 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
3361 // define a pattern to generate the right code, as a binary operator
3362 // (in a manner of speaking.)
3365 // 1. This only matches the setcc set of conditionals. Special pattern
3366 // matching is used for select conditionals.
3368 // 2. The "DAG" versions of these classes is almost exclusively used for
3369 // i64 comparisons. See the tblgen fundamentals documentation for what
3370 // ".ResultInstrs[0]" means; see TargetSelectionDAG.td and the Pattern
3371 // class for where ResultInstrs originates.
3372 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3374 class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3375 SPUInstr xorinst, SPUInstr cmpare>:
3376 Pat<(cond rclass:$rA, rclass:$rB),
3377 (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
3379 class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3380 PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
3381 Pat<(cond rclass:$rA, (inttype immpred:$imm)),
3382 (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
3384 def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
3385 def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
3387 def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
3388 def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
3390 def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
3391 def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
3393 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
3394 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3395 Pat<(cond rclass:$rA, rclass:$rB),
3396 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3397 (cmpOp2 rclass:$rA, rclass:$rB))>;
3399 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3401 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3402 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
3403 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
3404 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
3406 def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
3407 def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
3408 def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
3409 def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
3410 def : Pat<(setle R8C:$rA, R8C:$rB),
3411 (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3412 def : Pat<(setle R8C:$rA, immU8:$imm),
3413 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3415 def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
3416 def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
3417 ORr16, CGTHIr16, CEQHIr16>;
3418 def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
3419 def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
3420 def : Pat<(setle R16C:$rA, R16C:$rB),
3421 (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3422 def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
3423 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3425 def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
3426 def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
3427 ORr32, CGTIr32, CEQIr32>;
3428 def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
3429 def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
3430 def : Pat<(setle R32C:$rA, R32C:$rB),
3431 (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3432 def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
3433 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3435 def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
3436 def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
3437 def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
3438 def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
3439 def : Pat<(setule R8C:$rA, R8C:$rB),
3440 (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3441 def : Pat<(setule R8C:$rA, immU8:$imm),
3442 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3444 def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
3445 def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
3446 ORr16, CLGTHIr16, CEQHIr16>;
3447 def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
3448 def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
3449 CLGTHIr16, CEQHIr16>;
3450 def : Pat<(setule R16C:$rA, R16C:$rB),
3451 (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3452 def : Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
3453 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3455 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
3456 def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
3457 ORr32, CLGTIr32, CEQIr32>;
3458 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
3459 def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
3460 def : Pat<(setule R32C:$rA, R32C:$rB),
3461 (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3462 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
3463 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3465 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3466 // select conditional patterns:
3467 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3469 class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3470 SPUInstr selinstr, SPUInstr cmpare>:
3471 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3472 rclass:$rTrue, rclass:$rFalse),
3473 (selinstr rclass:$rTrue, rclass:$rFalse,
3474 (cmpare rclass:$rA, rclass:$rB))>;
3476 class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3477 PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
3478 Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
3479 rclass:$rTrue, rclass:$rFalse),
3480 (selinstr rclass:$rTrue, rclass:$rFalse,
3481 (cmpare rclass:$rA, immpred:$imm))>;
3483 def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
3484 def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
3485 def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
3486 def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
3487 def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
3488 def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
3490 def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
3491 def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
3492 def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
3493 def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
3494 def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
3495 def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
3497 def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
3498 def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
3499 def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
3500 def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
3501 def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
3502 def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
3504 class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3505 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3507 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3508 rclass:$rTrue, rclass:$rFalse),
3509 (selinstr rclass:$rFalse, rclass:$rTrue,
3510 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3511 (cmpOp2 rclass:$rA, rclass:$rB)))>;
3513 class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3515 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3517 Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
3518 rclass:$rTrue, rclass:$rFalse),
3519 (selinstr rclass:$rFalse, rclass:$rTrue,
3520 (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
3521 (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
3523 def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
3524 def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
3525 SELBr8, ORr8, CGTBIr8, CEQBIr8>;
3527 def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
3528 def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
3529 SELBr16, ORr16, CGTHIr16, CEQHIr16>;
3531 def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
3532 def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
3533 SELBr32, ORr32, CGTIr32, CEQIr32>;
3535 def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
3536 def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
3537 SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
3539 def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
3540 def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
3541 SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
3543 def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
3544 def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
3545 SELBr32, ORr32, CLGTIr32, CEQIr32>;
3547 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3550 // All calls clobber the non-callee-saved registers:
3551 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
3552 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
3553 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
3554 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
3555 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
3556 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
3557 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
3558 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
3559 // All of these instructions use $lr (aka $0)
3561 // Branch relative and set link: Used if we actually know that the target
3562 // is within [-32768, 32767] bytes of the target
3564 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
3565 "brsl\t$$lr, $func",
3566 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
3568 // Branch absolute and set link: Used if we actually know that the target
3569 // is an absolute address
3571 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
3572 "brasl\t$$lr, $func",
3573 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
3575 // Branch indirect and set link if external data. These instructions are not
3576 // actually generated, matched by an intrinsic:
3577 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
3578 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
3579 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
3580 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
3582 // Branch indirect and set link. This is the "X-form" address version of a
3585 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
3588 // Support calls to external symbols:
3589 def : Pat<(SPUcall (SPUpcrel texternalsym:$func, 0)),
3590 (BRSL texternalsym:$func)>;
3592 def : Pat<(SPUcall (SPUaform texternalsym:$func, 0)),
3593 (BRASL texternalsym:$func)>;
3595 // Unconditional branches:
3596 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
3597 let isBarrier = 1 in {
3599 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3603 // Unconditional, absolute address branch
3605 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3607 [/* no pattern */]>;
3611 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3614 // Conditional branches:
3615 class BRNZInst<dag IOL, list<dag> pattern>:
3616 RI16Form<0b010000100, (outs), IOL, "brnz\t$rCond,$dest",
3617 BranchResolv, pattern>;
3619 class BRNZRegInst<RegisterClass rclass>:
3620 BRNZInst<(ins rclass:$rCond, brtarget:$dest),
3621 [(brcond rclass:$rCond, bb:$dest)]>;
3623 class BRNZVecInst<ValueType vectype>:
3624 BRNZInst<(ins VECREG:$rCond, brtarget:$dest),
3625 [(brcond (vectype VECREG:$rCond), bb:$dest)]>;
3627 multiclass BranchNotZero {
3628 def v4i32 : BRNZVecInst<v4i32>;
3629 def r32 : BRNZRegInst<R32C>;
3632 defm BRNZ : BranchNotZero;
3634 class BRZInst<dag IOL, list<dag> pattern>:
3635 RI16Form<0b000000100, (outs), IOL, "brz\t$rT,$dest",
3636 BranchResolv, pattern>;
3638 class BRZRegInst<RegisterClass rclass>:
3639 BRZInst<(ins rclass:$rT, brtarget:$dest), [/* no pattern */]>;
3641 class BRZVecInst<ValueType vectype>:
3642 BRZInst<(ins VECREG:$rT, brtarget:$dest), [/* no pattern */]>;
3644 multiclass BranchZero {
3645 def v4i32: BRZVecInst<v4i32>;
3646 def r32: BRZRegInst<R32C>;
3649 defm BRZ: BranchZero;
3651 // Note: LLVM doesn't do branch conditional, indirect. Otherwise these would
3654 class BINZInst<dag IOL, list<dag> pattern>:
3655 BICondForm<0b10010100100, (outs), IOL, "binz\t$rA, $dest", pattern>;
3657 class BINZRegInst<RegisterClass rclass>:
3658 BINZInst<(ins rclass:$rA, brtarget:$dest),
3659 [(brcond rclass:$rA, R32C:$dest)]>;
3661 class BINZVecInst<ValueType vectype>:
3662 BINZInst<(ins VECREG:$rA, R32C:$dest),
3663 [(brcond (vectype VECREG:$rA), R32C:$dest)]>;
3665 multiclass BranchNotZeroIndirect {
3666 def v4i32: BINZVecInst<v4i32>;
3667 def r32: BINZRegInst<R32C>;
3670 defm BINZ: BranchNotZeroIndirect;
3672 class BIZInst<dag IOL, list<dag> pattern>:
3673 BICondForm<0b00010100100, (outs), IOL, "biz\t$rA, $func", pattern>;
3675 class BIZRegInst<RegisterClass rclass>:
3676 BIZInst<(ins rclass:$rA, R32C:$func), [/* no pattern */]>;
3678 class BIZVecInst<ValueType vectype>:
3679 BIZInst<(ins VECREG:$rA, R32C:$func), [/* no pattern */]>;
3681 multiclass BranchZeroIndirect {
3682 def v4i32: BIZVecInst<v4i32>;
3683 def r32: BIZRegInst<R32C>;
3686 defm BIZ: BranchZeroIndirect;
3689 class BRHNZInst<dag IOL, list<dag> pattern>:
3690 RI16Form<0b011000100, (outs), IOL, "brhnz\t$rCond,$dest", BranchResolv,
3693 class BRHNZRegInst<RegisterClass rclass>:
3694 BRHNZInst<(ins rclass:$rCond, brtarget:$dest),
3695 [(brcond rclass:$rCond, bb:$dest)]>;
3697 class BRHNZVecInst<ValueType vectype>:
3698 BRHNZInst<(ins VECREG:$rCond, brtarget:$dest), [/* no pattern */]>;
3700 multiclass BranchNotZeroHalfword {
3701 def v8i16: BRHNZVecInst<v8i16>;
3702 def r16: BRHNZRegInst<R16C>;
3705 defm BRHNZ: BranchNotZeroHalfword;
3707 class BRHZInst<dag IOL, list<dag> pattern>:
3708 RI16Form<0b001000100, (outs), IOL, "brhz\t$rT,$dest", BranchResolv,
3711 class BRHZRegInst<RegisterClass rclass>:
3712 BRHZInst<(ins rclass:$rT, brtarget:$dest), [/* no pattern */]>;
3714 class BRHZVecInst<ValueType vectype>:
3715 BRHZInst<(ins VECREG:$rT, brtarget:$dest), [/* no pattern */]>;
3717 multiclass BranchZeroHalfword {
3718 def v8i16: BRHZVecInst<v8i16>;
3719 def r16: BRHZRegInst<R16C>;
3722 defm BRHZ: BranchZeroHalfword;
3725 //===----------------------------------------------------------------------===//
3726 // setcc and brcond patterns:
3727 //===----------------------------------------------------------------------===//
3729 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3730 (BRHZr16 R16C:$rA, bb:$dest)>;
3731 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3732 (BRHNZr16 R16C:$rA, bb:$dest)>;
3734 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3735 (BRZr32 R32C:$rA, bb:$dest)>;
3736 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3737 (BRNZr32 R32C:$rA, bb:$dest)>;
3739 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3741 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3742 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3744 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3745 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3747 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3748 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3750 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3751 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3754 defm BRCONDeq : BranchCondEQ<seteq, BRHNZr16, BRNZr32>;
3755 defm BRCONDne : BranchCondEQ<setne, BRHZr16, BRZr32>;
3757 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3759 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3760 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3762 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3763 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3765 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3766 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3768 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3769 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3772 defm BRCONDugt : BranchCondLGT<setugt, BRHNZr16, BRNZr32>;
3773 defm BRCONDule : BranchCondLGT<setule, BRHZr16, BRZr32>;
3775 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3776 SPUInstr orinst32, SPUInstr brinst32>
3778 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3779 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3780 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3783 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3784 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3785 (CEQHr16 R16C:$rA, R16:$rB)),
3788 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3789 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3790 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3793 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3794 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3795 (CEQr32 R32C:$rA, R32C:$rB)),
3799 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZr16, ORr32, BRNZr32>;
3800 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZr16, ORr32, BRZr32>;
3802 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3804 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3805 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3807 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3808 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3810 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3811 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3813 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3814 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3817 defm BRCONDgt : BranchCondGT<setgt, BRHNZr16, BRNZr32>;
3818 defm BRCONDle : BranchCondGT<setle, BRHZr16, BRZr32>;
3820 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3821 SPUInstr orinst32, SPUInstr brinst32>
3823 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3824 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3825 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3828 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3829 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3830 (CEQHr16 R16C:$rA, R16:$rB)),
3833 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3834 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3835 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3838 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3839 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3840 (CEQr32 R32C:$rA, R32C:$rB)),
3844 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZr16, ORr32, BRNZr32>;
3845 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZr16, ORr32, BRZr32>;
3847 let isTerminator = 1, isBarrier = 1 in {
3848 let isReturn = 1 in {
3850 RETForm<"bi\t$$lr", [(retflag)]>;
3854 //===----------------------------------------------------------------------===//
3855 // Single precision floating point instructions
3856 //===----------------------------------------------------------------------===//
3858 class FAInst<dag OOL, dag IOL, list<dag> pattern>:
3859 RRForm<0b01011000100, OOL, IOL, "fa\t$rT, $rA, $rB",
3862 class FAVecInst<ValueType vectype>:
3863 FAInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3864 [(set (vectype VECREG:$rT),
3865 (fadd (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
3869 def v4f32: FAVecInst<v4f32>;
3870 def f32: FAInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3871 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3876 class FSInst<dag OOL, dag IOL, list<dag> pattern>:
3877 RRForm<0b01011000100, OOL, IOL, "fs\t$rT, $rA, $rB",
3880 class FSVecInst<ValueType vectype>:
3881 FSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3882 [(set (vectype VECREG:$rT),
3883 (fsub (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
3887 def v4f32: FSVecInst<v4f32>;
3888 def f32: FSInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3889 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3894 // Floating point reciprocal estimate
3896 class FRESTInst<dag OOL, dag IOL>:
3897 RRForm_1<0b00110111000, OOL, IOL,
3898 "frest\t$rT, $rA", SPrecFP,
3899 [/* no pattern */]>;
3902 FRESTInst<(outs VECREG:$rT), (ins VECREG:$rA)>;
3905 FRESTInst<(outs R32FP:$rT), (ins R32FP:$rA)>;
3907 // Floating point interpolate (used in conjunction with reciprocal estimate)
3909 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3910 "fi\t$rT, $rA, $rB", SPrecFP,
3911 [/* no pattern */]>;
3914 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3915 "fi\t$rT, $rA, $rB", SPrecFP,
3916 [/* no pattern */]>;
3918 //--------------------------------------------------------------------------
3919 // Basic single precision floating point comparisons:
3921 // Note: There is no support on SPU for single precision NaN. Consequently,
3922 // ordered and unordered comparisons are the same.
3923 //--------------------------------------------------------------------------
3926 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3927 "fceq\t$rT, $rA, $rB", SPrecFP,
3928 [(set R32C:$rT, (setueq R32FP:$rA, R32FP:$rB))]>;
3930 def : Pat<(setoeq R32FP:$rA, R32FP:$rB),
3931 (FCEQf32 R32FP:$rA, R32FP:$rB)>;
3934 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3935 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3936 [(set R32C:$rT, (setueq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3938 def : Pat<(setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)),
3939 (FCMEQf32 R32FP:$rA, R32FP:$rB)>;
3942 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3943 "fcgt\t$rT, $rA, $rB", SPrecFP,
3944 [(set R32C:$rT, (setugt R32FP:$rA, R32FP:$rB))]>;
3946 def : Pat<(setugt R32FP:$rA, R32FP:$rB),
3947 (FCGTf32 R32FP:$rA, R32FP:$rB)>;
3950 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3951 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3952 [(set R32C:$rT, (setugt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3954 def : Pat<(setugt (fabs R32FP:$rA), (fabs R32FP:$rB)),
3955 (FCMGTf32 R32FP:$rA, R32FP:$rB)>;
3957 //--------------------------------------------------------------------------
3958 // Single precision floating point comparisons and SETCC equivalents:
3959 //--------------------------------------------------------------------------
3961 def : SETCCNegCondReg<setune, R32FP, i32, XORIr32, FCEQf32>;
3962 def : SETCCNegCondReg<setone, R32FP, i32, XORIr32, FCEQf32>;
3964 def : SETCCBinOpReg<setuge, R32FP, ORr32, FCGTf32, FCEQf32>;
3965 def : SETCCBinOpReg<setoge, R32FP, ORr32, FCGTf32, FCEQf32>;
3967 def : SETCCBinOpReg<setult, R32FP, NORr32, FCGTf32, FCEQf32>;
3968 def : SETCCBinOpReg<setolt, R32FP, NORr32, FCGTf32, FCEQf32>;
3970 def : Pat<(setule R32FP:$rA, R32FP:$rB),
3971 (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
3972 def : Pat<(setole R32FP:$rA, R32FP:$rB),
3973 (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
3975 // FP Status and Control Register Write
3976 // Why isn't rT a don't care in the ISA?
3977 // Should we create a special RRForm_3 for this guy and zero out the rT?
3979 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3980 "fscrwr\t$rA", SPrecFP,
3981 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3983 // FP Status and Control Register Read
3985 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3986 "fscrrd\t$rT", SPrecFP,
3987 [/* This instruction requires an intrinsic */]>;
3989 // llvm instruction space
3990 // How do these map onto cell instructions?
3992 // frest rC rB # c = 1/b (both lines)
3994 // fm rD rA rC # d = a * 1/b
3995 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3996 // fma rB rB rC rD # b = b * c + d
3997 // = -(d *b -a) * c + d
3998 // = a * c - c ( a *b *c - a)
4003 // These llvm instructions will actually map to library calls.
4004 // All that's needed, then, is to check that the appropriate library is
4005 // imported and do a brsl to the proper function name.
4006 // frem # fmod(x, y): x - (x/y) * y
4007 // (Note: fmod(double, double), fmodf(float,float)
4011 // Unimplemented SPU instruction space
4012 // floating reciprocal absolute square root estimate (frsqest)
4014 // The following are probably just intrinsics
4015 // status and control register write
4016 // status and control register read
4018 //--------------------------------------
4019 // Floating point multiply instructions
4020 //--------------------------------------
4023 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
4024 "fm\t$rT, $rA, $rB", SPrecFP,
4025 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
4026 (v4f32 VECREG:$rB)))]>;
4029 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
4030 "fm\t$rT, $rA, $rB", SPrecFP,
4031 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
4033 // Floating point multiply and add
4034 // e.g. d = c + (a * b)
4036 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4037 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
4038 [(set (v4f32 VECREG:$rT),
4039 (fadd (v4f32 VECREG:$rC),
4040 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
4043 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
4044 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
4045 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
4047 // FP multiply and subtract
4048 // Subtracts value in rC from product
4051 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4052 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
4053 [(set (v4f32 VECREG:$rT),
4054 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
4055 (v4f32 VECREG:$rC)))]>;
4058 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
4059 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
4061 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
4063 // Floating Negative Mulitply and Subtract
4064 // Subtracts product from value in rC
4065 // res = fneg(fms a b c)
4068 // NOTE: subtraction order
4072 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
4073 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
4074 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
4077 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4078 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
4079 [(set (v4f32 VECREG:$rT),
4080 (fsub (v4f32 VECREG:$rC),
4081 (fmul (v4f32 VECREG:$rA),
4082 (v4f32 VECREG:$rB))))]>;
4084 //--------------------------------------
4085 // Floating Point Conversions
4086 // Signed conversions:
4088 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
4089 "csflt\t$rT, $rA, 0", SPrecFP,
4090 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
4092 // Convert signed integer to floating point
4094 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
4095 "csflt\t$rT, $rA, 0", SPrecFP,
4096 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
4098 // Convert unsigned into to float
4100 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
4101 "cuflt\t$rT, $rA, 0", SPrecFP,
4102 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
4105 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
4106 "cuflt\t$rT, $rA, 0", SPrecFP,
4107 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
4109 // Convert float to unsigned int
4110 // Assume that scale = 0
4113 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
4114 "cfltu\t$rT, $rA, 0", SPrecFP,
4115 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
4118 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
4119 "cfltu\t$rT, $rA, 0", SPrecFP,
4120 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
4122 // Convert float to signed int
4123 // Assume that scale = 0
4126 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
4127 "cflts\t$rT, $rA, 0", SPrecFP,
4128 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
4131 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
4132 "cflts\t$rT, $rA, 0", SPrecFP,
4133 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
4135 //===----------------------------------------------------------------------==//
4136 // Single<->Double precision conversions
4137 //===----------------------------------------------------------------------==//
4139 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
4140 // v4f32, output is v2f64--which goes in the name?)
4142 // Floating point extend single to double
4143 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
4144 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
4147 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
4148 "fesd\t$rT, $rA", SPrecFP,
4149 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
4152 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
4153 "fesd\t$rT, $rA", SPrecFP,
4154 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
4156 // Floating point round double to single
4158 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
4159 // "frds\t$rT, $rA,", SPrecFP,
4160 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
4163 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
4164 "frds\t$rT, $rA", SPrecFP,
4165 [(set R32FP:$rT, (fround R64FP:$rA))]>;
4167 //ToDo include anyextend?
4169 //===----------------------------------------------------------------------==//
4170 // Double precision floating point instructions
4171 //===----------------------------------------------------------------------==//
4173 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
4174 "dfa\t$rT, $rA, $rB", DPrecFP,
4175 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
4178 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
4179 "dfa\t$rT, $rA, $rB", DPrecFP,
4180 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
4183 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
4184 "dfs\t$rT, $rA, $rB", DPrecFP,
4185 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
4188 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
4189 "dfs\t$rT, $rA, $rB", DPrecFP,
4190 [(set (v2f64 VECREG:$rT),
4191 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
4194 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
4195 "dfm\t$rT, $rA, $rB", DPrecFP,
4196 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
4199 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
4200 "dfm\t$rT, $rA, $rB", DPrecFP,
4201 [(set (v2f64 VECREG:$rT),
4202 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
4205 RRForm<0b00111010110, (outs R64FP:$rT),
4206 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
4207 "dfma\t$rT, $rA, $rB", DPrecFP,
4208 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
4209 RegConstraint<"$rC = $rT">,
4213 RRForm<0b00111010110, (outs VECREG:$rT),
4214 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4215 "dfma\t$rT, $rA, $rB", DPrecFP,
4216 [(set (v2f64 VECREG:$rT),
4217 (fadd (v2f64 VECREG:$rC),
4218 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
4219 RegConstraint<"$rC = $rT">,
4223 RRForm<0b10111010110, (outs R64FP:$rT),
4224 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
4225 "dfms\t$rT, $rA, $rB", DPrecFP,
4226 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
4227 RegConstraint<"$rC = $rT">,
4231 RRForm<0b10111010110, (outs VECREG:$rT),
4232 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4233 "dfms\t$rT, $rA, $rB", DPrecFP,
4234 [(set (v2f64 VECREG:$rT),
4235 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
4236 (v2f64 VECREG:$rC)))]>;
4238 // DFNMS: - (a * b - c)
4239 // - (a * b) + c => c - (a * b)
4241 class DFNMSInst<dag OOL, dag IOL, list<dag> pattern>:
4242 RRForm<0b01111010110, OOL, IOL, "dfnms\t$rT, $rA, $rB",
4244 RegConstraint<"$rC = $rT">,
4247 class DFNMSVecInst<list<dag> pattern>:
4248 DFNMSInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4251 class DFNMSRegInst<list<dag> pattern>:
4252 DFNMSInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
4255 multiclass DFMultiplySubtract
4257 def v2f64 : DFNMSVecInst<[(set (v2f64 VECREG:$rT),
4258 (fsub (v2f64 VECREG:$rC),
4259 (fmul (v2f64 VECREG:$rA),
4260 (v2f64 VECREG:$rB))))]>;
4262 def f64 : DFNMSRegInst<[(set R64FP:$rT,
4264 (fmul R64FP:$rA, R64FP:$rB)))]>;
4267 defm DFNMS : DFMultiplySubtract;
4272 RRForm<0b11111010110, (outs R64FP:$rT),
4273 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
4274 "dfnma\t$rT, $rA, $rB", DPrecFP,
4275 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
4276 RegConstraint<"$rC = $rT">,
4280 RRForm<0b11111010110, (outs VECREG:$rT),
4281 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
4282 "dfnma\t$rT, $rA, $rB", DPrecFP,
4283 [(set (v2f64 VECREG:$rT),
4284 (fneg (fadd (v2f64 VECREG:$rC),
4285 (fmul (v2f64 VECREG:$rA),
4286 (v2f64 VECREG:$rB)))))]>,
4287 RegConstraint<"$rC = $rT">,
4290 //===----------------------------------------------------------------------==//
4291 // Floating point negation and absolute value
4292 //===----------------------------------------------------------------------==//
4294 def : Pat<(fneg (v4f32 VECREG:$rA)),
4295 (XORfnegvec (v4f32 VECREG:$rA),
4296 (v4f32 (ILHUv4i32 0x8000)))>;
4298 def : Pat<(fneg R32FP:$rA),
4299 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
4301 // Floating point absolute value
4302 // Note: f64 fabs is custom-selected.
4304 def : Pat<(fabs R32FP:$rA),
4305 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
4307 def : Pat<(fabs (v4f32 VECREG:$rA)),
4308 (ANDfabsvec (v4f32 VECREG:$rA),
4309 (IOHLv4i32 (ILHUv4i32 0x7fff), 0xffff))>;
4311 //===----------------------------------------------------------------------===//
4312 // Hint for branch instructions:
4313 //===----------------------------------------------------------------------===//
4315 /* def HBR : SPUInstr<(outs), (ins), "hbr\t" */
4317 //===----------------------------------------------------------------------===//
4318 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
4319 // in the odd pipeline)
4320 //===----------------------------------------------------------------------===//
4322 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
4325 let Inst{0-10} = 0b10000000010;
4326 let Inst{11-17} = 0;
4327 let Inst{18-24} = 0;
4328 let Inst{25-31} = 0;
4331 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
4334 let Inst{0-10} = 0b10000000000;
4335 let Inst{11-17} = 0;
4336 let Inst{18-24} = 0;
4337 let Inst{25-31} = 0;
4340 //===----------------------------------------------------------------------===//
4341 // Bit conversions (type conversions between vector/packed types)
4342 // NOTE: Promotions are handled using the XS* instructions.
4343 //===----------------------------------------------------------------------===//
4344 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
4345 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
4346 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
4347 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
4348 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
4350 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
4351 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
4352 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
4353 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
4354 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
4356 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
4357 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
4358 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
4359 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
4360 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
4362 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
4363 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
4364 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
4365 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
4366 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
4368 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
4369 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
4370 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
4371 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
4372 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
4374 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
4375 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
4376 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
4377 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
4378 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
4380 def : Pat<(i128 (bitconvert (v16i8 VECREG:$src))),
4381 (ORi128_vec VECREG:$src)>;
4382 def : Pat<(i128 (bitconvert (v8i16 VECREG:$src))),
4383 (ORi128_vec VECREG:$src)>;
4384 def : Pat<(i128 (bitconvert (v4i32 VECREG:$src))),
4385 (ORi128_vec VECREG:$src)>;
4386 def : Pat<(i128 (bitconvert (v2i64 VECREG:$src))),
4387 (ORi128_vec VECREG:$src)>;
4388 def : Pat<(i128 (bitconvert (v4f32 VECREG:$src))),
4389 (ORi128_vec VECREG:$src)>;
4390 def : Pat<(i128 (bitconvert (v2f64 VECREG:$src))),
4391 (ORi128_vec VECREG:$src)>;
4393 def : Pat<(v16i8 (bitconvert (i128 GPRC:$src))),
4394 (v16i8 (ORvec_i128 GPRC:$src))>;
4395 def : Pat<(v8i16 (bitconvert (i128 GPRC:$src))),
4396 (v8i16 (ORvec_i128 GPRC:$src))>;
4397 def : Pat<(v4i32 (bitconvert (i128 GPRC:$src))),
4398 (v4i32 (ORvec_i128 GPRC:$src))>;
4399 def : Pat<(v2i64 (bitconvert (i128 GPRC:$src))),
4400 (v2i64 (ORvec_i128 GPRC:$src))>;
4401 def : Pat<(v4f32 (bitconvert (i128 GPRC:$src))),
4402 (v4f32 (ORvec_i128 GPRC:$src))>;
4403 def : Pat<(v2f64 (bitconvert (i128 GPRC:$src))),
4404 (v2f64 (ORvec_i128 GPRC:$src))>;
4406 //===----------------------------------------------------------------------===//
4407 // Instruction patterns:
4408 //===----------------------------------------------------------------------===//
4410 // General 32-bit constants:
4411 def : Pat<(i32 imm:$imm),
4412 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
4414 // Single precision float constants:
4415 def : Pat<(f32 fpimm:$imm),
4416 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
4418 // General constant 32-bit vectors
4419 def : Pat<(v4i32 v4i32Imm:$imm),
4420 (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
4421 (LO16_vec v4i32Imm:$imm))>;
4424 def : Pat<(i8 imm:$imm),
4427 //===----------------------------------------------------------------------===//
4428 // Zero/Any/Sign extensions
4429 //===----------------------------------------------------------------------===//
4431 // sext 8->32: Sign extend bytes to words
4432 def : Pat<(sext_inreg R32C:$rSrc, i8),
4433 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
4435 def : Pat<(i32 (sext R8C:$rSrc)),
4436 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
4438 // sext 8->64: Sign extend bytes to double word
4439 def : Pat<(sext_inreg R64C:$rSrc, i8),
4440 (XSWDr64_inreg (XSHWr64 (XSBHr64 R64C:$rSrc)))>;
4442 def : Pat<(i64 (sext R8C:$rSrc)),
4443 (XSWDr64 (XSHWr16 (XSBHr8 R8C:$rSrc)))>;
4445 // zext 8->16: Zero extend bytes to halfwords
4446 def : Pat<(i16 (zext R8C:$rSrc)),
4447 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
4449 // zext 8->32: Zero extend bytes to words
4450 def : Pat<(i32 (zext R8C:$rSrc)),
4451 (ANDIi8i32 R8C:$rSrc, 0xff)>;
4453 // zext 8->64: Zero extend bytes to double words
4454 def : Pat<(i64 (zext R8C:$rSrc)),
4455 (ORi64_v2i64 (SELBv4i32 (ROTQMBYv4i32
4456 (ORv4i32_i32 (ANDIi8i32 R8C:$rSrc, 0xff)),
4459 (FSMBIv4i32 0x0f0f)))>;
4461 // anyext 8->16: Extend 8->16 bits, irrespective of sign, preserves high bits
4462 def : Pat<(i16 (anyext R8C:$rSrc)),
4463 (ORHIi8i16 R8C:$rSrc, 0)>;
4465 // anyext 8->32: Extend 8->32 bits, irrespective of sign, preserves high bits
4466 def : Pat<(i32 (anyext R8C:$rSrc)),
4467 (ORIi8i32 R8C:$rSrc, 0)>;
4469 // sext 16->64: Sign extend halfword to double word
4470 def : Pat<(sext_inreg R64C:$rSrc, i16),
4471 (XSWDr64_inreg (XSHWr64 R64C:$rSrc))>;
4473 def : Pat<(sext R16C:$rSrc),
4474 (XSWDr64 (XSHWr16 R16C:$rSrc))>;
4476 // zext 16->32: Zero extend halfwords to words
4477 def : Pat<(i32 (zext R16C:$rSrc)),
4478 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
4480 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
4481 (ANDIi16i32 R16C:$rSrc, 0xf)>;
4483 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
4484 (ANDIi16i32 R16C:$rSrc, 0xff)>;
4486 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
4487 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
4489 // anyext 16->32: Extend 16->32 bits, irrespective of sign
4490 def : Pat<(i32 (anyext R16C:$rSrc)),
4491 (ORIi16i32 R16C:$rSrc, 0)>;
4493 //===----------------------------------------------------------------------===//
4495 // These truncates are for the SPU's supported types (i8, i16, i32). i64 and
4496 // above are custom lowered.
4497 //===----------------------------------------------------------------------===//
4499 def : Pat<(i8 (trunc GPRC:$src)),
4501 (SHUFBgprc GPRC:$src, GPRC:$src,
4502 (IOHLv4i32 (ILHUv4i32 0x0f0f), 0x0f0f)))>;
4504 def : Pat<(i8 (trunc R64C:$src)),
4507 (ORv2i64_i64 R64C:$src),
4508 (ORv2i64_i64 R64C:$src),
4509 (IOHLv4i32 (ILHUv4i32 0x0707), 0x0707)))>;
4511 def : Pat<(i8 (trunc R32C:$src)),
4514 (ORv4i32_i32 R32C:$src),
4515 (ORv4i32_i32 R32C:$src),
4516 (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)))>;
4518 def : Pat<(i8 (trunc R16C:$src)),
4521 (ORv8i16_i16 R16C:$src),
4522 (ORv8i16_i16 R16C:$src),
4523 (IOHLv4i32 (ILHUv4i32 0x0303), 0x0303)))>;
4525 def : Pat<(i16 (trunc GPRC:$src)),
4527 (SHUFBgprc GPRC:$src, GPRC:$src,
4528 (IOHLv4i32 (ILHUv4i32 0x0e0f), 0x0e0f)))>;
4530 def : Pat<(i16 (trunc R64C:$src)),
4533 (ORv2i64_i64 R64C:$src),
4534 (ORv2i64_i64 R64C:$src),
4535 (IOHLv4i32 (ILHUv4i32 0x0607), 0x0607)))>;
4537 def : Pat<(i16 (trunc R32C:$src)),
4540 (ORv4i32_i32 R32C:$src),
4541 (ORv4i32_i32 R32C:$src),
4542 (IOHLv4i32 (ILHUv4i32 0x0203), 0x0203)))>;
4544 def : Pat<(i32 (trunc GPRC:$src)),
4546 (SHUFBgprc GPRC:$src, GPRC:$src,
4547 (IOHLv4i32 (ILHUv4i32 0x0c0d), 0x0e0f)))>;
4549 def : Pat<(i32 (trunc R64C:$src)),
4552 (ORv2i64_i64 R64C:$src),
4553 (ORv2i64_i64 R64C:$src),
4554 (IOHLv4i32 (ILHUv4i32 0x0405), 0x0607)))>;
4556 //===----------------------------------------------------------------------===//
4557 // Address generation: SPU, like PPC, has to split addresses into high and
4558 // low parts in order to load them into a register.
4559 //===----------------------------------------------------------------------===//
4561 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
4562 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
4563 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
4564 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
4566 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
4567 (SPUlo tglobaladdr:$in, 0)),
4568 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4570 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
4571 (SPUlo texternalsym:$in, 0)),
4572 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4574 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
4575 (SPUlo tjumptable:$in, 0)),
4576 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4578 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
4579 (SPUlo tconstpool:$in, 0)),
4580 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4582 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
4583 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4585 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
4586 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4588 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
4589 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4591 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
4592 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4595 include "CellSDKIntrinsics.td"
4596 // Various math operator instruction sequences
4597 include "SPUMathInstr.td"
4598 // 64-bit "instructions"/support
4599 include "SPU64InstrInfo.td"
4600 // 128-bit "instructions"/support
4601 include "SPU128InstrInfo.td"