1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm_i32:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start timm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm_i32:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end timm:$amt)]>;
33 //===----------------------------------------------------------------------===//
34 // DWARF debugging Pseudo Instructions
35 //===----------------------------------------------------------------------===//
37 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
38 "${:comment} .loc $file, $line, $col",
39 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
42 //===----------------------------------------------------------------------===//
44 // NB: The ordering is actually important, since the instruction selection
45 // will try each of the instructions in sequence, i.e., the D-form first with
46 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
47 // finally the X-form with the register-register.
48 //===----------------------------------------------------------------------===//
50 let isSimpleLoad = 1 in {
51 class LoadDFormVec<ValueType vectype>
52 : RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
55 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
58 class LoadDForm<RegisterClass rclass>
59 : RI10Form<0b00101100, (outs rclass:$rT), (ins memri10:$src),
62 [(set rclass:$rT, (load dform_addr:$src))]>
67 def v16i8: LoadDFormVec<v16i8>;
68 def v8i16: LoadDFormVec<v8i16>;
69 def v4i32: LoadDFormVec<v4i32>;
70 def v2i64: LoadDFormVec<v2i64>;
71 def v4f32: LoadDFormVec<v4f32>;
72 def v2f64: LoadDFormVec<v2f64>;
74 def r128: LoadDForm<GPRC>;
75 def r64: LoadDForm<R64C>;
76 def r32: LoadDForm<R32C>;
77 def f32: LoadDForm<R32FP>;
78 def f64: LoadDForm<R64FP>;
79 def r16: LoadDForm<R16C>;
80 def r8: LoadDForm<R8C>;
83 class LoadAFormVec<ValueType vectype>
84 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
87 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
90 class LoadAForm<RegisterClass rclass>
91 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
94 [(set rclass:$rT, (load aform_addr:$src))]>
99 def v16i8: LoadAFormVec<v16i8>;
100 def v8i16: LoadAFormVec<v8i16>;
101 def v4i32: LoadAFormVec<v4i32>;
102 def v2i64: LoadAFormVec<v2i64>;
103 def v4f32: LoadAFormVec<v4f32>;
104 def v2f64: LoadAFormVec<v2f64>;
106 def r128: LoadAForm<GPRC>;
107 def r64: LoadAForm<R64C>;
108 def r32: LoadAForm<R32C>;
109 def f32: LoadAForm<R32FP>;
110 def f64: LoadAForm<R64FP>;
111 def r16: LoadAForm<R16C>;
112 def r8: LoadAForm<R8C>;
115 class LoadXFormVec<ValueType vectype>
116 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
119 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
122 class LoadXForm<RegisterClass rclass>
123 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
126 [(set rclass:$rT, (load xform_addr:$src))]>
129 multiclass LoadXForms
131 def v16i8: LoadXFormVec<v16i8>;
132 def v8i16: LoadXFormVec<v8i16>;
133 def v4i32: LoadXFormVec<v4i32>;
134 def v2i64: LoadXFormVec<v2i64>;
135 def v4f32: LoadXFormVec<v4f32>;
136 def v2f64: LoadXFormVec<v2f64>;
138 def r128: LoadXForm<GPRC>;
139 def r64: LoadXForm<R64C>;
140 def r32: LoadXForm<R32C>;
141 def f32: LoadXForm<R32FP>;
142 def f64: LoadXForm<R64FP>;
143 def r16: LoadXForm<R16C>;
144 def r8: LoadXForm<R8C>;
147 defm LQA : LoadAForms;
148 defm LQD : LoadDForms;
149 defm LQX : LoadXForms;
151 /* Load quadword, PC relative: Not much use at this point in time.
152 Might be of use later for relocatable code. It's effectively the
153 same as LQA, but uses PC-relative addressing.
154 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
155 "lqr\t$rT, $disp", LoadStore,
156 [(set VECREG:$rT, (load iaddr:$disp))]>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
163 class StoreDFormVec<ValueType vectype>
164 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
167 [(store (vectype VECREG:$rT), dform_addr:$src)]>
170 class StoreDForm<RegisterClass rclass>
171 : RI10Form<0b00100100, (outs), (ins rclass:$rT, memri10:$src),
174 [(store rclass:$rT, dform_addr:$src)]>
177 multiclass StoreDForms
179 def v16i8: StoreDFormVec<v16i8>;
180 def v8i16: StoreDFormVec<v8i16>;
181 def v4i32: StoreDFormVec<v4i32>;
182 def v2i64: StoreDFormVec<v2i64>;
183 def v4f32: StoreDFormVec<v4f32>;
184 def v2f64: StoreDFormVec<v2f64>;
186 def r128: StoreDForm<GPRC>;
187 def r64: StoreDForm<R64C>;
188 def r32: StoreDForm<R32C>;
189 def f32: StoreDForm<R32FP>;
190 def f64: StoreDForm<R64FP>;
191 def r16: StoreDForm<R16C>;
192 def r8: StoreDForm<R8C>;
195 class StoreAFormVec<ValueType vectype>
196 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
199 [(store (vectype VECREG:$rT), aform_addr:$src)]>;
201 class StoreAForm<RegisterClass rclass>
202 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
205 [(store rclass:$rT, aform_addr:$src)]>;
207 multiclass StoreAForms
209 def v16i8: StoreAFormVec<v16i8>;
210 def v8i16: StoreAFormVec<v8i16>;
211 def v4i32: StoreAFormVec<v4i32>;
212 def v2i64: StoreAFormVec<v2i64>;
213 def v4f32: StoreAFormVec<v4f32>;
214 def v2f64: StoreAFormVec<v2f64>;
216 def r128: StoreAForm<GPRC>;
217 def r64: StoreAForm<R64C>;
218 def r32: StoreAForm<R32C>;
219 def f32: StoreAForm<R32FP>;
220 def f64: StoreAForm<R64FP>;
221 def r16: StoreAForm<R16C>;
222 def r8: StoreAForm<R8C>;
225 class StoreXFormVec<ValueType vectype>
226 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
229 [(store (vectype VECREG:$rT), xform_addr:$src)]>
232 class StoreXForm<RegisterClass rclass>
233 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
236 [(store rclass:$rT, xform_addr:$src)]>
239 multiclass StoreXForms
241 def v16i8: StoreXFormVec<v16i8>;
242 def v8i16: StoreXFormVec<v8i16>;
243 def v4i32: StoreXFormVec<v4i32>;
244 def v2i64: StoreXFormVec<v2i64>;
245 def v4f32: StoreXFormVec<v4f32>;
246 def v2f64: StoreXFormVec<v2f64>;
248 def r128: StoreXForm<GPRC>;
249 def r64: StoreXForm<R64C>;
250 def r32: StoreXForm<R32C>;
251 def f32: StoreXForm<R32FP>;
252 def f64: StoreXForm<R64FP>;
253 def r16: StoreXForm<R16C>;
254 def r8: StoreXForm<R8C>;
257 defm STQD : StoreDForms;
258 defm STQA : StoreAForms;
259 defm STQX : StoreXForms;
261 /* Store quadword, PC relative: Not much use at this point in time. Might
262 be useful for relocatable code.
263 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
264 "stqr\t$rT, $disp", LoadStore,
265 [(store VECREG:$rT, iaddr:$disp)]>;
268 //===----------------------------------------------------------------------===//
269 // Generate Controls for Insertion:
270 //===----------------------------------------------------------------------===//
273 RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
274 "cbd\t$rT, $src", ShuffleOp,
275 [(set (v16i8 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
277 def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
278 "cbx\t$rT, $src", ShuffleOp,
279 [(set (v16i8 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
281 def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
282 "chd\t$rT, $src", ShuffleOp,
283 [(set (v8i16 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
285 def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
286 "chx\t$rT, $src", ShuffleOp,
287 [(set (v8i16 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
289 def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
290 "cwd\t$rT, $src", ShuffleOp,
291 [(set (v4i32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
293 def CWDf32 : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
294 "cwd\t$rT, $src", ShuffleOp,
295 [(set (v4f32 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
297 def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
298 "cwx\t$rT, $src", ShuffleOp,
299 [(set (v4i32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
301 def CWXf32 : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
302 "cwx\t$rT, $src", ShuffleOp,
303 [(set (v4f32 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
305 def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
306 "cdd\t$rT, $src", ShuffleOp,
307 [(set (v2i64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
309 def CDDf64 : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
310 "cdd\t$rT, $src", ShuffleOp,
311 [(set (v2f64 VECREG:$rT), (SPUshufmask dform2_addr:$src))]>;
313 def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
314 "cdx\t$rT, $src", ShuffleOp,
315 [(set (v2i64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
317 def CDXf64 : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
318 "cdx\t$rT, $src", ShuffleOp,
319 [(set (v2f64 VECREG:$rT), (SPUshufmask xform_addr:$src))]>;
321 //===----------------------------------------------------------------------===//
322 // Constant formation:
323 //===----------------------------------------------------------------------===//
326 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
327 "ilh\t$rT, $val", ImmLoad,
328 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
331 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
332 "ilh\t$rT, $val", ImmLoad,
333 [(set R16C:$rT, immSExt16:$val)]>;
335 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
336 // the right constant")
338 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
339 "ilh\t$rT, $val", ImmLoad,
340 [(set R8C:$rT, immSExt8:$val)]>;
342 // IL does sign extension!
344 class ILInst<dag OOL, dag IOL, list<dag> pattern>:
345 RI16Form<0b100000010, OOL, IOL, "il\t$rT, $val",
348 class ILVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
349 ILInst<(outs VECREG:$rT), (ins immtype:$val),
350 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
352 class ILRegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
353 ILInst<(outs rclass:$rT), (ins immtype:$val),
354 [(set rclass:$rT, xform:$val)]>;
356 multiclass ImmediateLoad
358 def v2i64: ILVecInst<v2i64, s16imm_i64, v2i64SExt16Imm>;
359 def v4i32: ILVecInst<v4i32, s16imm_i32, v4i32SExt16Imm>;
361 // TODO: Need v2f64, v4f32
363 def r64: ILRegInst<R64C, s16imm_i64, immSExt16>;
364 def r32: ILRegInst<R32C, s16imm_i32, immSExt16>;
365 def f32: ILRegInst<R32FP, s16imm_f32, fpimmSExt16>;
366 def f64: ILRegInst<R64FP, s16imm_f64, fpimmSExt16>;
369 defm IL : ImmediateLoad;
371 class ILHUInst<dag OOL, dag IOL, list<dag> pattern>:
372 RI16Form<0b010000010, OOL, IOL, "ilhu\t$rT, $val",
375 class ILHUVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
376 ILHUInst<(outs VECREG:$rT), (ins immtype:$val),
377 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
379 class ILHURegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
380 ILHUInst<(outs rclass:$rT), (ins immtype:$val),
381 [(set rclass:$rT, xform:$val)]>;
383 multiclass ImmLoadHalfwordUpper
385 def v2i64: ILHUVecInst<v2i64, u16imm_i64, immILHUvec_i64>;
386 def v4i32: ILHUVecInst<v4i32, u16imm_i32, immILHUvec>;
388 def r64: ILHURegInst<R64C, u16imm_i64, hi16>;
389 def r32: ILHURegInst<R32C, u16imm_i32, hi16>;
391 // Loads the high portion of an address
392 def hi: ILHURegInst<R32C, symbolHi, hi16>;
394 // Used in custom lowering constant SFP loads:
395 def f32: ILHURegInst<R32FP, f16imm, hi16_f32>;
398 defm ILHU : ImmLoadHalfwordUpper;
400 // Immediate load address (can also be used to load 18-bit unsigned constants,
401 // see the zext 16->32 pattern)
403 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
404 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
407 class ILAVecInst<ValueType vectype, Operand immtype, PatLeaf xform>:
408 ILAInst<(outs VECREG:$rT), (ins immtype:$val),
409 [(set (vectype VECREG:$rT), (vectype xform:$val))]>;
411 class ILARegInst<RegisterClass rclass, Operand immtype, PatLeaf xform>:
412 ILAInst<(outs rclass:$rT), (ins immtype:$val),
413 [(set rclass:$rT, xform:$val)]>;
415 multiclass ImmLoadAddress
417 def v2i64: ILAVecInst<v2i64, u18imm, v2i64Uns18Imm>;
418 def v4i32: ILAVecInst<v4i32, u18imm, v4i32Uns18Imm>;
420 def r64: ILARegInst<R64C, u18imm_i64, imm18>;
421 def r32: ILARegInst<R32C, u18imm, imm18>;
422 def f32: ILARegInst<R32FP, f18imm, fpimm18>;
423 def f64: ILARegInst<R64FP, f18imm_f64, fpimm18>;
425 def lo: ILARegInst<R32C, symbolLo, imm18>;
427 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
431 defm ILA : ImmLoadAddress;
433 // Immediate OR, Halfword Lower: The "other" part of loading large constants
434 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
435 // Note that these are really two operand instructions, but they're encoded
436 // as three operands with the first two arguments tied-to each other.
438 class IOHLInst<dag OOL, dag IOL, list<dag> pattern>:
439 RI16Form<0b100000110, OOL, IOL, "iohl\t$rT, $val",
441 RegConstraint<"$rS = $rT">,
444 class IOHLVecInst<ValueType vectype, Operand immtype /* , PatLeaf xform */>:
445 IOHLInst<(outs VECREG:$rT), (ins VECREG:$rS, immtype:$val),
448 class IOHLRegInst<RegisterClass rclass, Operand immtype /* , PatLeaf xform */>:
449 IOHLInst<(outs rclass:$rT), (ins rclass:$rS, immtype:$val),
452 multiclass ImmOrHalfwordLower
454 def v2i64: IOHLVecInst<v2i64, u16imm_i64>;
455 def v4i32: IOHLVecInst<v4i32, u16imm_i32>;
457 def r32: IOHLRegInst<R32C, i32imm>;
458 def f32: IOHLRegInst<R32FP, f32imm>;
460 def lo: IOHLRegInst<R32C, symbolLo>;
463 defm IOHL: ImmOrHalfwordLower;
465 // Form select mask for bytes using immediate, used in conjunction with the
468 class FSMBIVec<ValueType vectype>:
469 RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
472 [(set (vectype VECREG:$rT), (SPUselmask (i16 immU16:$val)))]>;
474 multiclass FormSelectMaskBytesImm
476 def v16i8: FSMBIVec<v16i8>;
477 def v8i16: FSMBIVec<v8i16>;
478 def v4i32: FSMBIVec<v4i32>;
479 def v2i64: FSMBIVec<v2i64>;
482 defm FSMBI : FormSelectMaskBytesImm;
484 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
486 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
487 "fsmb\t$rT, $rA", SelectOp,
488 [(set (v16i8 VECREG:$rT), (SPUselmask R16C:$rA))]>;
490 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
491 // only 8-bits wide (even though it's input as 16-bits here)
493 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
494 "fsmh\t$rT, $rA", SelectOp,
495 [(set (v8i16 VECREG:$rT), (SPUselmask R16C:$rA))]>;
497 // fsm: Form select mask for words. Like the other fsm* instructions,
498 // only the lower 4 bits of $rA are significant.
499 class FSMInst<ValueType vectype, RegisterClass rclass>:
500 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins rclass:$rA),
503 [(set (vectype VECREG:$rT), (SPUselmask rclass:$rA))]>;
505 multiclass FormSelectMaskWord {
506 def r32 : FSMInst<v4i32, R32C>;
507 def r16 : FSMInst<v4i32, R16C>;
510 defm FSM : FormSelectMaskWord;
512 // Special case when used for i64 math operations
513 multiclass FormSelectMaskWord64 {
514 def r32 : FSMInst<v2i64, R32C>;
515 def r16 : FSMInst<v2i64, R16C>;
518 defm FSM64 : FormSelectMaskWord64;
520 //===----------------------------------------------------------------------===//
521 // Integer and Logical Operations:
522 //===----------------------------------------------------------------------===//
525 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
526 "ah\t$rT, $rA, $rB", IntegerOp,
527 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
529 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
530 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
533 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
534 "ah\t$rT, $rA, $rB", IntegerOp,
535 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
538 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
539 "ahi\t$rT, $rA, $val", IntegerOp,
540 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
541 v8i16SExt10Imm:$val))]>;
544 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
545 "ahi\t$rT, $rA, $val", IntegerOp,
546 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
549 RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
550 "a\t$rT, $rA, $rB", IntegerOp,
551 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
553 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
554 (Avec VECREG:$rA, VECREG:$rB)>;
557 RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
558 "a\t$rT, $rA, $rB", IntegerOp,
559 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
562 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
563 "a\t$rT, $rA, $rB", IntegerOp,
567 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
568 "ai\t$rT, $rA, $val", IntegerOp,
569 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
570 v4i32SExt10Imm:$val))]>;
573 RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
574 "ai\t$rT, $rA, $val", IntegerOp,
575 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
578 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
579 "sfh\t$rT, $rA, $rB", IntegerOp,
580 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
581 (v8i16 VECREG:$rB)))]>;
584 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
585 "sfh\t$rT, $rA, $rB", IntegerOp,
586 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
589 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
590 "sfhi\t$rT, $rA, $val", IntegerOp,
591 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
592 (v8i16 VECREG:$rA)))]>;
594 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
595 "sfhi\t$rT, $rA, $val", IntegerOp,
596 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
598 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
599 (ins VECREG:$rA, VECREG:$rB),
600 "sf\t$rT, $rA, $rB", IntegerOp,
601 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
603 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
604 "sf\t$rT, $rA, $rB", IntegerOp,
605 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
608 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
609 "sfi\t$rT, $rA, $val", IntegerOp,
610 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
611 (v4i32 VECREG:$rA)))]>;
613 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
614 (ins R32C:$rA, s10imm_i32:$val),
615 "sfi\t$rT, $rA, $val", IntegerOp,
616 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
618 // ADDX: only available in vector form, doesn't match a pattern.
619 class ADDXInst<dag OOL, dag IOL, list<dag> pattern>:
620 RRForm<0b00000010110, OOL, IOL,
621 "addx\t$rT, $rA, $rB",
624 class ADDXVecInst<ValueType vectype>:
625 ADDXInst<(outs VECREG:$rT),
626 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
627 [(set (vectype VECREG:$rT),
628 (SPUaddx (vectype VECREG:$rA), (vectype VECREG:$rB),
629 (vectype VECREG:$rCarry)))]>,
630 RegConstraint<"$rCarry = $rT">,
633 class ADDXRegInst<RegisterClass rclass>:
634 ADDXInst<(outs rclass:$rT),
635 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
637 (SPUaddx rclass:$rA, rclass:$rB, rclass:$rCarry))]>,
638 RegConstraint<"$rCarry = $rT">,
641 multiclass AddExtended {
642 def v2i64 : ADDXVecInst<v2i64>;
643 def v4i32 : ADDXVecInst<v4i32>;
644 def r64 : ADDXRegInst<R64C>;
645 def r32 : ADDXRegInst<R32C>;
648 defm ADDX : AddExtended;
650 // CG: Generate carry for add
651 class CGInst<dag OOL, dag IOL, list<dag> pattern>:
652 RRForm<0b01000011000, OOL, IOL,
656 class CGVecInst<ValueType vectype>:
657 CGInst<(outs VECREG:$rT),
658 (ins VECREG:$rA, VECREG:$rB),
659 [(set (vectype VECREG:$rT),
660 (SPUcarry_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
662 class CGRegInst<RegisterClass rclass>:
663 CGInst<(outs rclass:$rT),
664 (ins rclass:$rA, rclass:$rB),
666 (SPUcarry_gen rclass:$rA, rclass:$rB))]>;
668 multiclass CarryGenerate {
669 def v2i64 : CGVecInst<v2i64>;
670 def v4i32 : CGVecInst<v4i32>;
671 def r64 : CGRegInst<R64C>;
672 def r32 : CGRegInst<R32C>;
675 defm CG : CarryGenerate;
677 // SFX: Subract from, extended. This is used in conjunction with BG to subtract
678 // with carry (borrow, in this case)
679 class SFXInst<dag OOL, dag IOL, list<dag> pattern>:
680 RRForm<0b10000010110, OOL, IOL,
681 "sfx\t$rT, $rA, $rB",
684 class SFXVecInst<ValueType vectype>:
685 SFXInst<(outs VECREG:$rT),
686 (ins VECREG:$rA, VECREG:$rB, VECREG:$rCarry),
687 [(set (vectype VECREG:$rT),
688 (SPUsubx (vectype VECREG:$rA), (vectype VECREG:$rB),
689 (vectype VECREG:$rCarry)))]>,
690 RegConstraint<"$rCarry = $rT">,
693 class SFXRegInst<RegisterClass rclass>:
694 SFXInst<(outs rclass:$rT),
695 (ins rclass:$rA, rclass:$rB, rclass:$rCarry),
697 (SPUsubx rclass:$rA, rclass:$rB, rclass:$rCarry))]>,
698 RegConstraint<"$rCarry = $rT">,
701 multiclass SubtractExtended {
702 def v2i64 : SFXVecInst<v2i64>;
703 def v4i32 : SFXVecInst<v4i32>;
704 def r64 : SFXRegInst<R64C>;
705 def r32 : SFXRegInst<R32C>;
708 defm SFX : SubtractExtended;
710 // BG: only available in vector form, doesn't match a pattern.
711 class BGInst<dag OOL, dag IOL, list<dag> pattern>:
712 RRForm<0b01000010000, OOL, IOL,
716 class BGVecInst<ValueType vectype>:
717 BGInst<(outs VECREG:$rT),
718 (ins VECREG:$rA, VECREG:$rB),
719 [(set (vectype VECREG:$rT),
720 (SPUborrow_gen (vectype VECREG:$rA), (vectype VECREG:$rB)))]>;
722 class BGRegInst<RegisterClass rclass>:
723 BGInst<(outs rclass:$rT),
724 (ins rclass:$rA, rclass:$rB),
726 (SPUborrow_gen rclass:$rA, rclass:$rB))]>;
728 multiclass BorrowGenerate {
729 def v4i32 : BGVecInst<v4i32>;
730 def v2i64 : BGVecInst<v2i64>;
731 def r64 : BGRegInst<R64C>;
732 def r32 : BGRegInst<R32C>;
735 defm BG : BorrowGenerate;
737 // BGX: Borrow generate, extended.
739 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
741 "bgx\t$rT, $rA, $rB", IntegerOp,
743 RegConstraint<"$rCarry = $rT">,
746 // Halfword multiply variants:
747 // N.B: These can be used to build up larger quantities (16x16 -> 32)
750 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
751 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
752 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
753 (v8i16 VECREG:$rB)))]>;
756 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
757 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
758 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
761 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
762 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
763 [(set (v4i32 VECREG:$rT),
764 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
767 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
768 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
769 [(set R32C:$rT, (mul (zext R16C:$rA),
773 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
774 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
775 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
777 // mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
778 // this only produces the lower 16 bits)
780 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
781 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
782 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
785 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
786 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
787 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
789 // mpyui: same issues as other multiplies, plus, this doesn't match a
790 // pattern... but may be used during target DAG selection or lowering
792 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
793 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
797 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
798 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
801 // mpya: 16 x 16 + 16 -> 32 bit result
803 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
804 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
805 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
806 (v8i16 VECREG:$rB)))),
807 (v4i32 VECREG:$rC)))]>;
810 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
811 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
812 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
815 def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
816 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
818 def MPYAr32_sextinreg:
819 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
820 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
821 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
822 (sext_inreg R32C:$rB, i16)),
826 // RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
827 // "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
828 // [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
831 // mpyh: multiply high, used to synthesize 32-bit multiplies
833 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
834 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
835 [(set (v4i32 VECREG:$rT),
836 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
839 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
840 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
841 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
843 // mpys: multiply high and shift right (returns the top half of
844 // a 16-bit multiply, sign extended to 32 bits.)
846 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
847 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
851 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
852 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
855 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
856 // the top 16 bits of the $rA, $rB)
858 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
859 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
860 [(set (v8i16 VECREG:$rT),
861 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
864 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
865 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
868 // mpyhha: Multiply high-high, add to $rT:
870 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
871 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
875 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
876 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
879 // mpyhhu: Multiply high-high, unsigned
881 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
882 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
886 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
887 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
890 // mpyhhau: Multiply high-high, unsigned
892 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
893 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
897 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
898 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
901 // clz: Count leading zeroes
903 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
904 "clz\t$rT, $rA", IntegerOp,
908 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
909 "clz\t$rT, $rA", IntegerOp,
910 [(set R32C:$rT, (ctlz R32C:$rA))]>;
912 // cntb: Count ones in bytes (aka "population count")
913 // NOTE: This instruction is really a vector instruction, but the custom
914 // lowering code uses it in unorthodox ways to support CTPOP for other
917 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
918 "cntb\t$rT, $rA", IntegerOp,
919 [(set (v16i8 VECREG:$rT), (SPUcntb (v16i8 VECREG:$rA)))]>;
922 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
923 "cntb\t$rT, $rA", IntegerOp,
924 [(set (v8i16 VECREG:$rT), (SPUcntb (v8i16 VECREG:$rA)))]>;
927 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
928 "cntb\t$rT, $rA", IntegerOp,
929 [(set (v4i32 VECREG:$rT), (SPUcntb (v4i32 VECREG:$rA)))]>;
931 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
932 // quantity stored into $rT
934 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
935 "gbb\t$rT, $rA", GatherOp,
938 // gbh: Gather all low order bits from each halfword in $rA into a single
939 // 8-bit quantity stored in $rT
941 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
942 "gbh\t$rT, $rA", GatherOp,
945 // gb: Gather all low order bits from each word in $rA into a single
946 // 4-bit quantity stored in $rT
948 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
949 "gb\t$rT, $rA", GatherOp,
952 // avgb: average bytes
954 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
955 "avgb\t$rT, $rA, $rB", ByteOp,
958 // absdb: absolute difference of bytes
960 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
961 "absdb\t$rT, $rA, $rB", ByteOp,
964 // sumb: sum bytes into halfwords
966 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
967 "sumb\t$rT, $rA, $rB", ByteOp,
970 // Sign extension operations:
971 class XSBHInst<dag OOL, dag IOL, list<dag> pattern>:
972 RRForm_1<0b01101101010, OOL, IOL,
973 "xsbh\t$rDst, $rSrc",
976 class XSBHVecInst<ValueType vectype>:
977 XSBHInst<(outs VECREG:$rDst), (ins VECREG:$rSrc),
978 [(set (v8i16 VECREG:$rDst), (sext (vectype VECREG:$rSrc)))]>;
980 class XSBHRegInst<RegisterClass rclass>:
981 XSBHInst<(outs rclass:$rDst), (ins rclass:$rSrc),
982 [(set rclass:$rDst, (sext_inreg rclass:$rSrc, i8))]>;
984 multiclass ExtendByteHalfword {
985 def v16i8: XSBHVecInst<v8i16>;
986 def r16: XSBHRegInst<R16C>;
988 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
989 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
990 // pattern below). Intentionally doesn't match a pattern because we want the
991 // sext 8->32 pattern to do the work for us, namely because we need the extra
993 def r32: XSBHRegInst<R32C>;
996 defm XSBH : ExtendByteHalfword;
998 // Sign-extend, but take an 8-bit register to a 16-bit register (not done as
1001 XSBHInst<(outs R16C:$rDst), (ins R8C:$rSrc),
1002 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
1004 // Sign extend halfwords to words:
1006 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
1007 "xshw\t$rDest, $rSrc", IntegerOp,
1008 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
1011 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
1012 "xshw\t$rDst, $rSrc", IntegerOp,
1013 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
1016 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
1017 "xshw\t$rDst, $rSrc", IntegerOp,
1018 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
1021 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
1022 "xswd\t$rDst, $rSrc", IntegerOp,
1023 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
1026 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
1027 "xswd\t$rDst, $rSrc", IntegerOp,
1028 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
1031 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
1032 "xswd\t$rDst, $rSrc", IntegerOp,
1033 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
1035 def : Pat<(sext R32C:$inp),
1036 (XSWDr32 R32C:$inp)>;
1040 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
1041 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
1042 IntegerOp, pattern>;
1044 class ANDVecInst<ValueType vectype>:
1045 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1046 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1047 (vectype VECREG:$rB)))]>;
1049 class ANDRegInst<RegisterClass rclass>:
1050 ANDInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1051 [(set rclass:$rT, (and rclass:$rA, rclass:$rB))]>;
1053 multiclass BitwiseAnd
1055 def v16i8: ANDVecInst<v16i8>;
1056 def v8i16: ANDVecInst<v8i16>;
1057 def v4i32: ANDVecInst<v4i32>;
1058 def v2i64: ANDVecInst<v2i64>;
1060 def r128: ANDRegInst<GPRC>;
1061 def r64: ANDRegInst<R64C>;
1062 def r32: ANDRegInst<R32C>;
1063 def r16: ANDRegInst<R16C>;
1064 def r8: ANDRegInst<R8C>;
1066 //===---------------------------------------------
1067 // Special instructions to perform the fabs instruction
1068 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1069 [/* Intentionally does not match a pattern */]>;
1071 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1072 [/* Intentionally does not match a pattern */]>;
1074 // Could use v4i32, but won't for clarity
1075 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1076 [/* Intentionally does not match a pattern */]>;
1078 //===---------------------------------------------
1080 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
1081 // quantities -- see 16->32 zext pattern.
1083 // This pattern is somewhat artificial, since it might match some
1084 // compiler generated pattern but it is unlikely to do so.
1086 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
1087 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
1090 defm AND : BitwiseAnd;
1092 // N.B.: vnot_conv is one of those special target selection pattern fragments,
1093 // in which we expect there to be a bit_convert on the constant. Bear in mind
1094 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
1095 // constant -1 vector.)
1097 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
1098 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
1099 IntegerOp, pattern>;
1101 class ANDCVecInst<ValueType vectype>:
1102 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1103 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
1104 (vnot (vectype VECREG:$rB))))]>;
1106 class ANDCRegInst<RegisterClass rclass>:
1107 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1108 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
1110 multiclass AndComplement
1112 def v16i8: ANDCVecInst<v16i8>;
1113 def v8i16: ANDCVecInst<v8i16>;
1114 def v4i32: ANDCVecInst<v4i32>;
1115 def v2i64: ANDCVecInst<v2i64>;
1117 def r128: ANDCRegInst<GPRC>;
1118 def r64: ANDCRegInst<R64C>;
1119 def r32: ANDCRegInst<R32C>;
1120 def r16: ANDCRegInst<R16C>;
1121 def r8: ANDCRegInst<R8C>;
1124 defm ANDC : AndComplement;
1126 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1127 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1128 IntegerOp, pattern>;
1130 multiclass AndByteImm
1132 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1133 [(set (v16i8 VECREG:$rT),
1134 (and (v16i8 VECREG:$rA),
1135 (v16i8 v16i8U8Imm:$val)))]>;
1137 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1138 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1141 defm ANDBI : AndByteImm;
1143 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1144 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1145 IntegerOp, pattern>;
1147 multiclass AndHalfwordImm
1149 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1150 [(set (v8i16 VECREG:$rT),
1151 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1153 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1154 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1156 // Zero-extend i8 to i16:
1157 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1158 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1161 defm ANDHI : AndHalfwordImm;
1163 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1164 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1165 IntegerOp, pattern>;
1167 multiclass AndWordImm
1169 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1170 [(set (v4i32 VECREG:$rT),
1171 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1173 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1174 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1176 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1178 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1180 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1182 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1183 // zext 16->32 pattern below.
1185 // Note that this pattern is somewhat artificial, since it might match
1186 // something the compiler generates but is unlikely to occur in practice.
1187 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1189 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1192 defm ANDI : AndWordImm;
1194 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1195 // Bitwise OR group:
1196 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1198 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1199 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1200 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1201 IntegerOp, pattern>;
1203 class ORVecInst<ValueType vectype>:
1204 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1205 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1206 (vectype VECREG:$rB)))]>;
1208 class ORRegInst<RegisterClass rclass>:
1209 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1210 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1212 class ORPromoteScalar<RegisterClass rclass>:
1213 ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB),
1214 [/* no pattern */]>;
1216 class ORExtractElt<RegisterClass rclass>:
1217 ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB),
1218 [/* no pattern */]>;
1220 multiclass BitwiseOr
1222 def v16i8: ORVecInst<v16i8>;
1223 def v8i16: ORVecInst<v8i16>;
1224 def v4i32: ORVecInst<v4i32>;
1225 def v2i64: ORVecInst<v2i64>;
1227 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1228 [(set (v4f32 VECREG:$rT),
1229 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1230 (v4i32 VECREG:$rB)))))]>;
1232 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1233 [(set (v2f64 VECREG:$rT),
1234 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1235 (v2i64 VECREG:$rB)))))]>;
1237 def r64: ORRegInst<R64C>;
1238 def r32: ORRegInst<R32C>;
1239 def r16: ORRegInst<R16C>;
1240 def r8: ORRegInst<R8C>;
1242 // OR instructions used to copy f32 and f64 registers.
1243 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1244 [/* no pattern */]>;
1246 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1247 [/* no pattern */]>;
1249 // scalar->vector promotion:
1250 def v16i8_i8: ORPromoteScalar<R8C>;
1251 def v8i16_i16: ORPromoteScalar<R16C>;
1252 def v4i32_i32: ORPromoteScalar<R32C>;
1253 def v2i64_i64: ORPromoteScalar<R64C>;
1254 def v4f32_f32: ORPromoteScalar<R32FP>;
1255 def v2f64_f64: ORPromoteScalar<R64FP>;
1257 // extract element 0:
1258 def i8_v16i8: ORExtractElt<R8C>;
1259 def i16_v8i16: ORExtractElt<R16C>;
1260 def i32_v4i32: ORExtractElt<R32C>;
1261 def i64_v2i64: ORExtractElt<R64C>;
1262 def f32_v4f32: ORExtractElt<R32FP>;
1263 def f64_v2f64: ORExtractElt<R64FP>;
1266 defm OR : BitwiseOr;
1268 // scalar->vector promotion patterns:
1269 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
1270 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
1272 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1273 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1275 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1276 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1278 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1279 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1281 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1282 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1284 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1285 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1287 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1289 def : Pat<(SPUvec2prefslot (v16i8 VECREG:$rA)),
1290 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1292 def : Pat<(SPUvec2prefslot_chained (v16i8 VECREG:$rA)),
1293 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1295 def : Pat<(SPUvec2prefslot (v8i16 VECREG:$rA)),
1296 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1298 def : Pat<(SPUvec2prefslot_chained (v8i16 VECREG:$rA)),
1299 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1301 def : Pat<(SPUvec2prefslot (v4i32 VECREG:$rA)),
1302 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1304 def : Pat<(SPUvec2prefslot_chained (v4i32 VECREG:$rA)),
1305 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1307 def : Pat<(SPUvec2prefslot (v2i64 VECREG:$rA)),
1308 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1310 def : Pat<(SPUvec2prefslot_chained (v2i64 VECREG:$rA)),
1311 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1313 def : Pat<(SPUvec2prefslot (v4f32 VECREG:$rA)),
1314 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1316 def : Pat<(SPUvec2prefslot_chained (v4f32 VECREG:$rA)),
1317 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1319 def : Pat<(SPUvec2prefslot (v2f64 VECREG:$rA)),
1320 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1322 def : Pat<(SPUvec2prefslot_chained (v2f64 VECREG:$rA)),
1323 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1325 // ORC: Bitwise "or" with complement (c = a | ~b)
1327 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1328 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1329 IntegerOp, pattern>;
1331 class ORCVecInst<ValueType vectype>:
1332 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1333 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1334 (vnot (vectype VECREG:$rB))))]>;
1336 class ORCRegInst<RegisterClass rclass>:
1337 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1338 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1340 multiclass BitwiseOrComplement
1342 def v16i8: ORCVecInst<v16i8>;
1343 def v8i16: ORCVecInst<v8i16>;
1344 def v4i32: ORCVecInst<v4i32>;
1345 def v2i64: ORCVecInst<v2i64>;
1347 def r64: ORCRegInst<R64C>;
1348 def r32: ORCRegInst<R32C>;
1349 def r16: ORCRegInst<R16C>;
1350 def r8: ORCRegInst<R8C>;
1353 defm ORC : BitwiseOrComplement;
1355 // OR byte immediate
1356 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1357 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1358 IntegerOp, pattern>;
1360 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1361 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1362 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1363 (vectype immpred:$val)))]>;
1365 multiclass BitwiseOrByteImm
1367 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1369 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1370 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1373 defm ORBI : BitwiseOrByteImm;
1375 // Truncate i16 -> i8
1376 def ORBItrunc : ORBIInst<(outs R8C:$rT), (ins R16C:$rA, u10imm:$val),
1379 def : Pat<(trunc R16C:$rSrc),
1380 (ORBItrunc R16C:$rSrc, 0)>;
1382 // OR halfword immediate
1383 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1384 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1385 IntegerOp, pattern>;
1387 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1388 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1389 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1392 multiclass BitwiseOrHalfwordImm
1394 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1396 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1397 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1399 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1400 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1401 [(set R16C:$rT, (or (anyext R8C:$rA),
1402 i16ImmSExt10:$val))]>;
1405 defm ORHI : BitwiseOrHalfwordImm;
1407 // Truncate i32 -> i16
1408 def ORHItrunc : ORHIInst<(outs R16C:$rT), (ins R32C:$rA, u10imm:$val),
1411 def : Pat<(trunc R32C:$rSrc),
1412 (ORHItrunc R32C:$rSrc, 0)>;
1414 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1415 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1416 IntegerOp, pattern>;
1418 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1419 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1420 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1423 // Bitwise "or" with immediate
1424 multiclass BitwiseOrImm
1426 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1428 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1429 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1431 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1432 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1433 // infra "anyext 16->32" pattern.)
1434 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1435 [(set R32C:$rT, (or (anyext R16C:$rA),
1436 i32ImmSExt10:$val))]>;
1438 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1439 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1440 // infra "anyext 16->32" pattern.)
1441 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1442 [(set R32C:$rT, (or (anyext R8C:$rA),
1443 i32ImmSExt10:$val))]>;
1446 defm ORI : BitwiseOrImm;
1448 // Truncate i64 -> i32
1449 def ORItrunc : ORIInst<(outs R32C:$rT), (ins R64C:$rA, u10imm_i32:$val),
1452 def : Pat<(trunc R64C:$rSrc),
1453 (ORItrunc R64C:$rSrc, 0)>;
1455 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1456 // $rT[0], slots 1-3 are zeroed.
1458 // FIXME: Needs to match an intrinsic pattern.
1460 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1461 "orx\t$rT, $rA, $rB", IntegerOp,
1466 class XORInst<dag OOL, dag IOL, list<dag> pattern> :
1467 RRForm<0b10010010000, OOL, IOL, "xor\t$rT, $rA, $rB",
1468 IntegerOp, pattern>;
1470 class XORVecInst<ValueType vectype>:
1471 XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1472 [(set (vectype VECREG:$rT), (xor (vectype VECREG:$rA),
1473 (vectype VECREG:$rB)))]>;
1475 class XORRegInst<RegisterClass rclass>:
1476 XORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1477 [(set rclass:$rT, (xor rclass:$rA, rclass:$rB))]>;
1479 multiclass BitwiseExclusiveOr
1481 def v16i8: XORVecInst<v16i8>;
1482 def v8i16: XORVecInst<v8i16>;
1483 def v4i32: XORVecInst<v4i32>;
1484 def v2i64: XORVecInst<v2i64>;
1486 def r128: XORRegInst<GPRC>;
1487 def r64: XORRegInst<R64C>;
1488 def r32: XORRegInst<R32C>;
1489 def r16: XORRegInst<R16C>;
1490 def r8: XORRegInst<R8C>;
1492 // Special forms for floating point instructions.
1493 // fneg and fabs require bitwise logical ops to manipulate the sign bit.
1495 def fneg32: XORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1496 [/* no pattern */]>;
1498 def fneg64: XORInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1499 [/* no pattern */]>;
1501 def fnegvec: XORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1502 [/* no pattern, see fneg{32,64} */]>;
1505 defm XOR : BitwiseExclusiveOr;
1507 //==----------------------------------------------------------
1509 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1510 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1511 IntegerOp, pattern>;
1513 multiclass XorByteImm
1516 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1517 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1520 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1521 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1524 defm XORBI : XorByteImm;
1527 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1528 "xorhi\t$rT, $rA, $val", IntegerOp,
1529 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1530 v8i16SExt10Imm:$val))]>;
1533 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1534 "xorhi\t$rT, $rA, $val", IntegerOp,
1535 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1538 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm_i32:$val),
1539 "xori\t$rT, $rA, $val", IntegerOp,
1540 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1541 v4i32SExt10Imm:$val))]>;
1544 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1545 "xori\t$rT, $rA, $val", IntegerOp,
1546 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1550 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1551 "nand\t$rT, $rA, $rB", IntegerOp,
1552 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1553 (v16i8 VECREG:$rB))))]>;
1556 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1557 "nand\t$rT, $rA, $rB", IntegerOp,
1558 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1559 (v8i16 VECREG:$rB))))]>;
1562 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1563 "nand\t$rT, $rA, $rB", IntegerOp,
1564 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1565 (v4i32 VECREG:$rB))))]>;
1568 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1569 "nand\t$rT, $rA, $rB", IntegerOp,
1570 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1573 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1574 "nand\t$rT, $rA, $rB", IntegerOp,
1575 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1578 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1579 "nand\t$rT, $rA, $rB", IntegerOp,
1580 [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
1584 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1585 "nor\t$rT, $rA, $rB", IntegerOp,
1586 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1587 (v16i8 VECREG:$rB))))]>;
1590 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1591 "nor\t$rT, $rA, $rB", IntegerOp,
1592 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1593 (v8i16 VECREG:$rB))))]>;
1596 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1597 "nor\t$rT, $rA, $rB", IntegerOp,
1598 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1599 (v4i32 VECREG:$rB))))]>;
1602 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1603 "nor\t$rT, $rA, $rB", IntegerOp,
1604 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1607 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1608 "nor\t$rT, $rA, $rB", IntegerOp,
1609 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1612 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1613 "nor\t$rT, $rA, $rB", IntegerOp,
1614 [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
1617 class SELBInst<dag OOL, dag IOL, list<dag> pattern>:
1618 RRRForm<0b1000, OOL, IOL, "selb\t$rT, $rA, $rB, $rC",
1619 IntegerOp, pattern>;
1621 class SELBVecInst<ValueType vectype>:
1622 SELBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1623 [(set (vectype VECREG:$rT),
1624 (or (and (vectype VECREG:$rC), (vectype VECREG:$rB)),
1625 (and (vnot (vectype VECREG:$rC)),
1626 (vectype VECREG:$rA))))]>;
1628 class SELBRegInst<RegisterClass rclass>:
1629 SELBInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB, rclass:$rC),
1631 (or (and rclass:$rA, rclass:$rC),
1632 (and rclass:$rB, (not rclass:$rC))))]>;
1634 multiclass SelectBits
1636 def v16i8: SELBVecInst<v16i8>;
1637 def v8i16: SELBVecInst<v8i16>;
1638 def v4i32: SELBVecInst<v4i32>;
1639 def v2i64: SELBVecInst<v2i64>;
1641 def r128: SELBRegInst<GPRC>;
1642 def r64: SELBRegInst<R64C>;
1643 def r32: SELBRegInst<R32C>;
1644 def r16: SELBRegInst<R16C>;
1645 def r8: SELBRegInst<R8C>;
1648 defm SELB : SelectBits;
1650 class SPUselbPatVec<ValueType vectype, SPUInstr inst>:
1651 Pat<(SPUselb (vectype VECREG:$rA), (vectype VECREG:$rB), (vectype VECREG:$rC)),
1652 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1654 def : SPUselbPatVec<v16i8, SELBv16i8>;
1655 def : SPUselbPatVec<v8i16, SELBv8i16>;
1656 def : SPUselbPatVec<v4i32, SELBv4i32>;
1657 def : SPUselbPatVec<v2i64, SELBv2i64>;
1659 class SPUselbPatReg<RegisterClass rclass, SPUInstr inst>:
1660 Pat<(SPUselb rclass:$rA, rclass:$rB, rclass:$rC),
1661 (inst rclass:$rA, rclass:$rB, rclass:$rC)>;
1663 def : SPUselbPatReg<R8C, SELBr8>;
1664 def : SPUselbPatReg<R16C, SELBr16>;
1665 def : SPUselbPatReg<R32C, SELBr32>;
1666 def : SPUselbPatReg<R64C, SELBr64>;
1668 class SelectConditional<RegisterClass rclass, SPUInstr inst>:
1669 Pat<(select rclass:$rCond, rclass:$rTrue, rclass:$rFalse),
1670 (inst rclass:$rFalse, rclass:$rTrue, rclass:$rCond)>;
1672 def : SelectConditional<R32C, SELBr32>;
1673 def : SelectConditional<R16C, SELBr16>;
1674 def : SelectConditional<R8C, SELBr8>;
1676 // EQV: Equivalence (1 for each same bit, otherwise 0)
1678 // Note: There are a lot of ways to match this bit operator and these patterns
1679 // attempt to be as exhaustive as possible.
1681 class EQVInst<dag OOL, dag IOL, list<dag> pattern>:
1682 RRForm<0b10010010000, OOL, IOL, "eqv\t$rT, $rA, $rB",
1683 IntegerOp, pattern>;
1685 class EQVVecInst<ValueType vectype>:
1686 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1687 [(set (vectype VECREG:$rT),
1688 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1689 (and (vnot (vectype VECREG:$rA)),
1690 (vnot (vectype VECREG:$rB)))))]>;
1692 class EQVRegInst<RegisterClass rclass>:
1693 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1694 [(set rclass:$rT, (or (and rclass:$rA, rclass:$rB),
1695 (and (not rclass:$rA), (not rclass:$rB))))]>;
1697 class EQVVecPattern1<ValueType vectype>:
1698 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1699 [(set (vectype VECREG:$rT),
1700 (xor (vectype VECREG:$rA), (vnot (vectype VECREG:$rB))))]>;
1702 class EQVRegPattern1<RegisterClass rclass>:
1703 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1704 [(set rclass:$rT, (xor rclass:$rA, (not rclass:$rB)))]>;
1706 class EQVVecPattern2<ValueType vectype>:
1707 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1708 [(set (vectype VECREG:$rT),
1709 (or (and (vectype VECREG:$rA), (vectype VECREG:$rB)),
1710 (vnot (or (vectype VECREG:$rA), (vectype VECREG:$rB)))))]>;
1712 class EQVRegPattern2<RegisterClass rclass>:
1713 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1715 (or (and rclass:$rA, rclass:$rB),
1716 (not (or rclass:$rA, rclass:$rB))))]>;
1718 class EQVVecPattern3<ValueType vectype>:
1719 EQVInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1720 [(set (vectype VECREG:$rT),
1721 (not (xor (vectype VECREG:$rA), (vectype VECREG:$rB))))]>;
1723 class EQVRegPattern3<RegisterClass rclass>:
1724 EQVInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1725 [(set rclass:$rT, (not (xor rclass:$rA, rclass:$rB)))]>;
1727 multiclass BitEquivalence
1729 def v16i8: EQVVecInst<v16i8>;
1730 def v8i16: EQVVecInst<v8i16>;
1731 def v4i32: EQVVecInst<v4i32>;
1732 def v2i64: EQVVecInst<v2i64>;
1734 def v16i8_1: EQVVecPattern1<v16i8>;
1735 def v8i16_1: EQVVecPattern1<v8i16>;
1736 def v4i32_1: EQVVecPattern1<v4i32>;
1737 def v2i64_1: EQVVecPattern1<v2i64>;
1739 def v16i8_2: EQVVecPattern2<v16i8>;
1740 def v8i16_2: EQVVecPattern2<v8i16>;
1741 def v4i32_2: EQVVecPattern2<v4i32>;
1742 def v2i64_2: EQVVecPattern2<v2i64>;
1744 def v16i8_3: EQVVecPattern3<v16i8>;
1745 def v8i16_3: EQVVecPattern3<v8i16>;
1746 def v4i32_3: EQVVecPattern3<v4i32>;
1747 def v2i64_3: EQVVecPattern3<v2i64>;
1749 def r128: EQVRegInst<GPRC>;
1750 def r64: EQVRegInst<R64C>;
1751 def r32: EQVRegInst<R32C>;
1752 def r16: EQVRegInst<R16C>;
1753 def r8: EQVRegInst<R8C>;
1755 def r128_1: EQVRegPattern1<GPRC>;
1756 def r64_1: EQVRegPattern1<R64C>;
1757 def r32_1: EQVRegPattern1<R32C>;
1758 def r16_1: EQVRegPattern1<R16C>;
1759 def r8_1: EQVRegPattern1<R8C>;
1761 def r128_2: EQVRegPattern2<GPRC>;
1762 def r64_2: EQVRegPattern2<R64C>;
1763 def r32_2: EQVRegPattern2<R32C>;
1764 def r16_2: EQVRegPattern2<R16C>;
1765 def r8_2: EQVRegPattern2<R8C>;
1767 def r128_3: EQVRegPattern3<GPRC>;
1768 def r64_3: EQVRegPattern3<R64C>;
1769 def r32_3: EQVRegPattern3<R32C>;
1770 def r16_3: EQVRegPattern3<R16C>;
1771 def r8_3: EQVRegPattern3<R8C>;
1774 defm EQV: BitEquivalence;
1776 //===----------------------------------------------------------------------===//
1777 // Vector shuffle...
1778 //===----------------------------------------------------------------------===//
1779 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
1780 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
1781 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
1782 // the SPUISD::SHUFB opcode.
1783 //===----------------------------------------------------------------------===//
1785 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
1786 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
1787 IntegerOp, pattern>;
1789 class SHUFBVecInst<ValueType vectype>:
1790 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1791 [(set (vectype VECREG:$rT), (SPUshuffle (vectype VECREG:$rA),
1792 (vectype VECREG:$rB),
1793 (vectype VECREG:$rC)))]>;
1795 // It's this pattern that's probably the most useful, since SPUISelLowering
1796 // methods create a v16i8 vector for $rC:
1797 class SHUFBVecPat1<ValueType vectype, ValueType masktype, SPUInstr inst>:
1798 Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB),
1799 (masktype VECREG:$rC)),
1800 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1802 multiclass ShuffleBytes
1804 def v16i8 : SHUFBVecInst<v16i8>;
1805 def v8i16 : SHUFBVecInst<v8i16>;
1806 def v4i32 : SHUFBVecInst<v4i32>;
1807 def v2i64 : SHUFBVecInst<v2i64>;
1809 def v4f32 : SHUFBVecInst<v4f32>;
1810 def v2f64 : SHUFBVecInst<v2f64>;
1813 defm SHUFB : ShuffleBytes;
1815 // Shuffle mask is a v16i8 vector
1816 def : SHUFBVecPat1<v8i16, v16i8, SHUFBv16i8>;
1817 def : SHUFBVecPat1<v4i32, v16i8, SHUFBv16i8>;
1818 def : SHUFBVecPat1<v2i64, v16i8, SHUFBv16i8>;
1819 def : SHUFBVecPat1<v4f32, v16i8, SHUFBv16i8>;
1820 def : SHUFBVecPat1<v2f64, v16i8, SHUFBv16i8>;
1822 // Shuffle mask is a v4i32 vector:
1823 def : SHUFBVecPat1<v16i8, v4i32, SHUFBv4i32>;
1824 def : SHUFBVecPat1<v8i16, v4i32, SHUFBv4i32>;
1825 def : SHUFBVecPat1<v2i64, v4i32, SHUFBv4i32>;
1826 def : SHUFBVecPat1<v4f32, v4i32, SHUFBv4i32>;
1827 def : SHUFBVecPat1<v2f64, v4i32, SHUFBv4i32>;
1829 //===----------------------------------------------------------------------===//
1830 // Shift and rotate group:
1831 //===----------------------------------------------------------------------===//
1833 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
1834 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
1835 RotateShift, pattern>;
1837 class SHLHVecInst<ValueType vectype>:
1838 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1839 [(set (vectype VECREG:$rT),
1840 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
1842 // $rB gets promoted to 32-bit register type when confronted with
1843 // this llvm assembly code:
1845 // define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
1846 // %A = shl i16 %arg1, %arg2
1850 multiclass ShiftLeftHalfword
1852 def v8i16: SHLHVecInst<v8i16>;
1853 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1854 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1855 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1856 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1859 defm SHLH : ShiftLeftHalfword;
1861 //===----------------------------------------------------------------------===//
1863 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
1864 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
1865 RotateShift, pattern>;
1867 class SHLHIVecInst<ValueType vectype>:
1868 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
1869 [(set (vectype VECREG:$rT),
1870 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
1872 multiclass ShiftLeftHalfwordImm
1874 def v8i16: SHLHIVecInst<v8i16>;
1875 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
1876 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
1879 defm SHLHI : ShiftLeftHalfwordImm;
1881 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
1882 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
1884 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
1885 (SHLHIr16 R16C:$rA, uimm7:$val)>;
1887 //===----------------------------------------------------------------------===//
1889 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
1890 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
1891 RotateShift, pattern>;
1893 multiclass ShiftLeftWord
1896 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1897 [(set (v4i32 VECREG:$rT),
1898 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
1900 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1901 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
1904 defm SHL: ShiftLeftWord;
1906 //===----------------------------------------------------------------------===//
1908 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
1909 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
1910 RotateShift, pattern>;
1912 multiclass ShiftLeftWordImm
1915 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1916 [(set (v4i32 VECREG:$rT),
1917 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
1920 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
1921 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
1924 defm SHLI : ShiftLeftWordImm;
1926 //===----------------------------------------------------------------------===//
1927 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
1928 // register) to the left. Vector form is here to ensure type correctness.
1930 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
1931 // of 7 bits is actually possible.
1933 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
1934 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
1935 // bytes with SHLQBY.
1937 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
1938 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
1939 RotateShift, pattern>;
1941 class SHLQBIVecInst<ValueType vectype>:
1942 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1943 [(set (vectype VECREG:$rT),
1944 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
1946 multiclass ShiftLeftQuadByBits
1948 def v16i8: SHLQBIVecInst<v16i8>;
1949 def v8i16: SHLQBIVecInst<v8i16>;
1950 def v4i32: SHLQBIVecInst<v4i32>;
1951 def v4f32: SHLQBIVecInst<v4f32>;
1952 def v2i64: SHLQBIVecInst<v2i64>;
1953 def v2f64: SHLQBIVecInst<v2f64>;
1956 defm SHLQBI : ShiftLeftQuadByBits;
1958 // See note above on SHLQBI. In this case, the predicate actually does then
1959 // enforcement, whereas with SHLQBI, we have to "take it on faith."
1960 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
1961 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
1962 RotateShift, pattern>;
1964 class SHLQBIIVecInst<ValueType vectype>:
1965 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
1966 [(set (vectype VECREG:$rT),
1967 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
1969 multiclass ShiftLeftQuadByBitsImm
1971 def v16i8 : SHLQBIIVecInst<v16i8>;
1972 def v8i16 : SHLQBIIVecInst<v8i16>;
1973 def v4i32 : SHLQBIIVecInst<v4i32>;
1974 def v4f32 : SHLQBIIVecInst<v4f32>;
1975 def v2i64 : SHLQBIIVecInst<v2i64>;
1976 def v2f64 : SHLQBIIVecInst<v2f64>;
1979 defm SHLQBII : ShiftLeftQuadByBitsImm;
1981 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
1982 // not by bits. See notes above on SHLQBI.
1984 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
1985 RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB",
1986 RotateShift, pattern>;
1988 class SHLQBYVecInst<ValueType vectype>:
1989 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
1990 [(set (vectype VECREG:$rT),
1991 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
1993 multiclass ShiftLeftQuadBytes
1995 def v16i8: SHLQBYVecInst<v16i8>;
1996 def v8i16: SHLQBYVecInst<v8i16>;
1997 def v4i32: SHLQBYVecInst<v4i32>;
1998 def v4f32: SHLQBYVecInst<v4f32>;
1999 def v2i64: SHLQBYVecInst<v2i64>;
2000 def v2f64: SHLQBYVecInst<v2f64>;
2001 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
2002 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
2005 defm SHLQBY: ShiftLeftQuadBytes;
2007 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2008 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
2009 RotateShift, pattern>;
2011 class SHLQBYIVecInst<ValueType vectype>:
2012 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2013 [(set (vectype VECREG:$rT),
2014 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2016 multiclass ShiftLeftQuadBytesImm
2018 def v16i8: SHLQBYIVecInst<v16i8>;
2019 def v8i16: SHLQBYIVecInst<v8i16>;
2020 def v4i32: SHLQBYIVecInst<v4i32>;
2021 def v4f32: SHLQBYIVecInst<v4f32>;
2022 def v2i64: SHLQBYIVecInst<v2i64>;
2023 def v2f64: SHLQBYIVecInst<v2f64>;
2024 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
2026 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
2029 defm SHLQBYI : ShiftLeftQuadBytesImm;
2031 // Special form for truncating i64 to i32:
2032 def SHLQBYItrunc64: SHLQBYIInst<(outs R32C:$rT), (ins R64C:$rA, u7imm_i32:$val),
2033 [/* no pattern, see below */]>;
2035 def : Pat<(trunc R64C:$rSrc),
2036 (SHLQBYItrunc64 R64C:$rSrc, 4)>;
2038 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2040 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2041 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
2042 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
2043 RotateShift, pattern>;
2045 class ROTHVecInst<ValueType vectype>:
2046 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2047 [(set (vectype VECREG:$rT),
2048 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
2050 class ROTHRegInst<RegisterClass rclass>:
2051 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2052 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
2054 multiclass RotateLeftHalfword
2056 def v8i16: ROTHVecInst<v8i16>;
2057 def r16: ROTHRegInst<R16C>;
2060 defm ROTH: RotateLeftHalfword;
2062 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2063 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2065 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2066 // Rotate halfword, immediate:
2067 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2068 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
2069 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
2070 RotateShift, pattern>;
2072 class ROTHIVecInst<ValueType vectype>:
2073 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2074 [(set (vectype VECREG:$rT),
2075 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
2077 multiclass RotateLeftHalfwordImm
2079 def v8i16: ROTHIVecInst<v8i16>;
2080 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2081 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2082 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2083 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2086 defm ROTHI: RotateLeftHalfwordImm;
2088 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
2089 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2091 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2093 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2095 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
2096 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
2097 RotateShift, pattern>;
2099 class ROTVecInst<ValueType vectype>:
2100 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2101 [(set (vectype VECREG:$rT),
2102 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
2104 class ROTRegInst<RegisterClass rclass>:
2105 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2107 (rotl rclass:$rA, R32C:$rB))]>;
2109 multiclass RotateLeftWord
2111 def v4i32: ROTVecInst<v4i32>;
2112 def r32: ROTRegInst<R32C>;
2115 defm ROT: RotateLeftWord;
2117 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2119 def ROTr32_r16_anyext:
2120 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2121 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2123 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
2124 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2126 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
2127 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2129 def ROTr32_r8_anyext:
2130 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2131 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2133 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
2134 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2136 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
2137 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2139 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2140 // Rotate word, immediate
2141 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2143 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
2144 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
2145 RotateShift, pattern>;
2147 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
2148 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2149 [(set (vectype VECREG:$rT),
2150 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2152 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2153 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2154 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2156 multiclass RotateLeftWordImm
2158 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2159 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
2160 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
2162 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
2163 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
2164 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
2167 defm ROTI : RotateLeftWordImm;
2169 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2170 // Rotate quad by byte (count)
2171 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2173 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2174 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2175 RotateShift, pattern>;
2177 class ROTQBYVecInst<ValueType vectype>:
2178 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2179 [(set (vectype VECREG:$rT),
2180 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2182 multiclass RotateQuadLeftByBytes
2184 def v16i8: ROTQBYVecInst<v16i8>;
2185 def v8i16: ROTQBYVecInst<v8i16>;
2186 def v4i32: ROTQBYVecInst<v4i32>;
2187 def v2i64: ROTQBYVecInst<v2i64>;
2190 defm ROTQBY: RotateQuadLeftByBytes;
2192 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
2193 (ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
2194 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
2195 (ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
2196 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
2197 (ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
2198 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
2199 (ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
2201 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2202 // Rotate quad by byte (count), immediate
2203 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2205 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2206 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2207 RotateShift, pattern>;
2209 class ROTQBYIVecInst<ValueType vectype>:
2210 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2211 [(set (vectype VECREG:$rT),
2212 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2214 multiclass RotateQuadByBytesImm
2216 def v16i8: ROTQBYIVecInst<v16i8>;
2217 def v8i16: ROTQBYIVecInst<v8i16>;
2218 def v4i32: ROTQBYIVecInst<v4i32>;
2219 def v2i64: ROTQBYIVecInst<v2i64>;
2222 defm ROTQBYI: RotateQuadByBytesImm;
2224 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2225 (ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
2226 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2227 (ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
2228 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2229 (ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
2230 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
2231 (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
2233 // See ROTQBY note above.
2234 class ROTQBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2235 RI7Form<0b00110011100, OOL, IOL,
2236 "rotqbybi\t$rT, $rA, $shift",
2237 RotateShift, pattern>;
2239 class ROTQBYBIVecInst<ValueType vectype, RegisterClass rclass>:
2240 ROTQBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, rclass:$shift),
2241 [(set (vectype VECREG:$rT),
2242 (SPUrotbytes_left_bits (vectype VECREG:$rA), rclass:$shift))]>;
2244 multiclass RotateQuadByBytesByBitshift {
2245 def v16i8_r32: ROTQBYBIVecInst<v16i8, R32C>;
2246 def v8i16_r32: ROTQBYBIVecInst<v8i16, R32C>;
2247 def v4i32_r32: ROTQBYBIVecInst<v4i32, R32C>;
2248 def v2i64_r32: ROTQBYBIVecInst<v2i64, R32C>;
2251 defm ROTQBYBI : RotateQuadByBytesByBitshift;
2253 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2254 // See ROTQBY note above.
2256 // Assume that the user of this instruction knows to shift the rotate count
2258 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2260 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2261 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2262 RotateShift, pattern>;
2264 class ROTQBIVecInst<ValueType vectype>:
2265 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2266 [/* no pattern yet */]>;
2268 class ROTQBIRegInst<RegisterClass rclass>:
2269 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2270 [/* no pattern yet */]>;
2272 multiclass RotateQuadByBitCount
2274 def v16i8: ROTQBIVecInst<v16i8>;
2275 def v8i16: ROTQBIVecInst<v8i16>;
2276 def v4i32: ROTQBIVecInst<v4i32>;
2277 def v2i64: ROTQBIVecInst<v2i64>;
2279 def r128: ROTQBIRegInst<GPRC>;
2280 def r64: ROTQBIRegInst<R64C>;
2283 defm ROTQBI: RotateQuadByBitCount;
2285 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2286 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2287 RotateShift, pattern>;
2289 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2291 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2292 [/* no pattern yet */]>;
2294 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2296 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2297 [/* no pattern yet */]>;
2299 multiclass RotateQuadByBitCountImm
2301 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2302 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2303 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2304 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2306 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2307 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2310 defm ROTQBII : RotateQuadByBitCountImm;
2312 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2313 // ROTHM v8i16 form:
2314 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2315 // so this only matches a synthetically generated/lowered code
2317 // NOTE(2): $rB must be negated before the right rotate!
2318 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2320 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2321 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2322 RotateShift, pattern>;
2325 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2326 [/* see patterns below - $rB must be negated */]>;
2328 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2329 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2331 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2332 (ROTHMv8i16 VECREG:$rA,
2333 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2335 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2336 (ROTHMv8i16 VECREG:$rA,
2337 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2339 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2340 // Note: This instruction doesn't match a pattern because rB must be negated
2341 // for the instruction to work. Thus, the pattern below the instruction!
2344 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2345 [/* see patterns below - $rB must be negated! */]>;
2347 def : Pat<(srl R16C:$rA, R32C:$rB),
2348 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2350 def : Pat<(srl R16C:$rA, R16C:$rB),
2352 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2354 def : Pat<(srl R16C:$rA, R8C:$rB),
2356 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2358 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2359 // that the immediate can be complemented, so that the user doesn't have to
2362 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2363 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2364 RotateShift, pattern>;
2367 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2368 [/* no pattern */]>;
2370 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2371 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2373 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2374 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2376 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2377 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2380 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2381 [/* no pattern */]>;
2383 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2384 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2386 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2387 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2389 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2390 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2392 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2393 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2394 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2395 RotateShift, pattern>;
2398 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2399 [/* see patterns below - $rB must be negated */]>;
2401 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
2402 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2404 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
2405 (ROTMv4i32 VECREG:$rA,
2406 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2408 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
2409 (ROTMv4i32 VECREG:$rA,
2410 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2413 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2414 [/* see patterns below - $rB must be negated */]>;
2416 def : Pat<(srl R32C:$rA, R32C:$rB),
2417 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2419 def : Pat<(srl R32C:$rA, R16C:$rB),
2421 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2423 def : Pat<(srl R32C:$rA, R8C:$rB),
2425 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2427 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2429 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2430 "rotmi\t$rT, $rA, $val", RotateShift,
2431 [(set (v4i32 VECREG:$rT),
2432 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2434 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
2435 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2437 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
2438 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2440 // ROTMI r32 form: know how to complement the immediate value.
2442 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2443 "rotmi\t$rT, $rA, $val", RotateShift,
2444 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2446 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2447 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2449 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2450 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2452 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2453 // ROTQMBYvec: This is a vector form merely so that when used in an
2454 // instruction pattern, type checking will succeed. This instruction assumes
2455 // that the user knew to negate $rB.
2457 // Using the SPUrotquad_rz_bytes target-specific DAG node, the patterns
2458 // ensure that $rB is negated.
2459 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2461 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2462 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2463 RotateShift, pattern>;
2465 class ROTQMBYVecInst<ValueType vectype>:
2466 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2467 [/* no pattern, $rB must be negated */]>;
2469 class ROTQMBYRegInst<RegisterClass rclass>:
2470 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2472 (SPUrotquad_rz_bytes rclass:$rA, R32C:$rB))]>;
2474 multiclass RotateQuadBytes
2476 def v16i8: ROTQMBYVecInst<v16i8>;
2477 def v8i16: ROTQMBYVecInst<v8i16>;
2478 def v4i32: ROTQMBYVecInst<v4i32>;
2479 def v2i64: ROTQMBYVecInst<v2i64>;
2481 def r128: ROTQMBYRegInst<GPRC>;
2482 def r64: ROTQMBYRegInst<R64C>;
2485 defm ROTQMBY : RotateQuadBytes;
2487 def : Pat<(SPUrotquad_rz_bytes (v16i8 VECREG:$rA), R32C:$rB),
2488 (ROTQMBYv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2489 def : Pat<(SPUrotquad_rz_bytes (v8i16 VECREG:$rA), R32C:$rB),
2490 (ROTQMBYv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2491 def : Pat<(SPUrotquad_rz_bytes (v4i32 VECREG:$rA), R32C:$rB),
2492 (ROTQMBYv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2493 def : Pat<(SPUrotquad_rz_bytes (v2i64 VECREG:$rA), R32C:$rB),
2494 (ROTQMBYv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2495 def : Pat<(SPUrotquad_rz_bytes GPRC:$rA, R32C:$rB),
2496 (ROTQMBYr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2497 def : Pat<(SPUrotquad_rz_bytes R64C:$rA, R32C:$rB),
2498 (ROTQMBYr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2500 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2501 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2502 RotateShift, pattern>;
2504 class ROTQMBYIVecInst<ValueType vectype>:
2505 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2506 [(set (vectype VECREG:$rT),
2507 (SPUrotquad_rz_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2509 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2510 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2512 (SPUrotquad_rz_bytes rclass:$rA, (inttype pred:$val)))]>;
2514 multiclass RotateQuadBytesImm
2516 def v16i8: ROTQMBYIVecInst<v16i8>;
2517 def v8i16: ROTQMBYIVecInst<v8i16>;
2518 def v4i32: ROTQMBYIVecInst<v4i32>;
2519 def v2i64: ROTQMBYIVecInst<v2i64>;
2521 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2522 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2525 defm ROTQMBYI : RotateQuadBytesImm;
2527 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2528 // Rotate right and mask by bit count
2529 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2531 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2532 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2533 RotateShift, pattern>;
2535 class ROTQMBYBIVecInst<ValueType vectype>:
2536 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2537 [/* no pattern, intrinsic? */]>;
2539 multiclass RotateMaskQuadByBitCount
2541 def v16i8: ROTQMBYBIVecInst<v16i8>;
2542 def v8i16: ROTQMBYBIVecInst<v8i16>;
2543 def v4i32: ROTQMBYBIVecInst<v4i32>;
2544 def v2i64: ROTQMBYBIVecInst<v2i64>;
2547 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2549 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2550 // Rotate quad and mask by bits
2551 // Note that the rotate amount has to be negated
2552 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2554 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2555 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2556 RotateShift, pattern>;
2558 class ROTQMBIVecInst<ValueType vectype>:
2559 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2560 [/* no pattern */]>;
2562 class ROTQMBIRegInst<RegisterClass rclass>:
2563 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2564 [/* no pattern */]>;
2566 multiclass RotateMaskQuadByBits
2568 def v16i8: ROTQMBIVecInst<v16i8>;
2569 def v8i16: ROTQMBIVecInst<v8i16>;
2570 def v4i32: ROTQMBIVecInst<v4i32>;
2571 def v2i64: ROTQMBIVecInst<v2i64>;
2573 def r128: ROTQMBIRegInst<GPRC>;
2574 def r64: ROTQMBIRegInst<R64C>;
2577 defm ROTQMBI: RotateMaskQuadByBits;
2579 def : Pat<(SPUrotquad_rz_bits (v16i8 VECREG:$rA), R32C:$rB),
2580 (ROTQMBIv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2581 def : Pat<(SPUrotquad_rz_bits (v8i16 VECREG:$rA), R32C:$rB),
2582 (ROTQMBIv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2583 def : Pat<(SPUrotquad_rz_bits (v4i32 VECREG:$rA), R32C:$rB),
2584 (ROTQMBIv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2585 def : Pat<(SPUrotquad_rz_bits (v2i64 VECREG:$rA), R32C:$rB),
2586 (ROTQMBIv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2587 def : Pat<(SPUrotquad_rz_bits GPRC:$rA, R32C:$rB),
2588 (ROTQMBIr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2589 def : Pat<(SPUrotquad_rz_bits R64C:$rA, R32C:$rB),
2590 (ROTQMBIr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2592 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2593 // Rotate quad and mask by bits, immediate
2594 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2596 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2597 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2598 RotateShift, pattern>;
2600 class ROTQMBIIVecInst<ValueType vectype>:
2601 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2602 [(set (vectype VECREG:$rT),
2603 (SPUrotquad_rz_bits (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2605 class ROTQMBIIRegInst<RegisterClass rclass>:
2606 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2608 (SPUrotquad_rz_bits rclass:$rA, (i32 uimm7:$val)))]>;
2610 multiclass RotateMaskQuadByBitsImm
2612 def v16i8: ROTQMBIIVecInst<v16i8>;
2613 def v8i16: ROTQMBIIVecInst<v8i16>;
2614 def v4i32: ROTQMBIIVecInst<v4i32>;
2615 def v2i64: ROTQMBIIVecInst<v2i64>;
2617 def r128: ROTQMBIIRegInst<GPRC>;
2618 def r64: ROTQMBIIRegInst<R64C>;
2621 defm ROTQMBII: RotateMaskQuadByBitsImm;
2623 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2624 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2627 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2628 "rotmah\t$rT, $rA, $rB", RotateShift,
2629 [/* see patterns below - $rB must be negated */]>;
2631 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2632 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2634 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2635 (ROTMAHv8i16 VECREG:$rA,
2636 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2638 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2639 (ROTMAHv8i16 VECREG:$rA,
2640 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2643 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2644 "rotmah\t$rT, $rA, $rB", RotateShift,
2645 [/* see patterns below - $rB must be negated */]>;
2647 def : Pat<(sra R16C:$rA, R32C:$rB),
2648 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2650 def : Pat<(sra R16C:$rA, R16C:$rB),
2651 (ROTMAHr16 R16C:$rA,
2652 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2654 def : Pat<(sra R16C:$rA, R8C:$rB),
2655 (ROTMAHr16 R16C:$rA,
2656 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2659 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2660 "rotmahi\t$rT, $rA, $val", RotateShift,
2661 [(set (v8i16 VECREG:$rT),
2662 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2664 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2665 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2667 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2668 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2671 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2672 "rotmahi\t$rT, $rA, $val", RotateShift,
2673 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2675 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2676 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2678 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2679 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2682 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2683 "rotma\t$rT, $rA, $rB", RotateShift,
2684 [/* see patterns below - $rB must be negated */]>;
2686 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2687 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2689 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2690 (ROTMAv4i32 (v4i32 VECREG:$rA),
2691 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2693 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2694 (ROTMAv4i32 (v4i32 VECREG:$rA),
2695 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2698 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2699 "rotma\t$rT, $rA, $rB", RotateShift,
2700 [/* see patterns below - $rB must be negated */]>;
2702 def : Pat<(sra R32C:$rA, R32C:$rB),
2703 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2705 def : Pat<(sra R32C:$rA, R16C:$rB),
2707 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2709 def : Pat<(sra R32C:$rA, R8C:$rB),
2711 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2713 class ROTMAIInst<dag OOL, dag IOL, list<dag> pattern>:
2714 RRForm<0b01011110000, OOL, IOL,
2715 "rotmai\t$rT, $rA, $val",
2716 RotateShift, pattern>;
2718 class ROTMAIVecInst<ValueType vectype, Operand intop, ValueType inttype>:
2719 ROTMAIInst<(outs VECREG:$rT), (ins VECREG:$rA, intop:$val),
2720 [(set (vectype VECREG:$rT),
2721 (SPUvec_sra VECREG:$rA, (inttype uimm7:$val)))]>;
2723 class ROTMAIRegInst<RegisterClass rclass, Operand intop, ValueType inttype>:
2724 ROTMAIInst<(outs rclass:$rT), (ins rclass:$rA, intop:$val),
2725 [(set rclass:$rT, (sra rclass:$rA, (inttype uimm7:$val)))]>;
2727 multiclass RotateMaskAlgebraicImm {
2728 def v2i64_i32 : ROTMAIVecInst<v2i64, rotNeg7imm, i32>;
2729 def v4i32_i32 : ROTMAIVecInst<v4i32, rotNeg7imm, i32>;
2730 def r64_i32 : ROTMAIRegInst<R64C, rotNeg7imm, i32>;
2731 def r32_i32 : ROTMAIRegInst<R32C, rotNeg7imm, i32>;
2734 defm ROTMAI : RotateMaskAlgebraicImm;
2736 //===----------------------------------------------------------------------===//
2737 // Branch and conditionals:
2738 //===----------------------------------------------------------------------===//
2740 let isTerminator = 1, isBarrier = 1 in {
2741 // Halt If Equal (r32 preferred slot only, no vector form)
2743 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2744 "heq\t$rA, $rB", BranchResolv,
2745 [/* no pattern to match */]>;
2748 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2749 "heqi\t$rA, $val", BranchResolv,
2750 [/* no pattern to match */]>;
2752 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2753 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2755 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2756 "hgt\t$rA, $rB", BranchResolv,
2757 [/* no pattern to match */]>;
2760 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2761 "hgti\t$rA, $val", BranchResolv,
2762 [/* no pattern to match */]>;
2765 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2766 "hlgt\t$rA, $rB", BranchResolv,
2767 [/* no pattern to match */]>;
2770 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2771 "hlgti\t$rA, $val", BranchResolv,
2772 [/* no pattern to match */]>;
2775 //------------------------------------------------------------------------
2776 // Comparison operators:
2777 //------------------------------------------------------------------------
2779 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
2780 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
2783 multiclass CmpEqualByte
2786 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2787 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2788 (v8i16 VECREG:$rB)))]>;
2791 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2792 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
2795 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
2796 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
2799 multiclass CmpEqualByteImm
2802 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2803 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
2804 v16i8SExt8Imm:$val))]>;
2806 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2807 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
2810 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
2811 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
2814 multiclass CmpEqualHalfword
2816 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2817 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2818 (v8i16 VECREG:$rB)))]>;
2820 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2821 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
2824 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
2825 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
2828 multiclass CmpEqualHalfwordImm
2830 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2831 [(set (v8i16 VECREG:$rT),
2832 (seteq (v8i16 VECREG:$rA),
2833 (v8i16 v8i16SExt10Imm:$val)))]>;
2834 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2835 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
2838 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
2839 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
2842 multiclass CmpEqualWord
2844 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2845 [(set (v4i32 VECREG:$rT),
2846 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2848 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2849 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2852 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
2853 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
2856 multiclass CmpEqualWordImm
2858 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2859 [(set (v4i32 VECREG:$rT),
2860 (seteq (v4i32 VECREG:$rA),
2861 (v4i32 v4i32SExt16Imm:$val)))]>;
2863 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2864 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2867 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2868 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
2871 multiclass CmpGtrByte
2874 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2875 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2876 (v8i16 VECREG:$rB)))]>;
2879 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2880 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
2883 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2884 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
2887 multiclass CmpGtrByteImm
2890 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2891 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
2892 v16i8SExt8Imm:$val))]>;
2894 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2895 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
2898 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2899 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
2902 multiclass CmpGtrHalfword
2904 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2905 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2906 (v8i16 VECREG:$rB)))]>;
2908 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2909 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
2912 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
2913 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
2916 multiclass CmpGtrHalfwordImm
2918 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2919 [(set (v8i16 VECREG:$rT),
2920 (setgt (v8i16 VECREG:$rA),
2921 (v8i16 v8i16SExt10Imm:$val)))]>;
2922 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2923 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
2926 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
2927 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
2930 multiclass CmpGtrWord
2932 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2933 [(set (v4i32 VECREG:$rT),
2934 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2936 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2937 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
2940 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
2941 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
2944 multiclass CmpGtrWordImm
2946 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2947 [(set (v4i32 VECREG:$rT),
2948 (setgt (v4i32 VECREG:$rA),
2949 (v4i32 v4i32SExt16Imm:$val)))]>;
2951 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2952 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
2955 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2956 RRForm<0b00001011010, OOL, IOL, "clgtb\t$rT, $rA, $rB",
2959 multiclass CmpLGtrByte
2962 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2963 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2964 (v8i16 VECREG:$rB)))]>;
2967 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2968 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
2971 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2972 RI10Form<0b01111010, OOL, IOL, "clgtbi\t$rT, $rA, $val",
2975 multiclass CmpLGtrByteImm
2978 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2979 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
2980 v16i8SExt8Imm:$val))]>;
2982 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2983 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
2986 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
2987 RRForm<0b00010011010, OOL, IOL, "clgth\t$rT, $rA, $rB",
2990 multiclass CmpLGtrHalfword
2992 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2993 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
2994 (v8i16 VECREG:$rB)))]>;
2996 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2997 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
3000 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
3001 RI10Form<0b10111010, OOL, IOL, "clgthi\t$rT, $rA, $val",
3004 multiclass CmpLGtrHalfwordImm
3006 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3007 [(set (v8i16 VECREG:$rT),
3008 (setugt (v8i16 VECREG:$rA),
3009 (v8i16 v8i16SExt10Imm:$val)))]>;
3010 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3011 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
3014 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
3015 RRForm<0b00000011010, OOL, IOL, "clgt\t$rT, $rA, $rB",
3018 multiclass CmpLGtrWord
3020 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3021 [(set (v4i32 VECREG:$rT),
3022 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3024 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3025 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
3028 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
3029 RI10Form<0b00111010, OOL, IOL, "clgti\t$rT, $rA, $val",
3032 multiclass CmpLGtrWordImm
3034 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3035 [(set (v4i32 VECREG:$rT),
3036 (setugt (v4i32 VECREG:$rA),
3037 (v4i32 v4i32SExt16Imm:$val)))]>;
3039 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3040 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
3043 defm CEQB : CmpEqualByte;
3044 defm CEQBI : CmpEqualByteImm;
3045 defm CEQH : CmpEqualHalfword;
3046 defm CEQHI : CmpEqualHalfwordImm;
3047 defm CEQ : CmpEqualWord;
3048 defm CEQI : CmpEqualWordImm;
3049 defm CGTB : CmpGtrByte;
3050 defm CGTBI : CmpGtrByteImm;
3051 defm CGTH : CmpGtrHalfword;
3052 defm CGTHI : CmpGtrHalfwordImm;
3053 defm CGT : CmpGtrWord;
3054 defm CGTI : CmpGtrWordImm;
3055 defm CLGTB : CmpLGtrByte;
3056 defm CLGTBI : CmpLGtrByteImm;
3057 defm CLGTH : CmpLGtrHalfword;
3058 defm CLGTHI : CmpLGtrHalfwordImm;
3059 defm CLGT : CmpLGtrWord;
3060 defm CLGTI : CmpLGtrWordImm;
3062 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3063 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
3064 // define a pattern to generate the right code, as a binary operator
3065 // (in a manner of speaking.)
3067 // N.B.: This only matches the setcc set of conditionals. Special pattern
3068 // matching is used for select conditionals.
3069 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3071 class SETCCNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3072 SPUInstr xorinst, SPUInstr cmpare>:
3073 Pat<(cond rclass:$rA, rclass:$rB),
3074 (xorinst (cmpare rclass:$rA, rclass:$rB), (inttype -1))>;
3076 class SETCCNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3077 PatLeaf immpred, SPUInstr xorinst, SPUInstr cmpare>:
3078 Pat<(cond rclass:$rA, (inttype immpred:$imm)),
3079 (xorinst (cmpare rclass:$rA, (inttype immpred:$imm)), (inttype -1))>;
3081 def : SETCCNegCondReg<setne, R8C, i8, XORBIr8, CEQBr8>;
3082 def : SETCCNegCondImm<setne, R8C, i8, immSExt8, XORBIr8, CEQBIr8>;
3084 def : SETCCNegCondReg<setne, R16C, i16, XORHIr16, CEQHr16>;
3085 def : SETCCNegCondImm<setne, R16C, i16, i16ImmSExt10, XORHIr16, CEQHIr16>;
3087 def : SETCCNegCondReg<setne, R32C, i32, XORIr32, CEQr32>;
3088 def : SETCCNegCondImm<setne, R32C, i32, i32ImmSExt10, XORIr32, CEQIr32>;
3090 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
3091 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3092 Pat<(cond rclass:$rA, rclass:$rB),
3093 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3094 (cmpOp2 rclass:$rA, rclass:$rB))>;
3096 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3098 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3099 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
3100 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
3101 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
3103 def : SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
3104 def : SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
3105 def : SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
3106 def : SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
3107 def : Pat<(setle R8C:$rA, R8C:$rB),
3108 (XORBIr8 (CGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3109 def : Pat<(setle R8C:$rA, immU8:$imm),
3110 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3112 def : SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
3113 def : SETCCBinOpImm<setge, R16C, i16ImmSExt10, i16,
3114 ORr16, CGTHIr16, CEQHIr16>;
3115 def : SETCCBinOpReg<setlt, R16C, NORr16, CGTHr16, CEQHr16>;
3116 def : SETCCBinOpImm<setlt, R16C, i16ImmSExt10, i16, NORr16, CGTHIr16, CEQHIr16>;
3117 def : Pat<(setle R16C:$rA, R16C:$rB),
3118 (XORHIr16 (CGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3119 def : Pat<(setle R16C:$rA, i16ImmSExt10:$imm),
3120 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3122 def : SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
3123 def : SETCCBinOpImm<setge, R32C, i32ImmSExt10, i32,
3124 ORr32, CGTIr32, CEQIr32>;
3125 def : SETCCBinOpReg<setlt, R32C, NORr32, CGTr32, CEQr32>;
3126 def : SETCCBinOpImm<setlt, R32C, i32ImmSExt10, i32, NORr32, CGTIr32, CEQIr32>;
3127 def : Pat<(setle R32C:$rA, R32C:$rB),
3128 (XORIr32 (CGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3129 def : Pat<(setle R32C:$rA, i32ImmSExt10:$imm),
3130 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3132 def : SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
3133 def : SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
3134 def : SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
3135 def : SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
3136 def : Pat<(setule R8C:$rA, R8C:$rB),
3137 (XORBIr8 (CLGTBr8 R8C:$rA, R8C:$rB), 0xff)>;
3138 def : Pat<(setule R8C:$rA, immU8:$imm),
3139 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3141 def : SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
3142 def : SETCCBinOpImm<setuge, R16C, i16ImmSExt10, i16,
3143 ORr16, CLGTHIr16, CEQHIr16>;
3144 def : SETCCBinOpReg<setult, R16C, NORr16, CLGTHr16, CEQHr16>;
3145 def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
3146 CLGTHIr16, CEQHIr16>;
3147 def : Pat<(setule R16C:$rA, R16C:$rB),
3148 (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
3149 def : Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
3150 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3152 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
3153 def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
3154 ORr32, CLGTIr32, CEQIr32>;
3155 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
3156 def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
3157 def : Pat<(setule R32C:$rA, R32C:$rB),
3158 (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3159 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),
3160 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3162 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3163 // select conditional patterns:
3164 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3166 class SELECTNegCondReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3167 SPUInstr selinstr, SPUInstr cmpare>:
3168 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3169 rclass:$rTrue, rclass:$rFalse),
3170 (selinstr rclass:$rTrue, rclass:$rFalse,
3171 (cmpare rclass:$rA, rclass:$rB))>;
3173 class SELECTNegCondImm<PatFrag cond, RegisterClass rclass, ValueType inttype,
3174 PatLeaf immpred, SPUInstr selinstr, SPUInstr cmpare>:
3175 Pat<(select (inttype (cond rclass:$rA, immpred:$imm)),
3176 rclass:$rTrue, rclass:$rFalse),
3177 (selinstr rclass:$rTrue, rclass:$rFalse,
3178 (cmpare rclass:$rA, immpred:$imm))>;
3180 def : SELECTNegCondReg<setne, R8C, i8, SELBr8, CEQBr8>;
3181 def : SELECTNegCondImm<setne, R8C, i8, immSExt8, SELBr8, CEQBIr8>;
3182 def : SELECTNegCondReg<setle, R8C, i8, SELBr8, CGTBr8>;
3183 def : SELECTNegCondImm<setle, R8C, i8, immSExt8, SELBr8, CGTBr8>;
3184 def : SELECTNegCondReg<setule, R8C, i8, SELBr8, CLGTBr8>;
3185 def : SELECTNegCondImm<setule, R8C, i8, immU8, SELBr8, CLGTBIr8>;
3187 def : SELECTNegCondReg<setne, R16C, i16, SELBr16, CEQHr16>;
3188 def : SELECTNegCondImm<setne, R16C, i16, i16ImmSExt10, SELBr16, CEQHIr16>;
3189 def : SELECTNegCondReg<setle, R16C, i16, SELBr16, CGTHr16>;
3190 def : SELECTNegCondImm<setle, R16C, i16, i16ImmSExt10, SELBr16, CGTHIr16>;
3191 def : SELECTNegCondReg<setule, R16C, i16, SELBr16, CLGTHr16>;
3192 def : SELECTNegCondImm<setule, R16C, i16, i16ImmSExt10, SELBr16, CLGTHIr16>;
3194 def : SELECTNegCondReg<setne, R32C, i32, SELBr32, CEQr32>;
3195 def : SELECTNegCondImm<setne, R32C, i32, i32ImmSExt10, SELBr32, CEQIr32>;
3196 def : SELECTNegCondReg<setle, R32C, i32, SELBr32, CGTr32>;
3197 def : SELECTNegCondImm<setle, R32C, i32, i32ImmSExt10, SELBr32, CGTIr32>;
3198 def : SELECTNegCondReg<setule, R32C, i32, SELBr32, CLGTr32>;
3199 def : SELECTNegCondImm<setule, R32C, i32, i32ImmSExt10, SELBr32, CLGTIr32>;
3201 class SELECTBinOpReg<PatFrag cond, RegisterClass rclass, ValueType inttype,
3202 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3204 Pat<(select (inttype (cond rclass:$rA, rclass:$rB)),
3205 rclass:$rFalse, rclass:$rTrue),
3206 (selinstr rclass:$rTrue, rclass:$rFalse,
3207 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3208 (cmpOp2 rclass:$rA, rclass:$rB)))>;
3210 class SELECTBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3212 SPUInstr selinstr, SPUInstr binop, SPUInstr cmpOp1,
3214 Pat<(select (inttype (cond rclass:$rA, (inttype immpred:$imm))),
3215 rclass:$rTrue, rclass:$rFalse),
3216 (selinstr rclass:$rFalse, rclass:$rTrue,
3217 (binop (cmpOp1 rclass:$rA, (inttype immpred:$imm)),
3218 (cmpOp2 rclass:$rA, (inttype immpred:$imm))))>;
3220 def : SELECTBinOpReg<setge, R8C, i8, SELBr8, ORr8, CGTBr8, CEQBr8>;
3221 def : SELECTBinOpImm<setge, R8C, immSExt8, i8,
3222 SELBr8, ORr8, CGTBIr8, CEQBIr8>;
3224 def : SELECTBinOpReg<setge, R16C, i16, SELBr16, ORr16, CGTHr16, CEQHr16>;
3225 def : SELECTBinOpImm<setge, R16C, i16ImmSExt10, i16,
3226 SELBr16, ORr16, CGTHIr16, CEQHIr16>;
3228 def : SELECTBinOpReg<setge, R32C, i32, SELBr32, ORr32, CGTr32, CEQr32>;
3229 def : SELECTBinOpImm<setge, R32C, i32ImmSExt10, i32,
3230 SELBr32, ORr32, CGTIr32, CEQIr32>;
3232 def : SELECTBinOpReg<setuge, R8C, i8, SELBr8, ORr8, CLGTBr8, CEQBr8>;
3233 def : SELECTBinOpImm<setuge, R8C, immSExt8, i8,
3234 SELBr8, ORr8, CLGTBIr8, CEQBIr8>;
3236 def : SELECTBinOpReg<setuge, R16C, i16, SELBr16, ORr16, CLGTHr16, CEQHr16>;
3237 def : SELECTBinOpImm<setuge, R16C, i16ImmUns10, i16,
3238 SELBr16, ORr16, CLGTHIr16, CEQHIr16>;
3240 def : SELECTBinOpReg<setuge, R32C, i32, SELBr32, ORr32, CLGTr32, CEQr32>;
3241 def : SELECTBinOpImm<setuge, R32C, i32ImmUns10, i32,
3242 SELBr32, ORr32, CLGTIr32, CEQIr32>;
3244 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3247 // All calls clobber the non-callee-saved registers:
3248 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
3249 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
3250 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
3251 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
3252 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
3253 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
3254 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
3255 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
3256 // All of these instructions use $lr (aka $0)
3258 // Branch relative and set link: Used if we actually know that the target
3259 // is within [-32768, 32767] bytes of the target
3261 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
3262 "brsl\t$$lr, $func",
3263 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
3265 // Branch absolute and set link: Used if we actually know that the target
3266 // is an absolute address
3268 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
3269 "brasl\t$$lr, $func",
3270 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
3272 // Branch indirect and set link if external data. These instructions are not
3273 // actually generated, matched by an intrinsic:
3274 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
3275 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
3276 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
3277 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
3279 // Branch indirect and set link. This is the "X-form" address version of a
3282 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
3285 // Unconditional branches:
3286 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
3288 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3292 // Unconditional, absolute address branch
3294 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3296 [/* no pattern */]>;
3300 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3302 // Various branches:
3304 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
3305 "brnz\t$rCond,$dest",
3307 [(brcond R32C:$rCond, bb:$dest)]>;
3310 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
3313 [/* no pattern */]>;
3316 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
3317 "brhnz\t$rCond,$dest",
3319 [(brcond R16C:$rCond, bb:$dest)]>;
3322 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
3325 [/* no pattern */]>;
3329 BICondForm<0b10010100100, "binz\t$rA, $func",
3330 [(SPUbinz R32C:$rA, R32C:$func)]>;
3333 BICondForm<0b00010100100, "biz\t$rA, $func",
3334 [(SPUbiz R32C:$rA, R32C:$func)]>;
3338 //===----------------------------------------------------------------------===//
3339 // setcc and brcond patterns:
3340 //===----------------------------------------------------------------------===//
3342 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3343 (BRHZ R16C:$rA, bb:$dest)>;
3344 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3345 (BRHNZ R16C:$rA, bb:$dest)>;
3347 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3348 (BRZ R32C:$rA, bb:$dest)>;
3349 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3350 (BRNZ R32C:$rA, bb:$dest)>;
3352 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3354 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3355 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3357 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3358 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3360 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3361 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3363 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3364 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3367 defm BRCONDeq : BranchCondEQ<seteq, BRHZ, BRZ>;
3368 defm BRCONDne : BranchCondEQ<setne, BRHNZ, BRNZ>;
3370 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3372 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3373 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3375 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3376 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3378 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3379 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3381 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3382 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3385 defm BRCONDugt : BranchCondLGT<setugt, BRHNZ, BRNZ>;
3386 defm BRCONDule : BranchCondLGT<setule, BRHZ, BRZ>;
3388 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3389 SPUInstr orinst32, SPUInstr brinst32>
3391 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3392 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3393 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3396 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3397 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3398 (CEQHr16 R16C:$rA, R16:$rB)),
3401 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3402 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3403 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3406 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3407 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3408 (CEQr32 R32C:$rA, R32C:$rB)),
3412 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZ, ORr32, BRNZ>;
3413 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZ, ORr32, BRZ>;
3415 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3417 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3418 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3420 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3421 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3423 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3424 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3426 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3427 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3430 defm BRCONDgt : BranchCondGT<setgt, BRHNZ, BRNZ>;
3431 defm BRCONDle : BranchCondGT<setle, BRHZ, BRZ>;
3433 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3434 SPUInstr orinst32, SPUInstr brinst32>
3436 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3437 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3438 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3441 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3442 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3443 (CEQHr16 R16C:$rA, R16:$rB)),
3446 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3447 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3448 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3451 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3452 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3453 (CEQr32 R32C:$rA, R32C:$rB)),
3457 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZ, ORr32, BRNZ>;
3458 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZ, ORr32, BRZ>;
3460 let isTerminator = 1, isBarrier = 1 in {
3461 let isReturn = 1 in {
3463 RETForm<"bi\t$$lr", [(retflag)]>;
3467 //===----------------------------------------------------------------------===//
3468 // Single precision floating point instructions
3469 //===----------------------------------------------------------------------===//
3472 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3473 "fa\t$rT, $rA, $rB", SPrecFP,
3474 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3477 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3478 "fa\t$rT, $rA, $rB", SPrecFP,
3479 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3482 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3483 "fs\t$rT, $rA, $rB", SPrecFP,
3484 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3487 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3488 "fs\t$rT, $rA, $rB", SPrecFP,
3489 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3491 // Floating point reciprocal estimate
3493 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
3494 "frest\t$rT, $rA", SPrecFP,
3495 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
3498 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
3499 "frest\t$rT, $rA", SPrecFP,
3500 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
3502 // Floating point interpolate (used in conjunction with reciprocal estimate)
3504 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3505 "fi\t$rT, $rA, $rB", SPrecFP,
3506 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
3507 (v4f32 VECREG:$rB)))]>;
3510 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3511 "fi\t$rT, $rA, $rB", SPrecFP,
3512 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
3514 //--------------------------------------------------------------------------
3515 // Basic single precision floating point comparisons:
3517 // Note: There is no support on SPU for single precision NaN. Consequently,
3518 // ordered and unordered comparisons are the same.
3519 //--------------------------------------------------------------------------
3522 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3523 "fceq\t$rT, $rA, $rB", SPrecFP,
3524 [(set R32C:$rT, (setueq R32FP:$rA, R32FP:$rB))]>;
3526 def : Pat<(setoeq R32FP:$rA, R32FP:$rB),
3527 (FCEQf32 R32FP:$rA, R32FP:$rB)>;
3530 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3531 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3532 [(set R32C:$rT, (setueq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3534 def : Pat<(setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)),
3535 (FCMEQf32 R32FP:$rA, R32FP:$rB)>;
3538 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3539 "fcgt\t$rT, $rA, $rB", SPrecFP,
3540 [(set R32C:$rT, (setugt R32FP:$rA, R32FP:$rB))]>;
3542 def : Pat<(setugt R32FP:$rA, R32FP:$rB),
3543 (FCGTf32 R32FP:$rA, R32FP:$rB)>;
3546 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3547 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3548 [(set R32C:$rT, (setugt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3550 def : Pat<(setugt (fabs R32FP:$rA), (fabs R32FP:$rB)),
3551 (FCMGTf32 R32FP:$rA, R32FP:$rB)>;
3553 //--------------------------------------------------------------------------
3554 // Single precision floating point comparisons and SETCC equivalents:
3555 //--------------------------------------------------------------------------
3557 def : SETCCNegCondReg<setune, R32FP, i32, XORIr32, FCEQf32>;
3558 def : SETCCNegCondReg<setone, R32FP, i32, XORIr32, FCEQf32>;
3560 def : SETCCBinOpReg<setuge, R32FP, ORr32, FCGTf32, FCEQf32>;
3561 def : SETCCBinOpReg<setoge, R32FP, ORr32, FCGTf32, FCEQf32>;
3563 def : SETCCBinOpReg<setult, R32FP, NORr32, FCGTf32, FCEQf32>;
3564 def : SETCCBinOpReg<setolt, R32FP, NORr32, FCGTf32, FCEQf32>;
3566 def : Pat<(setule R32FP:$rA, R32FP:$rB),
3567 (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
3568 def : Pat<(setole R32FP:$rA, R32FP:$rB),
3569 (XORIr32 (FCGTf32 R32FP:$rA, R32FP:$rB), 0xffffffff)>;
3571 // FP Status and Control Register Write
3572 // Why isn't rT a don't care in the ISA?
3573 // Should we create a special RRForm_3 for this guy and zero out the rT?
3575 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3576 "fscrwr\t$rA", SPrecFP,
3577 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3579 // FP Status and Control Register Read
3581 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3582 "fscrrd\t$rT", SPrecFP,
3583 [/* This instruction requires an intrinsic */]>;
3585 // llvm instruction space
3586 // How do these map onto cell instructions?
3588 // frest rC rB # c = 1/b (both lines)
3590 // fm rD rA rC # d = a * 1/b
3591 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3592 // fma rB rB rC rD # b = b * c + d
3593 // = -(d *b -a) * c + d
3594 // = a * c - c ( a *b *c - a)
3599 // These llvm instructions will actually map to library calls.
3600 // All that's needed, then, is to check that the appropriate library is
3601 // imported and do a brsl to the proper function name.
3602 // frem # fmod(x, y): x - (x/y) * y
3603 // (Note: fmod(double, double), fmodf(float,float)
3607 // Unimplemented SPU instruction space
3608 // floating reciprocal absolute square root estimate (frsqest)
3610 // The following are probably just intrinsics
3611 // status and control register write
3612 // status and control register read
3614 //--------------------------------------
3615 // Floating point multiply instructions
3616 //--------------------------------------
3619 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3620 "fm\t$rT, $rA, $rB", SPrecFP,
3621 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
3622 (v4f32 VECREG:$rB)))]>;
3625 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3626 "fm\t$rT, $rA, $rB", SPrecFP,
3627 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
3629 // Floating point multiply and add
3630 // e.g. d = c + (a * b)
3632 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3633 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3634 [(set (v4f32 VECREG:$rT),
3635 (fadd (v4f32 VECREG:$rC),
3636 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
3639 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3640 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3641 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3643 // FP multiply and subtract
3644 // Subtracts value in rC from product
3647 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3648 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3649 [(set (v4f32 VECREG:$rT),
3650 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
3651 (v4f32 VECREG:$rC)))]>;
3654 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3655 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3657 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
3659 // Floating Negative Mulitply and Subtract
3660 // Subtracts product from value in rC
3661 // res = fneg(fms a b c)
3664 // NOTE: subtraction order
3668 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3669 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3670 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3673 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3674 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3675 [(set (v4f32 VECREG:$rT),
3676 (fsub (v4f32 VECREG:$rC),
3677 (fmul (v4f32 VECREG:$rA),
3678 (v4f32 VECREG:$rB))))]>;
3680 //--------------------------------------
3681 // Floating Point Conversions
3682 // Signed conversions:
3684 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3685 "csflt\t$rT, $rA, 0", SPrecFP,
3686 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
3688 // Convert signed integer to floating point
3690 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
3691 "csflt\t$rT, $rA, 0", SPrecFP,
3692 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
3694 // Convert unsigned into to float
3696 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3697 "cuflt\t$rT, $rA, 0", SPrecFP,
3698 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
3701 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
3702 "cuflt\t$rT, $rA, 0", SPrecFP,
3703 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
3705 // Convert float to unsigned int
3706 // Assume that scale = 0
3709 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3710 "cfltu\t$rT, $rA, 0", SPrecFP,
3711 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
3714 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3715 "cfltu\t$rT, $rA, 0", SPrecFP,
3716 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
3718 // Convert float to signed int
3719 // Assume that scale = 0
3722 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3723 "cflts\t$rT, $rA, 0", SPrecFP,
3724 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
3727 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3728 "cflts\t$rT, $rA, 0", SPrecFP,
3729 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
3731 //===----------------------------------------------------------------------==//
3732 // Single<->Double precision conversions
3733 //===----------------------------------------------------------------------==//
3735 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
3736 // v4f32, output is v2f64--which goes in the name?)
3738 // Floating point extend single to double
3739 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
3740 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
3743 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3744 "fesd\t$rT, $rA", SPrecFP,
3745 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
3748 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
3749 "fesd\t$rT, $rA", SPrecFP,
3750 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
3752 // Floating point round double to single
3754 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3755 // "frds\t$rT, $rA,", SPrecFP,
3756 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
3759 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
3760 "frds\t$rT, $rA", SPrecFP,
3761 [(set R32FP:$rT, (fround R64FP:$rA))]>;
3763 //ToDo include anyextend?
3765 //===----------------------------------------------------------------------==//
3766 // Double precision floating point instructions
3767 //===----------------------------------------------------------------------==//
3769 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3770 "dfa\t$rT, $rA, $rB", DPrecFP,
3771 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
3774 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3775 "dfa\t$rT, $rA, $rB", DPrecFP,
3776 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3779 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3780 "dfs\t$rT, $rA, $rB", DPrecFP,
3781 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
3784 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3785 "dfs\t$rT, $rA, $rB", DPrecFP,
3786 [(set (v2f64 VECREG:$rT),
3787 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3790 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3791 "dfm\t$rT, $rA, $rB", DPrecFP,
3792 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
3795 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3796 "dfm\t$rT, $rA, $rB", DPrecFP,
3797 [(set (v2f64 VECREG:$rT),
3798 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3801 RRForm<0b00111010110, (outs R64FP:$rT),
3802 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3803 "dfma\t$rT, $rA, $rB", DPrecFP,
3804 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3805 RegConstraint<"$rC = $rT">,
3809 RRForm<0b00111010110, (outs VECREG:$rT),
3810 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3811 "dfma\t$rT, $rA, $rB", DPrecFP,
3812 [(set (v2f64 VECREG:$rT),
3813 (fadd (v2f64 VECREG:$rC),
3814 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
3815 RegConstraint<"$rC = $rT">,
3819 RRForm<0b10111010110, (outs R64FP:$rT),
3820 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3821 "dfms\t$rT, $rA, $rB", DPrecFP,
3822 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
3823 RegConstraint<"$rC = $rT">,
3827 RRForm<0b10111010110, (outs VECREG:$rT),
3828 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3829 "dfms\t$rT, $rA, $rB", DPrecFP,
3830 [(set (v2f64 VECREG:$rT),
3831 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3832 (v2f64 VECREG:$rC)))]>;
3834 // FNMS: - (a * b - c)
3835 // - (a * b) + c => c - (a * b)
3837 RRForm<0b01111010110, (outs R64FP:$rT),
3838 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3839 "dfnms\t$rT, $rA, $rB", DPrecFP,
3840 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3841 RegConstraint<"$rC = $rT">,
3844 def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
3845 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
3848 RRForm<0b01111010110, (outs VECREG:$rT),
3849 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3850 "dfnms\t$rT, $rA, $rB", DPrecFP,
3851 [(set (v2f64 VECREG:$rT),
3852 (fsub (v2f64 VECREG:$rC),
3853 (fmul (v2f64 VECREG:$rA),
3854 (v2f64 VECREG:$rB))))]>,
3855 RegConstraint<"$rC = $rT">,
3858 def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3859 (v2f64 VECREG:$rC))),
3860 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
3865 RRForm<0b11111010110, (outs R64FP:$rT),
3866 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3867 "dfnma\t$rT, $rA, $rB", DPrecFP,
3868 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
3869 RegConstraint<"$rC = $rT">,
3873 RRForm<0b11111010110, (outs VECREG:$rT),
3874 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3875 "dfnma\t$rT, $rA, $rB", DPrecFP,
3876 [(set (v2f64 VECREG:$rT),
3877 (fneg (fadd (v2f64 VECREG:$rC),
3878 (fmul (v2f64 VECREG:$rA),
3879 (v2f64 VECREG:$rB)))))]>,
3880 RegConstraint<"$rC = $rT">,
3883 //===----------------------------------------------------------------------==//
3884 // Floating point negation and absolute value
3885 //===----------------------------------------------------------------------==//
3887 def : Pat<(fneg (v4f32 VECREG:$rA)),
3888 (XORfnegvec (v4f32 VECREG:$rA),
3889 (v4f32 (ILHUv4i32 0x8000)))>;
3891 def : Pat<(fneg R32FP:$rA),
3892 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
3894 def : Pat<(fneg (v2f64 VECREG:$rA)),
3895 (XORfnegvec (v2f64 VECREG:$rA),
3896 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
3898 def : Pat<(fneg R64FP:$rA),
3899 (XORfneg64 R64FP:$rA,
3900 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
3902 // Floating point absolute value
3904 def : Pat<(fabs R32FP:$rA),
3905 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
3907 def : Pat<(fabs (v4f32 VECREG:$rA)),
3908 (ANDfabsvec (v4f32 VECREG:$rA),
3909 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3911 def : Pat<(fabs R64FP:$rA),
3912 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
3914 def : Pat<(fabs (v2f64 VECREG:$rA)),
3915 (ANDfabsvec (v2f64 VECREG:$rA),
3916 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3918 //===----------------------------------------------------------------------===//
3919 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
3920 // in the odd pipeline)
3921 //===----------------------------------------------------------------------===//
3923 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
3926 let Inst{0-10} = 0b10000000010;
3927 let Inst{11-17} = 0;
3928 let Inst{18-24} = 0;
3929 let Inst{25-31} = 0;
3932 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
3935 let Inst{0-10} = 0b10000000000;
3936 let Inst{11-17} = 0;
3937 let Inst{18-24} = 0;
3938 let Inst{25-31} = 0;
3941 //===----------------------------------------------------------------------===//
3942 // Bit conversions (type conversions between vector/packed types)
3943 // NOTE: Promotions are handled using the XS* instructions. Truncation
3945 //===----------------------------------------------------------------------===//
3946 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3947 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3948 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3949 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3950 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3952 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3953 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3954 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3955 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3956 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3958 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3959 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3960 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3961 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3962 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3964 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3965 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3966 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3967 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3968 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3970 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3971 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3972 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3973 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3974 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3976 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3977 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3978 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3979 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3980 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3982 def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3983 def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
3985 //===----------------------------------------------------------------------===//
3986 // Instruction patterns:
3987 //===----------------------------------------------------------------------===//
3989 // General 32-bit constants:
3990 def : Pat<(i32 imm:$imm),
3991 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3993 // Single precision float constants:
3994 def : Pat<(f32 fpimm:$imm),
3995 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3997 // General constant 32-bit vectors
3998 def : Pat<(v4i32 v4i32Imm:$imm),
3999 (IOHLv4i32 (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
4000 (LO16_vec v4i32Imm:$imm))>;
4003 def : Pat<(i8 imm:$imm),
4006 //===----------------------------------------------------------------------===//
4007 // Call instruction patterns:
4008 //===----------------------------------------------------------------------===//
4013 //===----------------------------------------------------------------------===//
4014 // Zero/Any/Sign extensions
4015 //===----------------------------------------------------------------------===//
4017 // zext 1->32: Zero extend i1 to i32
4018 def : Pat<(SPUextract_i1_zext R32C:$rSrc),
4019 (ANDIr32 R32C:$rSrc, 0x1)>;
4021 // sext 8->32: Sign extend bytes to words
4022 def : Pat<(sext_inreg R32C:$rSrc, i8),
4023 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
4025 def : Pat<(i32 (sext R8C:$rSrc)),
4026 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
4028 def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
4029 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
4030 (v4i32 VECREG:$rSrc))))>;
4032 // zext 8->16: Zero extend bytes to halfwords
4033 def : Pat<(i16 (zext R8C:$rSrc)),
4034 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
4036 // zext 8->32 from preferred slot in load/store
4037 def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
4038 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
4041 // zext 8->32: Zero extend bytes to words
4042 def : Pat<(i32 (zext R8C:$rSrc)),
4043 (ANDIi8i32 R8C:$rSrc, 0xff)>;
4045 // anyext 8->16: Extend 8->16 bits, irrespective of sign
4046 def : Pat<(i16 (anyext R8C:$rSrc)),
4047 (ORHIi8i16 R8C:$rSrc, 0)>;
4049 // anyext 8->32: Extend 8->32 bits, irrespective of sign
4050 def : Pat<(i32 (anyext R8C:$rSrc)),
4051 (ORIi8i32 R8C:$rSrc, 0)>;
4053 // zext 16->32: Zero extend halfwords to words
4054 def : Pat<(i32 (zext R16C:$rSrc)),
4055 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
4057 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
4058 (ANDIi16i32 R16C:$rSrc, 0xf)>;
4060 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
4061 (ANDIi16i32 R16C:$rSrc, 0xff)>;
4063 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
4064 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
4066 // anyext 16->32: Extend 16->32 bits, irrespective of sign
4067 def : Pat<(i32 (anyext R16C:$rSrc)),
4068 (ORIi16i32 R16C:$rSrc, 0)>;
4070 //===----------------------------------------------------------------------===//
4071 // Address generation: SPU, like PPC, has to split addresses into high and
4072 // low parts in order to load them into a register.
4073 //===----------------------------------------------------------------------===//
4075 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
4076 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
4077 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
4078 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
4080 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
4081 (SPUlo tglobaladdr:$in, 0)),
4082 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4084 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
4085 (SPUlo texternalsym:$in, 0)),
4086 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4088 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
4089 (SPUlo tjumptable:$in, 0)),
4090 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4092 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
4093 (SPUlo tconstpool:$in, 0)),
4094 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4096 def : Pat<(SPUindirect R32C:$sp, i32ImmSExt10:$imm),
4097 (AIr32 R32C:$sp, i32ImmSExt10:$imm)>;
4099 def : Pat<(SPUindirect R32C:$sp, imm:$imm),
4101 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm)))>;
4103 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
4104 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4106 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
4107 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4109 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
4110 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4112 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
4113 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4116 include "CellSDKIntrinsics.td"