1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
10 // Cell SPU Instructions:
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // TODO Items (not urgent today, but would be nice, low priority)
16 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
17 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
18 // in 16-bit and 32-bit constants and reduce instruction count.
19 //===----------------------------------------------------------------------===//
21 //===----------------------------------------------------------------------===//
22 // Pseudo instructions:
23 //===----------------------------------------------------------------------===//
25 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
26 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
27 "${:comment} ADJCALLSTACKDOWN",
28 [(callseq_start imm:$amt)]>;
29 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
30 "${:comment} ADJCALLSTACKUP",
31 [(callseq_end imm:$amt)]>;
34 //===----------------------------------------------------------------------===//
35 // DWARF debugging Pseudo Instructions
36 //===----------------------------------------------------------------------===//
38 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
39 "${:comment} .loc $file, $line, $col",
40 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
43 //===----------------------------------------------------------------------===//
45 // NB: The ordering is actually important, since the instruction selection
46 // will try each of the instructions in sequence, i.e., the D-form first with
47 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
48 // finally the X-form with the register-register.
49 //===----------------------------------------------------------------------===//
53 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
54 "lqd\t$rT, $src", LoadStore,
55 [(set (v16i8 VECREG:$rT), (load dform_addr:$src))]>;
58 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
59 "lqd\t$rT, $src", LoadStore,
60 [(set (v8i16 VECREG:$rT), (load dform_addr:$src))]>;
63 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
64 "lqd\t$rT, $src", LoadStore,
65 [(set (v4i32 VECREG:$rT), (load dform_addr:$src))]>;
68 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
69 "lqd\t$rT, $src", LoadStore,
70 [(set (v2i64 VECREG:$rT), (load dform_addr:$src))]>;
73 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
74 "lqd\t$rT, $src", LoadStore,
75 [(set (v4f32 VECREG:$rT), (load dform_addr:$src))]>;
78 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
79 "lqd\t$rT, $src", LoadStore,
80 [(set (v2f64 VECREG:$rT), (load dform_addr:$src))]>;
83 RI10Form<0b00101100, (outs GPRC:$rT), (ins memri10:$src),
84 "lqd\t$rT, $src", LoadStore,
85 [(set GPRC:$rT, (load dform_addr:$src))]>;
88 RI10Form<0b00101100, (outs R64C:$rT), (ins memri10:$src),
89 "lqd\t$rT, $src", LoadStore,
90 [(set R64C:$rT, (load dform_addr:$src))]>;
93 RI10Form<0b00101100, (outs R32C:$rT), (ins memri10:$src),
94 "lqd\t$rT, $src", LoadStore,
95 [(set R32C:$rT, (load dform_addr:$src))]>;
99 RI10Form<0b00101100, (outs R32FP:$rT), (ins memri10:$src),
100 "lqd\t$rT, $src", LoadStore,
101 [(set R32FP:$rT, (load dform_addr:$src))]>;
104 RI10Form<0b00101100, (outs R64FP:$rT), (ins memri10:$src),
105 "lqd\t$rT, $src", LoadStore,
106 [(set R64FP:$rT, (load dform_addr:$src))]>;
107 // END Floating Point
110 RI10Form<0b00101100, (outs R16C:$rT), (ins memri10:$src),
111 "lqd\t$rT, $src", LoadStore,
112 [(set R16C:$rT, (load dform_addr:$src))]>;
115 RI10Form<0b00101100, (outs R8C:$rT), (ins memri10:$src),
116 "lqd\t$rT, $src", LoadStore,
117 [(set R8C:$rT, (load dform_addr:$src))]>;
120 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
121 "lqa\t$rT, $src", LoadStore,
122 [(set (v16i8 VECREG:$rT), (load aform_addr:$src))]>;
125 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
126 "lqa\t$rT, $src", LoadStore,
127 [(set (v8i16 VECREG:$rT), (load aform_addr:$src))]>;
130 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
131 "lqa\t$rT, $src", LoadStore,
132 [(set (v4i32 VECREG:$rT), (load aform_addr:$src))]>;
135 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
136 "lqa\t$rT, $src", LoadStore,
137 [(set (v2i64 VECREG:$rT), (load aform_addr:$src))]>;
140 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
141 "lqa\t$rT, $src", LoadStore,
142 [(set (v4f32 VECREG:$rT), (load aform_addr:$src))]>;
145 RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
146 "lqa\t$rT, $src", LoadStore,
147 [(set (v2f64 VECREG:$rT), (load aform_addr:$src))]>;
150 RI16Form<0b100001100, (outs GPRC:$rT), (ins addr256k:$src),
151 "lqa\t$rT, $src", LoadStore,
152 [(set GPRC:$rT, (load aform_addr:$src))]>;
155 RI16Form<0b100001100, (outs R64C:$rT), (ins addr256k:$src),
156 "lqa\t$rT, $src", LoadStore,
157 [(set R64C:$rT, (load aform_addr:$src))]>;
160 RI16Form<0b100001100, (outs R32C:$rT), (ins addr256k:$src),
161 "lqa\t$rT, $src", LoadStore,
162 [(set R32C:$rT, (load aform_addr:$src))]>;
165 RI16Form<0b100001100, (outs R32FP:$rT), (ins addr256k:$src),
166 "lqa\t$rT, $src", LoadStore,
167 [(set R32FP:$rT, (load aform_addr:$src))]>;
170 RI16Form<0b100001100, (outs R64FP:$rT), (ins addr256k:$src),
171 "lqa\t$rT, $src", LoadStore,
172 [(set R64FP:$rT, (load aform_addr:$src))]>;
175 RI16Form<0b100001100, (outs R16C:$rT), (ins addr256k:$src),
176 "lqa\t$rT, $src", LoadStore,
177 [(set R16C:$rT, (load aform_addr:$src))]>;
180 RI16Form<0b100001100, (outs R8C:$rT), (ins addr256k:$src),
181 "lqa\t$rT, $src", LoadStore,
182 [(set R8C:$rT, (load aform_addr:$src))]>;
185 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
186 "lqx\t$rT, $src", LoadStore,
187 [(set (v16i8 VECREG:$rT), (load xform_addr:$src))]>;
190 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
191 "lqx\t$rT, $src", LoadStore,
192 [(set (v8i16 VECREG:$rT), (load xform_addr:$src))]>;
195 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
196 "lqx\t$rT, $src", LoadStore,
197 [(set (v4i32 VECREG:$rT), (load xform_addr:$src))]>;
200 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
201 "lqx\t$rT, $src", LoadStore,
202 [(set (v2i64 VECREG:$rT), (load xform_addr:$src))]>;
205 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
206 "lqx\t$rT, $src", LoadStore,
207 [(set (v4f32 VECREG:$rT), (load xform_addr:$src))]>;
210 RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
211 "lqx\t$rT, $src", LoadStore,
212 [(set (v2f64 VECREG:$rT), (load xform_addr:$src))]>;
215 RRForm<0b00100011100, (outs GPRC:$rT), (ins memrr:$src),
216 "lqx\t$rT, $src", LoadStore,
217 [(set GPRC:$rT, (load xform_addr:$src))]>;
220 RRForm<0b00100011100, (outs R64C:$rT), (ins memrr:$src),
221 "lqx\t$rT, $src", LoadStore,
222 [(set R64C:$rT, (load xform_addr:$src))]>;
225 RRForm<0b00100011100, (outs R32C:$rT), (ins memrr:$src),
226 "lqx\t$rT, $src", LoadStore,
227 [(set R32C:$rT, (load xform_addr:$src))]>;
230 RRForm<0b00100011100, (outs R32FP:$rT), (ins memrr:$src),
231 "lqx\t$rT, $src", LoadStore,
232 [(set R32FP:$rT, (load xform_addr:$src))]>;
235 RRForm<0b00100011100, (outs R64FP:$rT), (ins memrr:$src),
236 "lqx\t$rT, $src", LoadStore,
237 [(set R64FP:$rT, (load xform_addr:$src))]>;
240 RRForm<0b00100011100, (outs R16C:$rT), (ins memrr:$src),
241 "lqx\t$rT, $src", LoadStore,
242 [(set R16C:$rT, (load xform_addr:$src))]>;
245 RRForm<0b00100011100, (outs R8C:$rT), (ins memrr:$src),
246 "lqx\t$rT, $src", LoadStore,
247 [(set R8C:$rT, (load xform_addr:$src))]>;
249 /* Load quadword, PC relative: Not much use at this point in time.
250 Might be of use later for relocatable code.
251 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
252 "lqr\t$rT, $disp", LoadStore,
253 [(set VECREG:$rT, (load iaddr:$disp))]>;
257 //===----------------------------------------------------------------------===//
259 //===----------------------------------------------------------------------===//
262 def STQDv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
263 "stqd\t$rT, $src", LoadStore,
264 [(store (v16i8 VECREG:$rT), dform_addr:$src)]>;
266 def STQDv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
267 "stqd\t$rT, $src", LoadStore,
268 [(store (v8i16 VECREG:$rT), dform_addr:$src)]>;
270 def STQDv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
271 "stqd\t$rT, $src", LoadStore,
272 [(store (v4i32 VECREG:$rT), dform_addr:$src)]>;
274 def STQDv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
275 "stqd\t$rT, $src", LoadStore,
276 [(store (v2i64 VECREG:$rT), dform_addr:$src)]>;
278 def STQDv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
279 "stqd\t$rT, $src", LoadStore,
280 [(store (v4f32 VECREG:$rT), dform_addr:$src)]>;
282 def STQDv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
283 "stqd\t$rT, $src", LoadStore,
284 [(store (v2f64 VECREG:$rT), dform_addr:$src)]>;
286 def STQDr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memri10:$src),
287 "stqd\t$rT, $src", LoadStore,
288 [(store GPRC:$rT, dform_addr:$src)]>;
290 def STQDr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, memri10:$src),
291 "stqd\t$rT, $src", LoadStore,
292 [(store R64C:$rT, dform_addr:$src)]>;
294 def STQDr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, memri10:$src),
295 "stqd\t$rT, $src", LoadStore,
296 [(store R32C:$rT, dform_addr:$src)]>;
299 def STQDf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, memri10:$src),
300 "stqd\t$rT, $src", LoadStore,
301 [(store R32FP:$rT, dform_addr:$src)]>;
303 def STQDf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, memri10:$src),
304 "stqd\t$rT, $src", LoadStore,
305 [(store R64FP:$rT, dform_addr:$src)]>;
307 def STQDr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, memri10:$src),
308 "stqd\t$rT, $src", LoadStore,
309 [(store R16C:$rT, dform_addr:$src)]>;
311 def STQDr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, memri10:$src),
312 "stqd\t$rT, $src", LoadStore,
313 [(store R8C:$rT, dform_addr:$src)]>;
315 def STQAv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
316 "stqa\t$rT, $src", LoadStore,
317 [(store (v16i8 VECREG:$rT), aform_addr:$src)]>;
319 def STQAv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
320 "stqa\t$rT, $src", LoadStore,
321 [(store (v8i16 VECREG:$rT), aform_addr:$src)]>;
323 def STQAv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
324 "stqa\t$rT, $src", LoadStore,
325 [(store (v4i32 VECREG:$rT), aform_addr:$src)]>;
327 def STQAv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
328 "stqa\t$rT, $src", LoadStore,
329 [(store (v2i64 VECREG:$rT), aform_addr:$src)]>;
331 def STQAv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
332 "stqa\t$rT, $src", LoadStore,
333 [(store (v4f32 VECREG:$rT), aform_addr:$src)]>;
335 def STQAv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, addr256k:$src),
336 "stqa\t$rT, $src", LoadStore,
337 [(store (v2f64 VECREG:$rT), aform_addr:$src)]>;
339 def STQAr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, addr256k:$src),
340 "stqa\t$rT, $src", LoadStore,
341 [(store GPRC:$rT, aform_addr:$src)]>;
343 def STQAr64 : RI10Form<0b00100100, (outs), (ins R64C:$rT, addr256k:$src),
344 "stqa\t$rT, $src", LoadStore,
345 [(store R64C:$rT, aform_addr:$src)]>;
347 def STQAr32 : RI10Form<0b00100100, (outs), (ins R32C:$rT, addr256k:$src),
348 "stqa\t$rT, $src", LoadStore,
349 [(store R32C:$rT, aform_addr:$src)]>;
352 def STQAf32 : RI10Form<0b00100100, (outs), (ins R32FP:$rT, addr256k:$src),
353 "stqa\t$rT, $src", LoadStore,
354 [(store R32FP:$rT, aform_addr:$src)]>;
356 def STQAf64 : RI10Form<0b00100100, (outs), (ins R64FP:$rT, addr256k:$src),
357 "stqa\t$rT, $src", LoadStore,
358 [(store R64FP:$rT, aform_addr:$src)]>;
360 def STQAr16 : RI10Form<0b00100100, (outs), (ins R16C:$rT, addr256k:$src),
361 "stqa\t$rT, $src", LoadStore,
362 [(store R16C:$rT, aform_addr:$src)]>;
364 def STQAr8 : RI10Form<0b00100100, (outs), (ins R8C:$rT, addr256k:$src),
365 "stqa\t$rT, $src", LoadStore,
366 [(store R8C:$rT, aform_addr:$src)]>;
368 def STQXv16i8 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
369 "stqx\t$rT, $src", LoadStore,
370 [(store (v16i8 VECREG:$rT), xform_addr:$src)]>;
372 def STQXv8i16 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
373 "stqx\t$rT, $src", LoadStore,
374 [(store (v8i16 VECREG:$rT), xform_addr:$src)]>;
376 def STQXv4i32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
377 "stqx\t$rT, $src", LoadStore,
378 [(store (v4i32 VECREG:$rT), xform_addr:$src)]>;
380 def STQXv2i64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
381 "stqx\t$rT, $src", LoadStore,
382 [(store (v2i64 VECREG:$rT), xform_addr:$src)]>;
384 def STQXv4f32 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
385 "stqx\t$rT, $src", LoadStore,
386 [(store (v4f32 VECREG:$rT), xform_addr:$src)]>;
388 def STQXv2f64 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
389 "stqx\t$rT, $src", LoadStore,
390 [(store (v2f64 VECREG:$rT), xform_addr:$src)]>;
392 def STQXr128 : RI10Form<0b00100100, (outs), (ins GPRC:$rT, memrr:$src),
393 "stqx\t$rT, $src", LoadStore,
394 [(store GPRC:$rT, xform_addr:$src)]>;
397 RI10Form<0b00100100, (outs), (ins R64C:$rT, memrr:$src),
398 "stqx\t$rT, $src", LoadStore,
399 [(store R64C:$rT, xform_addr:$src)]>;
402 RI10Form<0b00100100, (outs), (ins R32C:$rT, memrr:$src),
403 "stqx\t$rT, $src", LoadStore,
404 [(store R32C:$rT, xform_addr:$src)]>;
408 RI10Form<0b00100100, (outs), (ins R32FP:$rT, memrr:$src),
409 "stqx\t$rT, $src", LoadStore,
410 [(store R32FP:$rT, xform_addr:$src)]>;
413 RI10Form<0b00100100, (outs), (ins R64FP:$rT, memrr:$src),
414 "stqx\t$rT, $src", LoadStore,
415 [(store R64FP:$rT, xform_addr:$src)]>;
418 RI10Form<0b00100100, (outs), (ins R16C:$rT, memrr:$src),
419 "stqx\t$rT, $src", LoadStore,
420 [(store R16C:$rT, xform_addr:$src)]>;
423 RI10Form<0b00100100, (outs), (ins R8C:$rT, memrr:$src),
424 "stqx\t$rT, $src", LoadStore,
425 [(store R8C:$rT, xform_addr:$src)]>;
427 /* Store quadword, PC relative: Not much use at this point in time. Might
428 be useful for relocatable code.
429 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
430 "stqr\t$rT, $disp", LoadStore,
431 [(store VECREG:$rT, iaddr:$disp)]>;
435 //===----------------------------------------------------------------------===//
436 // Generate Controls for Insertion:
437 //===----------------------------------------------------------------------===//
440 RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
441 "cbd\t$rT, $src", ShuffleOp,
442 [(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
444 def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
445 "cbx\t$rT, $src", ShuffleOp,
446 [(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
448 def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
449 "chd\t$rT, $src", ShuffleOp,
450 [(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
452 def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
453 "chx\t$rT, $src", ShuffleOp,
454 [(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
456 def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
457 "cwd\t$rT, $src", ShuffleOp,
458 [(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
460 def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
461 "cwx\t$rT, $src", ShuffleOp,
462 [(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
464 def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
465 "cdd\t$rT, $src", ShuffleOp,
466 [(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
468 def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
469 "cdx\t$rT, $src", ShuffleOp,
470 [(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
472 //===----------------------------------------------------------------------===//
473 // Constant formation:
474 //===----------------------------------------------------------------------===//
477 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
478 "ilh\t$rT, $val", ImmLoad,
479 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
482 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
483 "ilh\t$rT, $val", ImmLoad,
484 [(set R16C:$rT, immSExt16:$val)]>;
486 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
487 // the right constant")
489 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
490 "ilh\t$rT, $val", ImmLoad,
491 [(set R8C:$rT, immSExt8:$val)]>;
493 // IL does sign extension!
495 RI16Form<0b100000010, (outs R64C:$rT), (ins s16imm_i64:$val),
496 "il\t$rT, $val", ImmLoad,
497 [(set R64C:$rT, immSExt16:$val)]>;
500 RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm_i64:$val),
501 "il\t$rT, $val", ImmLoad,
502 [(set VECREG:$rT, (v2i64 v2i64SExt16Imm:$val))]>;
505 RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm:$val),
506 "il\t$rT, $val", ImmLoad,
507 [(set VECREG:$rT, (v4i32 v4i32SExt16Imm:$val))]>;
510 RI16Form<0b100000010, (outs R32C:$rT), (ins s16imm_i32:$val),
511 "il\t$rT, $val", ImmLoad,
512 [(set R32C:$rT, immSExt16:$val)]>;
515 RI16Form<0b100000010, (outs R32FP:$rT), (ins s16imm_f32:$val),
516 "il\t$rT, $val", ImmLoad,
517 [(set R32FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>;
520 RI16Form<0b100000010, (outs R64FP:$rT), (ins s16imm_f64:$val),
521 "il\t$rT, $val", ImmLoad,
522 [(set R64FP:$rT, (SPUFPconstant fpimmSExt16:$val))]>;
525 RI16Form<0b010000010, (outs VECREG:$rT), (ins u16imm:$val),
526 "ilhu\t$rT, $val", ImmLoad,
527 [(set VECREG:$rT, (v4i32 immILHUvec:$val))]>;
530 RI16Form<0b010000010, (outs R32C:$rT), (ins u16imm:$val),
531 "ilhu\t$rT, $val", ImmLoad,
532 [(set R32C:$rT, hi16:$val)]>;
534 // ILHUf32: Used to custom lower float constant loads
536 RI16Form<0b010000010, (outs R32FP:$rT), (ins f16imm:$val),
537 "ilhu\t$rT, $val", ImmLoad,
538 [(set R32FP:$rT, (SPUFPconstant hi16_f32:$val))]>;
540 // ILHUhi: Used for loading high portion of an address. Note the symbolHi
541 // printer used for the operand.
542 def ILHUhi : RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val),
543 "ilhu\t$rT, $val", ImmLoad,
544 [(set R32C:$rT, hi16:$val)]>;
546 // Immediate load address (can also be used to load 18-bit unsigned constants,
547 // see the zext 16->32 pattern)
549 RI18Form<0b1000010, (outs R64C:$rT), (ins u18imm_i64:$val),
550 "ila\t$rT, $val", LoadNOP,
551 [(set R64C:$rT, imm18:$val)]>;
556 RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val),
557 "ila\t$rT, $val", LoadNOP,
558 [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>;
561 RI18Form<0b1000010, (outs VECREG:$rT), (ins u18imm:$val),
562 "ila\t$rT, $val", LoadNOP,
563 [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>;
566 RI18Form<0b1000010, (outs R32C:$rT), (ins u18imm:$val),
567 "ila\t$rT, $val", LoadNOP,
568 [(set R32C:$rT, imm18:$val)]>;
571 RI18Form<0b1000010, (outs R32FP:$rT), (ins f18imm:$val),
572 "ila\t$rT, $val", LoadNOP,
573 [(set R32FP:$rT, (SPUFPconstant fpimm18:$val))]>;
576 RI18Form<0b1000010, (outs R64FP:$rT), (ins f18imm_f64:$val),
577 "ila\t$rT, $val", LoadNOP,
578 [(set R64FP:$rT, (SPUFPconstant fpimm18:$val))]>;
581 RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLo:$val),
582 "ila\t$rT, $val", ImmLoad,
583 [(set R32C:$rT, imm18:$val)]>;
586 RI18Form<0b1000010, (outs R32C:$rT), (ins symbolLSA:$val),
587 "ila\t$rT, $val", ImmLoad,
590 // Immediate OR, Halfword Lower: The "other" part of loading large constants
591 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
592 // Note that these are really two operand instructions, but they're encoded
593 // as three operands with the first two arguments tied-to each other.
596 RI16Form<0b100000110, (outs VECREG:$rT), (ins VECREG:$rS, u16imm:$val),
597 "iohl\t$rT, $val", ImmLoad,
598 [/* insert intrinsic here */]>,
599 RegConstraint<"$rS = $rT">,
603 RI16Form<0b100000110, (outs R32C:$rT), (ins R32C:$rS, i32imm:$val),
604 "iohl\t$rT, $val", ImmLoad,
605 [/* insert intrinsic here */]>,
606 RegConstraint<"$rS = $rT">,
610 RI16Form<0b100000110, (outs R32FP:$rT), (ins R32FP:$rS, f32imm:$val),
611 "iohl\t$rT, $val", ImmLoad,
612 [/* insert intrinsic here */]>,
613 RegConstraint<"$rS = $rT">,
616 // Form select mask for bytes using immediate, used in conjunction with the
619 def FSMBIv16i8 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
620 "fsmbi\t$rT, $val", SelectOp,
621 [(set (v16i8 VECREG:$rT), (SPUfsmbi_v16i8 immU16:$val))]>;
623 def FSMBIv8i16 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
624 "fsmbi\t$rT, $val", SelectOp,
625 [(set (v8i16 VECREG:$rT), (SPUfsmbi_v8i16 immU16:$val))]>;
627 def FSMBIvecv4i32 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
628 "fsmbi\t$rT, $val", SelectOp,
629 [(set (v4i32 VECREG:$rT), (SPUfsmbi_v4i32 immU16:$val))]>;
631 //===----------------------------------------------------------------------===//
632 // Integer and Logical Operations:
633 //===----------------------------------------------------------------------===//
636 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
637 "ah\t$rT, $rA, $rB", IntegerOp,
638 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
640 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
641 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
643 // [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
646 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
647 "ah\t$rT, $rA, $rB", IntegerOp,
648 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
651 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
652 "ahi\t$rT, $rA, $val", IntegerOp,
653 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
654 v8i16SExt10Imm:$val))]>;
656 def AHIr16 : RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
657 "ahi\t$rT, $rA, $val", IntegerOp,
658 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
660 def Avec : RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
661 "a\t$rT, $rA, $rB", IntegerOp,
662 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
664 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
665 (Avec VECREG:$rA, VECREG:$rB)>;
667 def Ar32 : RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
668 "a\t$rT, $rA, $rB", IntegerOp,
669 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
672 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
673 "a\t$rT, $rA, $rB", IntegerOp,
674 [(set R8C:$rT, (add R8C:$rA, R8C:$rB))]>;
677 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
678 "ai\t$rT, $rA, $val", IntegerOp,
679 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
680 v4i32SExt10Imm:$val))]>;
683 RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
684 "ai\t$rT, $rA, $val", IntegerOp,
685 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
688 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
689 "sfh\t$rT, $rA, $rB", IntegerOp,
690 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
691 (v8i16 VECREG:$rB)))]>;
694 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
695 "sfh\t$rT, $rA, $rB", IntegerOp,
696 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
699 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
700 "sfhi\t$rT, $rA, $val", IntegerOp,
701 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
702 (v8i16 VECREG:$rA)))]>;
704 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
705 "sfhi\t$rT, $rA, $val", IntegerOp,
706 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
708 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
709 (ins VECREG:$rA, VECREG:$rB),
710 "sf\t$rT, $rA, $rB", IntegerOp,
711 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
713 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
714 "sf\t$rT, $rA, $rB", IntegerOp,
715 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
718 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
719 "sfi\t$rT, $rA, $val", IntegerOp,
720 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
721 (v4i32 VECREG:$rA)))]>;
723 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
724 (ins R32C:$rA, s10imm_i32:$val),
725 "sfi\t$rT, $rA, $val", IntegerOp,
726 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
728 // ADDX: only available in vector form, doesn't match a pattern.
730 RRForm<0b00000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
732 "addx\t$rT, $rA, $rB", IntegerOp,
734 RegConstraint<"$rCarry = $rT">,
737 // CG: only available in vector form, doesn't match a pattern.
739 RRForm<0b01000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
741 "cg\t$rT, $rA, $rB", IntegerOp,
743 RegConstraint<"$rCarry = $rT">,
746 // SFX: only available in vector form, doesn't match a pattern
748 RRForm<0b10000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
750 "sfx\t$rT, $rA, $rB", IntegerOp,
752 RegConstraint<"$rCarry = $rT">,
755 // BG: only available in vector form, doesn't match a pattern.
757 RRForm<0b01000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
759 "bg\t$rT, $rA, $rB", IntegerOp,
761 RegConstraint<"$rCarry = $rT">,
764 // BGX: only available in vector form, doesn't match a pattern.
766 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
768 "bgx\t$rT, $rA, $rB", IntegerOp,
770 RegConstraint<"$rCarry = $rT">,
773 // Halfword multiply variants:
774 // N.B: These can be used to build up larger quantities (16x16 -> 32)
777 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
778 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
779 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
780 (v8i16 VECREG:$rB)))]>;
783 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
784 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
785 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
788 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
789 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
790 [(set (v4i32 VECREG:$rT),
791 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
794 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
795 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
796 [(set R32C:$rT, (mul (zext R16C:$rA),
800 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
801 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
802 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
804 // mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
805 // this only produces the lower 16 bits)
807 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
808 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
809 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
812 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
813 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
814 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
816 // mpyui: same issues as other multiplies, plus, this doesn't match a
817 // pattern... but may be used during target DAG selection or lowering
819 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
820 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
824 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
825 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
828 // mpya: 16 x 16 + 16 -> 32 bit result
830 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
831 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
832 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
833 (v8i16 VECREG:$rB)))),
834 (v4i32 VECREG:$rC)))]>;
837 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
838 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
839 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
842 def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
843 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
845 def MPYAr32_sextinreg:
846 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
847 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
848 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
849 (sext_inreg R32C:$rB, i16)),
853 // RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
854 // "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
855 // [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
858 // mpyh: multiply high, used to synthesize 32-bit multiplies
860 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
861 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
862 [(set (v4i32 VECREG:$rT),
863 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
866 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
867 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
868 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
870 // mpys: multiply high and shift right (returns the top half of
871 // a 16-bit multiply, sign extended to 32 bits.)
873 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
874 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
878 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
879 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
882 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
883 // the top 16 bits of the $rA, $rB)
885 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
886 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
887 [(set (v8i16 VECREG:$rT),
888 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
891 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
892 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
895 // mpyhha: Multiply high-high, add to $rT:
897 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
898 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
902 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
903 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
906 // mpyhhu: Multiply high-high, unsigned
908 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
909 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
913 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
914 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
917 // mpyhhau: Multiply high-high, unsigned
919 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
920 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
924 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
925 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
928 // clz: Count leading zeroes
930 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
931 "clz\t$rT, $rA", IntegerOp,
935 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
936 "clz\t$rT, $rA", IntegerOp,
937 [(set R32C:$rT, (ctlz R32C:$rA))]>;
939 // cntb: Count ones in bytes (aka "population count")
940 // NOTE: This instruction is really a vector instruction, but the custom
941 // lowering code uses it in unorthodox ways to support CTPOP for other
944 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
945 "cntb\t$rT, $rA", IntegerOp,
946 [(set (v16i8 VECREG:$rT), (SPUcntb_v16i8 (v16i8 VECREG:$rA)))]>;
949 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
950 "cntb\t$rT, $rA", IntegerOp,
951 [(set (v8i16 VECREG:$rT), (SPUcntb_v8i16 (v8i16 VECREG:$rA)))]>;
954 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
955 "cntb\t$rT, $rA", IntegerOp,
956 [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>;
958 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
960 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
961 "fsmb\t$rT, $rA", SelectOp,
964 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
965 // only 8-bits wide (even though it's input as 16-bits here)
967 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
968 "fsmh\t$rT, $rA", SelectOp,
971 // fsm: Form select mask for words. Like the other fsm* instructions,
972 // only the lower 4 bits of $rA are significant.
974 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA),
975 "fsm\t$rT, $rA", SelectOp,
978 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
979 // quantity stored into $rT
981 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
982 "gbb\t$rT, $rA", GatherOp,
985 // gbh: Gather all low order bits from each halfword in $rA into a single
986 // 8-bit quantity stored in $rT
988 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
989 "gbh\t$rT, $rA", GatherOp,
992 // gb: Gather all low order bits from each word in $rA into a single
993 // 4-bit quantity stored in $rT
995 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
996 "gb\t$rT, $rA", GatherOp,
999 // avgb: average bytes
1001 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1002 "avgb\t$rT, $rA, $rB", ByteOp,
1005 // absdb: absolute difference of bytes
1007 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1008 "absdb\t$rT, $rA, $rB", ByteOp,
1011 // sumb: sum bytes into halfwords
1013 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1014 "sumb\t$rT, $rA, $rB", ByteOp,
1017 // Sign extension operations:
1019 RRForm_1<0b01101101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
1020 "xsbh\t$rDst, $rSrc", IntegerOp,
1021 [(set (v8i16 VECREG:$rDst), (sext (v16i8 VECREG:$rSrc)))]>;
1023 // Ordinary form for XSBH
1025 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R16C:$rSrc),
1026 "xsbh\t$rDst, $rSrc", IntegerOp,
1027 [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>;
1030 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R8C:$rSrc),
1031 "xsbh\t$rDst, $rSrc", IntegerOp,
1032 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
1034 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
1035 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
1036 // pattern below). Intentionally doesn't match a pattern because we want the
1037 // sext 8->32 pattern to do the work for us, namely because we need the extra
1040 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
1041 "xsbh\t$rDst, $rSrc", IntegerOp,
1042 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i8))]>;
1044 // Sign extend halfwords to words:
1046 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
1047 "xshw\t$rDest, $rSrc", IntegerOp,
1048 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
1051 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
1052 "xshw\t$rDst, $rSrc", IntegerOp,
1053 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
1056 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
1057 "xshw\t$rDst, $rSrc", IntegerOp,
1058 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
1061 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
1062 "xswd\t$rDst, $rSrc", IntegerOp,
1063 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
1066 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
1067 "xswd\t$rDst, $rSrc", IntegerOp,
1068 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
1071 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
1072 "xswd\t$rDst, $rSrc", IntegerOp,
1073 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
1075 def : Pat<(sext R32C:$inp),
1076 (XSWDr32 R32C:$inp)>;
1080 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1081 "and\t$rT, $rA, $rB", IntegerOp,
1082 [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA),
1083 (v16i8 VECREG:$rB)))]>;
1086 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1087 "and\t$rT, $rA, $rB", IntegerOp,
1088 [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA),
1089 (v8i16 VECREG:$rB)))]>;
1092 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1093 "and\t$rT, $rA, $rB", IntegerOp,
1094 [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA),
1095 (v4i32 VECREG:$rB)))]>;
1098 RRForm<0b10000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1099 "and\t$rT, $rA, $rB", IntegerOp,
1100 [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>;
1102 //===---------------------------------------------
1103 // Special instructions to perform the fabs instruction
1105 RRForm<0b10000011000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1106 "and\t$rT, $rA, $rB", IntegerOp,
1107 [/* Intentionally does not match a pattern */]>;
1110 RRForm<0b10000011000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1111 "and\t$rT, $rA, $rB", IntegerOp,
1112 [/* Intentionally does not match a pattern */]>;
1114 // Could use ANDv4i32, but won't for clarity
1116 RRForm<0b10000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1117 "and\t$rT, $rA, $rB", IntegerOp,
1118 [/* Intentionally does not match a pattern */]>;
1120 //===---------------------------------------------
1123 RRForm<0b10000011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1124 "and\t$rT, $rA, $rB", IntegerOp,
1125 [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>;
1128 RRForm<0b10000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1129 "and\t$rT, $rA, $rB", IntegerOp,
1130 [(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>;
1132 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
1133 // quantities -- see 16->32 zext pattern.
1135 // This pattern is somewhat artificial, since it might match some
1136 // compiler generated pattern but it is unlikely to do so.
1138 RRForm<0b10000011000, (outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
1139 "and\t$rT, $rA, $rB", IntegerOp,
1140 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
1142 // N.B.: vnot_conv is one of those special target selection pattern fragments,
1143 // in which we expect there to be a bit_convert on the constant. Bear in mind
1144 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
1145 // constant -1 vector.)
1147 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1148 "andc\t$rT, $rA, $rB", IntegerOp,
1149 [(set (v16i8 VECREG:$rT), (and (v16i8 VECREG:$rA),
1150 (vnot (v16i8 VECREG:$rB))))]>;
1153 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1154 "andc\t$rT, $rA, $rB", IntegerOp,
1155 [(set (v8i16 VECREG:$rT), (and (v8i16 VECREG:$rA),
1156 (vnot (v8i16 VECREG:$rB))))]>;
1159 RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1160 "andc\t$rT, $rA, $rB", IntegerOp,
1161 [(set (v4i32 VECREG:$rT), (and (v4i32 VECREG:$rA),
1162 (vnot (v4i32 VECREG:$rB))))]>;
1165 RRForm<0b10000011010, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1166 "andc\t$rT, $rA, $rB", IntegerOp,
1167 [(set R32C:$rT, (and R32C:$rA, (not R32C:$rB)))]>;
1170 RRForm<0b10000011010, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1171 "andc\t$rT, $rA, $rB", IntegerOp,
1172 [(set R16C:$rT, (and R16C:$rA, (not R16C:$rB)))]>;
1175 RRForm<0b10000011010, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1176 "andc\t$rT, $rA, $rB", IntegerOp,
1177 [(set R8C:$rT, (and R8C:$rA, (not R8C:$rB)))]>;
1180 RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1181 "andbi\t$rT, $rA, $val", IntegerOp,
1182 [(set (v16i8 VECREG:$rT),
1183 (and (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>;
1186 RI10Form<0b01101000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1187 "andbi\t$rT, $rA, $val", IntegerOp,
1188 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1191 RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1192 "andhi\t$rT, $rA, $val", IntegerOp,
1193 [(set (v8i16 VECREG:$rT),
1194 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1197 RI10Form<0b10101000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1198 "andhi\t$rT, $rA, $val", IntegerOp,
1199 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1202 RI10Form<0b10101000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1203 "andhi\t$rT, $rA, $val", IntegerOp,
1204 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmSExt10:$val))]>;
1207 RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1208 "andi\t$rT, $rA, $val", IntegerOp,
1209 [(set (v4i32 VECREG:$rT),
1210 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1213 RI10Form<0b10101000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1214 "andi\t$rT, $rA, $val", IntegerOp,
1215 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1217 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1220 RI10Form<0b10101000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1221 "andi\t$rT, $rA, $val", IntegerOp,
1222 [(set R32C:$rT, (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1224 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1225 // zext 16->32 pattern below.
1227 // Note that this pattern is somewhat artificial, since it might match
1228 // something the compiler generates but is unlikely to occur in practice.
1230 RI10Form<0b10101000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1231 "andi\t$rT, $rA, $val", IntegerOp,
1232 [(set R32C:$rT, (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1234 // Bitwise OR group:
1235 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1237 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1238 "or\t$rT, $rA, $rB", IntegerOp,
1239 [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
1242 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1243 "or\t$rT, $rA, $rB", IntegerOp,
1244 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
1247 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1248 "or\t$rT, $rA, $rB", IntegerOp,
1249 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
1252 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1253 "or\t$rT, $rA, $rB", IntegerOp,
1254 [(set (v4f32 VECREG:$rT),
1255 (v4f32 (bitconvert (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))))]>;
1258 RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1259 "or\t$rT, $rA, $rB", IntegerOp,
1260 [(set (v2f64 VECREG:$rT),
1261 (v2f64 (bitconvert (or (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)))))]>;
1264 RRForm<0b10000010000, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
1265 "or\t$rT, $rA, $rB", IntegerOp,
1266 [(set GPRC:$rT, (or GPRC:$rA, GPRC:$rB))]>;
1269 RRForm<0b10000010000, (outs R64C:$rT), (ins R64C:$rA, R64C:$rB),
1270 "or\t$rT, $rA, $rB", IntegerOp,
1271 [(set R64C:$rT, (or R64C:$rA, R64C:$rB))]>;
1274 RRForm<0b10000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1275 "or\t$rT, $rA, $rB", IntegerOp,
1276 [(set R32C:$rT, (or R32C:$rA, R32C:$rB))]>;
1279 RRForm<0b10000010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1280 "or\t$rT, $rA, $rB", IntegerOp,
1281 [(set R16C:$rT, (or R16C:$rA, R16C:$rB))]>;
1284 RRForm<0b10000010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1285 "or\t$rT, $rA, $rB", IntegerOp,
1286 [(set R8C:$rT, (or R8C:$rA, R8C:$rB))]>;
1288 // ORv*_*: Used in scalar->vector promotions:
1290 RRForm<0b10000010000, (outs VECREG:$rT), (ins R8C:$rA, R8C:$rB),
1291 "or\t$rT, $rA, $rB", IntegerOp,
1292 [/* no pattern */]>;
1294 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
1295 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
1298 RRForm<0b10000010000, (outs VECREG:$rT), (ins R16C:$rA, R16C:$rB),
1299 "or\t$rT, $rA, $rB", IntegerOp,
1300 [/* no pattern */]>;
1302 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1303 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1306 RRForm<0b10000010000, (outs VECREG:$rT), (ins R32C:$rA, R32C:$rB),
1307 "or\t$rT, $rA, $rB", IntegerOp,
1308 [/* no pattern */]>;
1310 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1311 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1314 RRForm<0b10000010000, (outs VECREG:$rT), (ins R64C:$rA, R64C:$rB),
1315 "or\t$rT, $rA, $rB", IntegerOp,
1316 [/* no pattern */]>;
1318 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1319 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1322 RRForm<0b10000010000, (outs VECREG:$rT), (ins R32FP:$rA, R32FP:$rB),
1323 "or\t$rT, $rA, $rB", IntegerOp,
1324 [/* no pattern */]>;
1326 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1327 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1330 RRForm<0b10000010000, (outs VECREG:$rT), (ins R64FP:$rA, R64FP:$rB),
1331 "or\t$rT, $rA, $rB", IntegerOp,
1332 [/* no pattern */]>;
1334 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1335 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1337 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1339 RRForm<0b10000010000, (outs R8C:$rT), (ins VECREG:$rA, VECREG:$rB),
1340 "or\t$rT, $rA, $rB", IntegerOp,
1341 [/* no pattern */]>;
1343 def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)),
1344 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1347 RRForm<0b10000010000, (outs R16C:$rT), (ins VECREG:$rA, VECREG:$rB),
1348 "or\t$rT, $rA, $rB", IntegerOp,
1349 [/* no pattern */]>;
1351 def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
1352 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1354 def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
1355 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1358 RRForm<0b10000010000, (outs R32C:$rT), (ins VECREG:$rA, VECREG:$rB),
1359 "or\t$rT, $rA, $rB", IntegerOp,
1360 [/* no pattern */]>;
1362 def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
1363 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1365 def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
1366 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1369 RRForm<0b10000010000, (outs R64C:$rT), (ins VECREG:$rA, VECREG:$rB),
1370 "or\t$rT, $rA, $rB", IntegerOp,
1371 [/* no pattern */]>;
1373 def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
1374 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1376 def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
1377 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1380 RRForm<0b10000010000, (outs R32FP:$rT), (ins VECREG:$rA, VECREG:$rB),
1381 "or\t$rT, $rA, $rB", IntegerOp,
1382 [/* no pattern */]>;
1384 def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
1385 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1387 def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
1388 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1391 RRForm<0b10000010000, (outs R64FP:$rT), (ins VECREG:$rA, VECREG:$rB),
1392 "or\t$rT, $rA, $rB", IntegerOp,
1393 [/* no pattern */]>;
1395 def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
1396 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1398 def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
1399 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1401 // ORC: Bitwise "or" with complement (match before ORvec, ORr32)
1403 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1404 "orc\t$rT, $rA, $rB", IntegerOp,
1405 [(set (v16i8 VECREG:$rT), (or (v16i8 VECREG:$rA),
1406 (vnot (v16i8 VECREG:$rB))))]>;
1409 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1410 "orc\t$rT, $rA, $rB", IntegerOp,
1411 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA),
1412 (vnot (v8i16 VECREG:$rB))))]>;
1415 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1416 "orc\t$rT, $rA, $rB", IntegerOp,
1417 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA),
1418 (vnot (v4i32 VECREG:$rB))))]>;
1421 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1422 "orc\t$rT, $rA, $rB", IntegerOp,
1423 [(set R32C:$rT, (or R32C:$rA, (not R32C:$rB)))]>;
1426 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1427 "orc\t$rT, $rA, $rB", IntegerOp,
1428 [(set R16C:$rT, (or R16C:$rA, (not R16C:$rB)))]>;
1431 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1432 "orc\t$rT, $rA, $rB", IntegerOp,
1433 [(set R8C:$rT, (or R8C:$rA, (not R8C:$rB)))]>;
1435 // OR byte immediate
1437 RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1438 "orbi\t$rT, $rA, $val", IntegerOp,
1439 [(set (v16i8 VECREG:$rT),
1440 (or (v16i8 VECREG:$rA), (v16i8 v16i8U8Imm:$val)))]>;
1443 RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1444 "orbi\t$rT, $rA, $val", IntegerOp,
1445 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1447 // OR halfword immediate
1449 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1450 "orhi\t$rT, $rA, $val", IntegerOp,
1451 [(set (v8i16 VECREG:$rT), (or (v8i16 VECREG:$rA),
1452 v8i16Uns10Imm:$val))]>;
1455 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1456 "orhi\t$rT, $rA, $val", IntegerOp,
1457 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1459 // Hacked form of ORHI used to promote 8-bit registers to 16-bit
1461 RI10Form<0b10100000, (outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1462 "orhi\t$rT, $rA, $val", IntegerOp,
1463 [(set R16C:$rT, (or (anyext R8C:$rA), i16ImmSExt10:$val))]>;
1465 // Bitwise "or" with immediate
1467 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1468 "ori\t$rT, $rA, $val", IntegerOp,
1469 [(set (v4i32 VECREG:$rT), (or (v4i32 VECREG:$rA),
1470 v4i32Uns10Imm:$val))]>;
1473 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1474 "ori\t$rT, $rA, $val", IntegerOp,
1475 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1477 // Hacked forms of or immediate to copy one 32- and 64-bit FP register
1478 // to another. Do not match patterns.
1480 RI10Form_1<0b00100000, (outs R32FP:$rT), (ins R32FP:$rA, s10imm_i32:$val),
1481 "ori\t$rT, $rA, $val", IntegerOp,
1482 [/* no pattern */]>;
1485 RI10Form_1<0b00100000, (outs R64FP:$rT), (ins R64FP:$rA, s10imm_i32:$val),
1486 "ori\t$rT, $rA, $val", IntegerOp,
1487 [/* no pattern */]>;
1490 RI10Form_1<0b00100000, (outs R64C:$rT), (ins R64C:$rA, s10imm_i32:$val),
1491 "ori\t$rT, $rA, $val", IntegerOp,
1492 [/* no pattern */]>;
1494 // ORI2To4: hacked version of the ori instruction to extend 16-bit quantities
1495 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1496 // infra "anyext 16->32" pattern.)
1498 RI10Form<0b00100000, (outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1499 "ori\t$rT, $rA, $val", IntegerOp,
1500 [(set R32C:$rT, (or (anyext R16C:$rA), i32ImmSExt10:$val))]>;
1502 // ORI1To4: Hacked version of the ORI instruction to extend 16-bit quantities
1503 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1504 // infra "anyext 16->32" pattern.)
1506 RI10Form<0b00100000, (outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1507 "ori\t$rT, $rA, $val", IntegerOp,
1508 [(set R32C:$rT, (or (anyext R8C:$rA), i32ImmSExt10:$val))]>;
1510 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1511 // $rT[0], slots 1-3 are zeroed.
1513 // FIXME: Needs to match an intrinsic pattern.
1515 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1516 "orx\t$rT, $rA, $rB", IntegerOp,
1521 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1522 "xor\t$rT, $rA, $rB", IntegerOp,
1523 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
1526 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1527 "xor\t$rT, $rA, $rB", IntegerOp,
1528 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
1531 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1532 "xor\t$rT, $rA, $rB", IntegerOp,
1533 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
1536 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1537 "xor\t$rT, $rA, $rB", IntegerOp,
1538 [(set R32C:$rT, (xor R32C:$rA, R32C:$rB))]>;
1540 //==----------------------------------------------------------
1541 // Special forms for floating point instructions.
1542 // Bitwise ORs and ANDs don't make sense for normal floating
1543 // point numbers. These operations (fneg and fabs), however,
1544 // require bitwise logical ops to manipulate the sign bit.
1546 RRForm<0b10010010000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1547 "xor\t$rT, $rA, $rB", IntegerOp,
1548 [/* Intentionally does not match a pattern, see fneg32 */]>;
1550 // KLUDGY! Better way to do this without a VECREG? bitconvert?
1551 // VECREG is assumed to contain two identical 64-bit masks, so
1552 // it doesn't matter which word we select for the xor
1554 RRForm<0b10010010000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1555 "xor\t$rT, $rA, $rB", IntegerOp,
1556 [/* Intentionally does not match a pattern, see fneg64 */]>;
1558 // Could use XORv4i32, but will use this for clarity
1560 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1561 "xor\t$rT, $rA, $rB", IntegerOp,
1562 [/* Intentionally does not match a pattern, see fneg{32,64} */]>;
1564 //==----------------------------------------------------------
1567 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1568 "xor\t$rT, $rA, $rB", IntegerOp,
1569 [(set R16C:$rT, (xor R16C:$rA, R16C:$rB))]>;
1572 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1573 "xor\t$rT, $rA, $rB", IntegerOp,
1574 [(set R8C:$rT, (xor R8C:$rA, R8C:$rB))]>;
1577 RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1578 "xorbi\t$rT, $rA, $val", IntegerOp,
1579 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1582 RI10Form<0b01100000, (outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1583 "xorbi\t$rT, $rA, $val", IntegerOp,
1584 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1587 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1588 "xorhi\t$rT, $rA, $val", IntegerOp,
1589 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1590 v8i16SExt10Imm:$val))]>;
1593 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1594 "xorhi\t$rT, $rA, $val", IntegerOp,
1595 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1598 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1599 "xori\t$rT, $rA, $val", IntegerOp,
1600 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1601 v4i32SExt10Imm:$val))]>;
1604 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1605 "xori\t$rT, $rA, $val", IntegerOp,
1606 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1610 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1611 "nand\t$rT, $rA, $rB", IntegerOp,
1612 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1613 (v16i8 VECREG:$rB))))]>;
1616 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1617 "nand\t$rT, $rA, $rB", IntegerOp,
1618 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1619 (v8i16 VECREG:$rB))))]>;
1622 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1623 "nand\t$rT, $rA, $rB", IntegerOp,
1624 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1625 (v4i32 VECREG:$rB))))]>;
1628 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1629 "nand\t$rT, $rA, $rB", IntegerOp,
1630 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1633 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1634 "nand\t$rT, $rA, $rB", IntegerOp,
1635 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1638 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1639 "nand\t$rT, $rA, $rB", IntegerOp,
1640 [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
1644 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1645 "nor\t$rT, $rA, $rB", IntegerOp,
1646 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1647 (v16i8 VECREG:$rB))))]>;
1650 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1651 "nor\t$rT, $rA, $rB", IntegerOp,
1652 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1653 (v8i16 VECREG:$rB))))]>;
1656 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1657 "nor\t$rT, $rA, $rB", IntegerOp,
1658 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1659 (v4i32 VECREG:$rB))))]>;
1662 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1663 "nor\t$rT, $rA, $rB", IntegerOp,
1664 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1667 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1668 "nor\t$rT, $rA, $rB", IntegerOp,
1669 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1672 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1673 "nor\t$rT, $rA, $rB", IntegerOp,
1674 [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
1676 // EQV: Equivalence (1 for each same bit, otherwise 0)
1678 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1679 "eqv\t$rT, $rA, $rB", IntegerOp,
1680 [(set (v16i8 VECREG:$rT), (or (and (v16i8 VECREG:$rA),
1681 (v16i8 VECREG:$rB)),
1682 (and (vnot (v16i8 VECREG:$rA)),
1683 (vnot (v16i8 VECREG:$rB)))))]>;
1685 def : Pat<(xor (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rB))),
1686 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1688 def : Pat<(xor (vnot (v16i8 VECREG:$rA)), (v16i8 VECREG:$rB)),
1689 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1692 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1693 "eqv\t$rT, $rA, $rB", IntegerOp,
1694 [(set (v8i16 VECREG:$rT), (or (and (v8i16 VECREG:$rA),
1695 (v8i16 VECREG:$rB)),
1696 (and (vnot (v8i16 VECREG:$rA)),
1697 (vnot (v8i16 VECREG:$rB)))))]>;
1699 def : Pat<(xor (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rB))),
1700 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1702 def : Pat<(xor (vnot (v8i16 VECREG:$rA)), (v8i16 VECREG:$rB)),
1703 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1706 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1707 "eqv\t$rT, $rA, $rB", IntegerOp,
1708 [(set (v4i32 VECREG:$rT), (or (and (v4i32 VECREG:$rA),
1709 (v4i32 VECREG:$rB)),
1710 (and (vnot (v4i32 VECREG:$rA)),
1711 (vnot (v4i32 VECREG:$rB)))))]>;
1713 def : Pat<(xor (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rB))),
1714 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1716 def : Pat<(xor (vnot (v4i32 VECREG:$rA)), (v4i32 VECREG:$rB)),
1717 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1720 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1721 "eqv\t$rT, $rA, $rB", IntegerOp,
1722 [(set R32C:$rT, (or (and R32C:$rA, R32C:$rB),
1723 (and (not R32C:$rA), (not R32C:$rB))))]>;
1725 def : Pat<(xor R32C:$rA, (not R32C:$rB)),
1726 (EQVr32 R32C:$rA, R32C:$rB)>;
1728 def : Pat<(xor (not R32C:$rA), R32C:$rB),
1729 (EQVr32 R32C:$rA, R32C:$rB)>;
1732 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1733 "eqv\t$rT, $rA, $rB", IntegerOp,
1734 [(set R16C:$rT, (or (and R16C:$rA, R16C:$rB),
1735 (and (not R16C:$rA), (not R16C:$rB))))]>;
1737 def : Pat<(xor R16C:$rA, (not R16C:$rB)),
1738 (EQVr16 R16C:$rA, R16C:$rB)>;
1740 def : Pat<(xor (not R16C:$rA), R16C:$rB),
1741 (EQVr16 R16C:$rA, R16C:$rB)>;
1744 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1745 "eqv\t$rT, $rA, $rB", IntegerOp,
1746 [(set R8C:$rT, (or (and R8C:$rA, R8C:$rB),
1747 (and (not R8C:$rA), (not R8C:$rB))))]>;
1749 def : Pat<(xor R8C:$rA, (not R8C:$rB)),
1750 (EQVr8 R8C:$rA, R8C:$rB)>;
1752 def : Pat<(xor (not R8C:$rA), R8C:$rB),
1753 (EQVr8 R8C:$rA, R8C:$rB)>;
1755 // gcc optimizes (p & q) | (~p & ~q) -> ~(p | q) | (p & q), so match that
1757 def : Pat<(or (vnot (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))),
1758 (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))),
1759 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1761 def : Pat<(or (vnot (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))),
1762 (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))),
1763 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1765 def : Pat<(or (vnot (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))),
1766 (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))),
1767 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1769 def : Pat<(or (not (or R32C:$rA, R32C:$rB)), (and R32C:$rA, R32C:$rB)),
1770 (EQVr32 R32C:$rA, R32C:$rB)>;
1772 def : Pat<(or (not (or R16C:$rA, R16C:$rB)), (and R16C:$rA, R16C:$rB)),
1773 (EQVr16 R16C:$rA, R16C:$rB)>;
1775 def : Pat<(or (not (or R8C:$rA, R8C:$rB)), (and R8C:$rA, R8C:$rB)),
1776 (EQVr8 R8C:$rA, R8C:$rB)>;
1780 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1781 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1782 [(set (v16i8 VECREG:$rT),
1783 (SPUselb_v16i8 (v16i8 VECREG:$rA), (v16i8 VECREG:$rB),
1784 (v16i8 VECREG:$rC)))]>;
1786 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1787 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1788 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1790 def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1791 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1792 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1794 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1795 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1796 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1798 def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1799 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1800 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1802 def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1803 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1804 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1806 def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1807 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1808 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1810 def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1811 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1812 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1814 def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1815 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1816 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1818 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1819 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1820 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1822 def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1823 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1824 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1826 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1827 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1828 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1830 def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1831 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1832 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1834 def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1835 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1836 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1838 def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1839 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1840 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1842 def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1843 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1844 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1846 def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1847 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1848 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1851 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1852 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1853 [(set (v8i16 VECREG:$rT),
1854 (SPUselb_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB),
1855 (v8i16 VECREG:$rC)))]>;
1857 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1858 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1859 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1861 def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1862 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1863 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1865 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1866 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1867 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1869 def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1870 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1871 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1873 def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1874 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1875 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1877 def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1878 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1879 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1881 def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1882 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1883 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1885 def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1886 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1887 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1889 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1890 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1891 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1893 def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1894 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1895 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1897 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1898 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1899 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1901 def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1902 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1903 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1905 def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1906 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1907 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1909 def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1910 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1911 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1913 def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1914 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1915 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1917 def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1918 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1919 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1922 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1923 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1924 [(set (v4i32 VECREG:$rT),
1925 (SPUselb_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB),
1926 (v4i32 VECREG:$rC)))]>;
1928 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1929 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1930 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1932 def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1933 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1934 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1936 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1937 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1938 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1940 def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1941 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1942 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1944 def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1945 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1946 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1948 def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1949 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1950 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1952 def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1953 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1954 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1956 def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1957 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1958 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1960 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1961 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1962 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1964 def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1965 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1966 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1968 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1969 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1970 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1972 def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1973 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1974 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1976 def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1977 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1978 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1980 def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1981 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1982 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1984 def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1985 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1986 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1988 def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1989 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1990 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1993 RRRForm<0b1000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
1994 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1997 // And the various patterns that can be matched... (all 8 of them :-)
1998 def : Pat<(or (and R32C:$rA, R32C:$rC),
1999 (and R32C:$rB, (not R32C:$rC))),
2000 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
2002 def : Pat<(or (and R32C:$rC, R32C:$rA),
2003 (and R32C:$rB, (not R32C:$rC))),
2004 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
2006 def : Pat<(or (and R32C:$rA, R32C:$rC),
2007 (and (not R32C:$rC), R32C:$rB)),
2008 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
2010 def : Pat<(or (and R32C:$rC, R32C:$rA),
2011 (and (not R32C:$rC), R32C:$rB)),
2012 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
2014 def : Pat<(or (and R32C:$rA, (not R32C:$rC)),
2015 (and R32C:$rB, R32C:$rC)),
2016 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
2018 def : Pat<(or (and R32C:$rA, (not R32C:$rC)),
2019 (and R32C:$rC, R32C:$rB)),
2020 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
2022 def : Pat<(or (and (not R32C:$rC), R32C:$rA),
2023 (and R32C:$rB, R32C:$rC)),
2024 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
2026 def : Pat<(or (and (not R32C:$rC), R32C:$rA),
2027 (and R32C:$rC, R32C:$rB)),
2028 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
2031 RRRForm<0b1000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB, R16C:$rC),
2032 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
2035 def : Pat<(or (and R16C:$rA, R16C:$rC),
2036 (and R16C:$rB, (not R16C:$rC))),
2037 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
2039 def : Pat<(or (and R16C:$rC, R16C:$rA),
2040 (and R16C:$rB, (not R16C:$rC))),
2041 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
2043 def : Pat<(or (and R16C:$rA, R16C:$rC),
2044 (and (not R16C:$rC), R16C:$rB)),
2045 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
2047 def : Pat<(or (and R16C:$rC, R16C:$rA),
2048 (and (not R16C:$rC), R16C:$rB)),
2049 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
2051 def : Pat<(or (and R16C:$rA, (not R16C:$rC)),
2052 (and R16C:$rB, R16C:$rC)),
2053 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
2055 def : Pat<(or (and R16C:$rA, (not R16C:$rC)),
2056 (and R16C:$rC, R16C:$rB)),
2057 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
2059 def : Pat<(or (and (not R16C:$rC), R16C:$rA),
2060 (and R16C:$rB, R16C:$rC)),
2061 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
2063 def : Pat<(or (and (not R16C:$rC), R16C:$rA),
2064 (and R16C:$rC, R16C:$rB)),
2065 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
2068 RRRForm<0b1000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB, R8C:$rC),
2069 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
2072 def : Pat<(or (and R8C:$rA, R8C:$rC),
2073 (and R8C:$rB, (not R8C:$rC))),
2074 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
2076 def : Pat<(or (and R8C:$rC, R8C:$rA),
2077 (and R8C:$rB, (not R8C:$rC))),
2078 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
2080 def : Pat<(or (and R8C:$rA, R8C:$rC),
2081 (and (not R8C:$rC), R8C:$rB)),
2082 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
2084 def : Pat<(or (and R8C:$rC, R8C:$rA),
2085 (and (not R8C:$rC), R8C:$rB)),
2086 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
2088 def : Pat<(or (and R8C:$rA, (not R8C:$rC)),
2089 (and R8C:$rB, R8C:$rC)),
2090 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
2092 def : Pat<(or (and R8C:$rA, (not R8C:$rC)),
2093 (and R8C:$rC, R8C:$rB)),
2094 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
2096 def : Pat<(or (and (not R8C:$rC), R8C:$rA),
2097 (and R8C:$rB, R8C:$rC)),
2098 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
2100 def : Pat<(or (and (not R8C:$rC), R8C:$rA),
2101 (and R8C:$rC, R8C:$rB)),
2102 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
2104 //===----------------------------------------------------------------------===//
2105 // Vector shuffle...
2106 //===----------------------------------------------------------------------===//
2109 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
2110 "shufb\t$rT, $rA, $rB, $rC", IntegerOp,
2111 [/* insert intrinsic here */]>;
2113 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
2114 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
2115 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
2116 // the SPUISD::SHUFB opcode.
2117 def : Pat<(SPUshuffle (v16i8 VECREG:$rA), (v16i8 VECREG:$rB), VECREG:$rC),
2118 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
2120 def : Pat<(SPUshuffle (v8i16 VECREG:$rA), (v8i16 VECREG:$rB), VECREG:$rC),
2121 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
2123 def : Pat<(SPUshuffle (v4i32 VECREG:$rA), (v4i32 VECREG:$rB), VECREG:$rC),
2124 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
2126 def : Pat<(SPUshuffle (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), VECREG:$rC),
2127 (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
2129 //===----------------------------------------------------------------------===//
2130 // Shift and rotate group:
2131 //===----------------------------------------------------------------------===//
2134 RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2135 "shlh\t$rT, $rA, $rB", RotateShift,
2136 [(set (v8i16 VECREG:$rT),
2137 (SPUvec_shl_v8i16 (v8i16 VECREG:$rA), R16C:$rB))]>;
2139 // $rB gets promoted to 32-bit register type when confronted with
2140 // this llvm assembly code:
2142 // define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
2143 // %A = shl i16 %arg1, %arg2
2147 // However, we will generate this code when lowering 8-bit shifts and rotates.
2150 RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2151 "shlh\t$rT, $rA, $rB", RotateShift,
2152 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
2155 RRForm<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2156 "shlh\t$rT, $rA, $rB", RotateShift,
2157 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
2160 RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
2161 "shlhi\t$rT, $rA, $val", RotateShift,
2162 [(set (v8i16 VECREG:$rT),
2163 (SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i8 uimm7:$val)))]>;
2165 def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2166 (SHLHIv8i16 VECREG:$rA, imm:$val)>;
2168 def : Pat<(SPUvec_shl_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)),
2169 (SHLHIv8i16 VECREG:$rA, imm:$val)>;
2172 RI7Form<0b11111010000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2173 "shlhi\t$rT, $rA, $val", RotateShift,
2174 [(set R16C:$rT, (shl R16C:$rA, (i32 uimm7:$val)))]>;
2176 def : Pat<(shl R16C:$rA, (i8 uimm7:$val)),
2177 (SHLHIr16 R16C:$rA, uimm7:$val)>;
2179 def : Pat<(shl R16C:$rA, (i16 uimm7:$val)),
2180 (SHLHIr16 R16C:$rA, uimm7:$val)>;
2183 RRForm<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2184 "shl\t$rT, $rA, $rB", RotateShift,
2185 [(set (v4i32 VECREG:$rT),
2186 (SPUvec_shl_v4i32 (v4i32 VECREG:$rA), R16C:$rB))]>;
2189 RRForm<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2190 "shl\t$rT, $rA, $rB", RotateShift,
2191 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
2194 RI7Form<0b11111010000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
2195 "shli\t$rT, $rA, $val", RotateShift,
2196 [(set (v4i32 VECREG:$rT),
2197 (SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i8 uimm7:$val)))]>;
2199 def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2200 (SHLIv4i32 VECREG:$rA, uimm7:$val)>;
2202 def: Pat<(SPUvec_shl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)),
2203 (SHLIv4i32 VECREG:$rA, uimm7:$val)>;
2206 RI7Form<0b11111010000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2207 "shli\t$rT, $rA, $val", RotateShift,
2208 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
2210 def : Pat<(shl R32C:$rA, (i16 uimm7:$val)),
2211 (SHLIr32 R32C:$rA, uimm7:$val)>;
2213 def : Pat<(shl R32C:$rA, (i8 uimm7:$val)),
2214 (SHLIr32 R32C:$rA, uimm7:$val)>;
2216 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
2217 // register) to the left. Vector form is here to ensure type correctness.
2219 RRForm<0b11011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2220 "shlqbi\t$rT, $rA, $rB", RotateShift,
2223 // See note above on SHLQBI.
2225 RI7Form<0b11011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2226 "shlqbii\t$rT, $rA, $val", RotateShift,
2229 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
2232 RI7Form<0b11111011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2233 "shlqbyi\t$rT, $rA, $rB", RotateShift,
2237 RI7Form<0b11111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2238 "shlqbyi\t$rT, $rA, $val", RotateShift,
2243 RRForm<0b00111010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2244 "roth\t$rT, $rA, $rB", RotateShift,
2245 [(set (v8i16 VECREG:$rT),
2246 (SPUvec_rotl_v8i16 VECREG:$rA, VECREG:$rB))]>;
2249 RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2250 "roth\t$rT, $rA, $rB", RotateShift,
2251 [(set R16C:$rT, (rotl R16C:$rA, R16C:$rB))]>;
2254 RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2255 "roth\t$rT, $rA, $rB", RotateShift,
2256 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2258 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2261 RRForm<0b00111010000, (outs R16C:$rT), (ins R16C:$rA, R8C:$rB),
2262 "roth\t$rT, $rA, $rB", RotateShift,
2263 [(set R16C:$rT, (rotl R16C:$rA, (i32 (zext R8C:$rB))))]>;
2265 def : Pat<(rotl R16C:$rA, (i32 (sext R8C:$rB))),
2266 (ROTHr16_r8 R16C:$rA, R8C:$rB)>;
2268 def : Pat<(rotl R16C:$rA, (i32 (zext R8C:$rB))),
2269 (ROTHr16_r8 R16C:$rA, R8C:$rB)>;
2271 def : Pat<(rotl R16C:$rA, (i32 (anyext R8C:$rB))),
2272 (ROTHr16_r8 R16C:$rA, R8C:$rB)>;
2275 RI7Form<0b00111110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i8:$val),
2276 "rothi\t$rT, $rA, $val", RotateShift,
2277 [(set (v8i16 VECREG:$rT),
2278 (SPUvec_rotl_v8i16 VECREG:$rA, (i8 uimm7:$val)))]>;
2280 def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i16 uimm7:$val)),
2281 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2283 def : Pat<(SPUvec_rotl_v8i16 VECREG:$rA, (i32 uimm7:$val)),
2284 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2287 RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2288 "rothi\t$rT, $rA, $val", RotateShift,
2289 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2292 RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2293 "rothi\t$rT, $rA, $val", RotateShift,
2294 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2297 RI7Form<0b00111110000, (outs R16C:$rT), (ins R16C:$rA, u7imm_i8:$val),
2298 "rothi\t$rT, $rA, $val", RotateShift,
2299 [(set R16C:$rT, (rotl R16C:$rA, (i8 uimm7:$val)))]>;
2302 RRForm<0b00011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2303 "rot\t$rT, $rA, $rB", RotateShift,
2304 [(set (v4i32 VECREG:$rT),
2305 (SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), R32C:$rB))]>;
2308 RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2309 "rot\t$rT, $rA, $rB", RotateShift,
2310 [(set R32C:$rT, (rotl R32C:$rA, R32C:$rB))]>;
2312 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2314 def ROTr32_r16_anyext:
2315 RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2316 "rot\t$rT, $rA, $rB", RotateShift,
2317 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2319 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
2320 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2322 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
2323 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2325 def ROTr32_r8_anyext:
2326 RRForm<0b00011010000, (outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2327 "rot\t$rT, $rA, $rB", RotateShift,
2328 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2330 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
2331 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2333 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
2334 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2337 RI7Form<0b00011110000, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2338 "roti\t$rT, $rA, $val", RotateShift,
2339 [(set (v4i32 VECREG:$rT),
2340 (SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
2342 def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2343 (ROTIv4i32 VECREG:$rA, imm:$val)>;
2345 def : Pat<(SPUvec_rotl_v4i32 (v4i32 VECREG:$rA), (i8 uimm7:$val)),
2346 (ROTIv4i32 VECREG:$rA, imm:$val)>;
2349 RI7Form<0b00011110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2350 "roti\t$rT, $rA, $val", RotateShift,
2351 [(set R32C:$rT, (rotl R32C:$rA, (i32 uimm7:$val)))]>;
2354 RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm:$val),
2355 "roti\t$rT, $rA, $val", RotateShift,
2356 [(set R32C:$rT, (rotl R32C:$rA, (i16 uimm7:$val)))]>;
2359 RI7Form<0b00111110000, (outs R32C:$rT), (ins R32C:$rA, u7imm_i8:$val),
2360 "roti\t$rT, $rA, $val", RotateShift,
2361 [(set R32C:$rT, (rotl R32C:$rA, (i8 uimm7:$val)))]>;
2363 // ROTQBY* vector forms: This rotates the entire vector, but vector registers
2364 // are used here for type checking (instances where ROTQBI is used actually
2365 // use vector registers)
2367 RRForm<0b00111011100, (outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2368 "rotqby\t$rT, $rA, $rB", RotateShift,
2369 [(set (v16i8 VECREG:$rT), (SPUrotbytes_left (v16i8 VECREG:$rA), R16C:$rB))]>;
2371 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R16C:$rB),
2372 (ROTQBYvec VECREG:$rA, R16C:$rB)>;
2374 // See ROTQBY note above.
2376 RI7Form<0b00111111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2377 "rotqbyi\t$rT, $rA, $val", RotateShift,
2378 [(set (v16i8 VECREG:$rT),
2379 (SPUrotbytes_left (v16i8 VECREG:$rA), (i16 uimm7:$val)))]>;
2381 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2382 (ROTQBYIvec VECREG:$rA, uimm7:$val)>;
2384 // See ROTQBY note above.
2386 RI7Form<0b00110011100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2387 "rotqbybi\t$rT, $rA, $val", RotateShift,
2390 // See ROTQBY note above.
2392 // Assume that the user of this instruction knows to shift the rotate count
2395 RRForm<0b00011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2396 "rotqbi\t$rT, $rA, $rB", RotateShift,
2397 [/* insert intrinsic here */]>;
2399 // See ROTQBY note above.
2401 RI7Form<0b00011111100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2402 "rotqbii\t$rT, $rA, $val", RotateShift,
2403 [/* insert intrinsic here */]>;
2405 // ROTHM v8i16 form:
2406 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2407 // so this only matches a synthetically generated/lowered code
2409 // NOTE(2): $rB must be negated before the right rotate!
2411 RRForm<0b10111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2412 "rothm\t$rT, $rA, $rB", RotateShift,
2413 [/* see patterns below - $rB must be negated */]>;
2415 def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R32C:$rB),
2416 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2418 def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R16C:$rB),
2419 (ROTHMv8i16 VECREG:$rA,
2420 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2422 def : Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), R8C:$rB),
2423 (ROTHMv8i16 VECREG:$rA,
2424 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2426 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2427 // Note: This instruction doesn't match a pattern because rB must be negated
2428 // for the instruction to work. Thus, the pattern below the instruction!
2430 RRForm<0b10111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2431 "rothm\t$rT, $rA, $rB", RotateShift,
2432 [/* see patterns below - $rB must be negated! */]>;
2434 def : Pat<(srl R16C:$rA, R32C:$rB),
2435 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2437 def : Pat<(srl R16C:$rA, R16C:$rB),
2439 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2441 def : Pat<(srl R16C:$rA, R8C:$rB),
2443 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2445 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2446 // that the immediate can be complemented, so that the user doesn't have to
2449 RI7Form<0b10111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2450 "rothmi\t$rT, $rA, $val", RotateShift,
2451 [(set (v8i16 VECREG:$rT),
2452 (SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i32 imm:$val)))]>;
2454 def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i16 imm:$val)),
2455 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2457 def: Pat<(SPUvec_srl_v8i16 (v8i16 VECREG:$rA), (i8 imm:$val)),
2458 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2461 RI7Form<0b10111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2462 "rothmi\t$rT, $rA, $val", RotateShift,
2463 [(set R16C:$rT, (srl R16C:$rA, (i32 uimm7:$val)))]>;
2465 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2466 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2468 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2469 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2471 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2473 RRForm<0b10011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2474 "rotm\t$rT, $rA, $rB", RotateShift,
2475 [/* see patterns below - $rB must be negated */]>;
2477 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R32C:$rB),
2478 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2480 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, R16C:$rB),
2481 (ROTMv4i32 VECREG:$rA,
2482 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2484 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, /* R8C */ R16C:$rB),
2485 (ROTMv4i32 VECREG:$rA,
2486 (SFIr32 (XSHWr16 /* (XSBHr8 R8C */ R16C:$rB) /*)*/, 0))>;
2489 RRForm<0b10011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2490 "rotm\t$rT, $rA, $rB", RotateShift,
2491 [/* see patterns below - $rB must be negated */]>;
2493 def : Pat<(srl R32C:$rA, R32C:$rB),
2494 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2496 def : Pat<(srl R32C:$rA, R16C:$rB),
2498 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2500 def : Pat<(srl R32C:$rA, R8C:$rB),
2502 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2504 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2506 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2507 "rotmi\t$rT, $rA, $val", RotateShift,
2508 [(set (v4i32 VECREG:$rT),
2509 (SPUvec_srl_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>;
2511 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i16 uimm7:$val)),
2512 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2514 def : Pat<(SPUvec_srl_v4i32 VECREG:$rA, (i8 uimm7:$val)),
2515 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2517 // ROTMI r32 form: know how to complement the immediate value.
2519 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2520 "rotmi\t$rT, $rA, $val", RotateShift,
2521 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2523 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2524 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2526 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2527 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2529 // ROTQMBYvec: This is a vector form merely so that when used in an
2530 // instruction pattern, type checking will succeed. This instruction assumes
2531 // that the user knew to complement $rB.
2533 RRForm<0b10111011100, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2534 "rotqmby\t$rT, $rA, $rB", RotateShift,
2535 [(set (v16i8 VECREG:$rT),
2536 (SPUrotbytes_right_zfill (v16i8 VECREG:$rA), R32C:$rB))]>;
2539 RI7Form<0b10111111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2540 "rotqmbyi\t$rT, $rA, $val", RotateShift,
2541 [(set (v16i8 VECREG:$rT),
2542 (SPUrotbytes_right_zfill (v16i8 VECREG:$rA), (i32 uimm7:$val)))]>;
2544 def : Pat<(SPUrotbytes_right_zfill VECREG:$rA, (i16 uimm7:$val)),
2545 (ROTQMBYIvec VECREG:$rA, uimm7:$val)>;
2548 RRForm<0b10110011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2549 "rotqmbybi\t$rT, $rA, $rB", RotateShift,
2553 RRForm<0b10011011100, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2554 "rotqmbi\t$rT, $rA, $rB", RotateShift,
2558 RI7Form<0b10011111100, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2559 "rotqmbii\t$rT, $rA, $val", RotateShift,
2563 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2564 "rotmah\t$rT, $rA, $rB", RotateShift,
2565 [/* see patterns below - $rB must be negated */]>;
2567 def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R32C:$rB),
2568 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2570 def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R16C:$rB),
2571 (ROTMAHv8i16 VECREG:$rA,
2572 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2574 def : Pat<(SPUvec_sra_v8i16 VECREG:$rA, R8C:$rB),
2575 (ROTMAHv8i16 VECREG:$rA,
2576 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2579 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2580 "rotmah\t$rT, $rA, $rB", RotateShift,
2581 [/* see patterns below - $rB must be negated */]>;
2583 def : Pat<(sra R16C:$rA, R32C:$rB),
2584 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2586 def : Pat<(sra R16C:$rA, R16C:$rB),
2587 (ROTMAHr16 R16C:$rA,
2588 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2590 def : Pat<(sra R16C:$rA, R8C:$rB),
2591 (ROTMAHr16 R16C:$rA,
2592 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2595 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2596 "rotmahi\t$rT, $rA, $val", RotateShift,
2597 [(set (v8i16 VECREG:$rT),
2598 (SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2600 def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2601 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2603 def : Pat<(SPUvec_sra_v8i16 (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2604 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2607 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2608 "rotmahi\t$rT, $rA, $val", RotateShift,
2609 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2611 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2612 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2614 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2615 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2618 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2619 "rotma\t$rT, $rA, $rB", RotateShift,
2620 [/* see patterns below - $rB must be negated */]>;
2622 def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R32C:$rB),
2623 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2625 def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R16C:$rB),
2626 (ROTMAv4i32 (v4i32 VECREG:$rA),
2627 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2629 def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, R8C:$rB),
2630 (ROTMAv4i32 (v4i32 VECREG:$rA),
2631 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2634 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2635 "rotma\t$rT, $rA, $rB", RotateShift,
2636 [/* see patterns below - $rB must be negated */]>;
2638 def : Pat<(sra R32C:$rA, R32C:$rB),
2639 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2641 def : Pat<(sra R32C:$rA, R16C:$rB),
2643 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2645 def : Pat<(sra R32C:$rA, R8C:$rB),
2647 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2650 RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2651 "rotmai\t$rT, $rA, $val", RotateShift,
2652 [(set (v4i32 VECREG:$rT),
2653 (SPUvec_sra_v4i32 VECREG:$rA, (i32 uimm7:$val)))]>;
2655 def : Pat<(SPUvec_sra_v4i32 VECREG:$rA, (i16 uimm7:$val)),
2656 (ROTMAIv4i32 VECREG:$rA, uimm7:$val)>;
2659 RRForm<0b01011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2660 "rotmai\t$rT, $rA, $val", RotateShift,
2661 [(set R32C:$rT, (sra R32C:$rA, (i32 uimm7:$val)))]>;
2663 def : Pat<(sra R32C:$rA, (i16 uimm7:$val)),
2664 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2666 def : Pat<(sra R32C:$rA, (i8 uimm7:$val)),
2667 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2669 //===----------------------------------------------------------------------===//
2670 // Branch and conditionals:
2671 //===----------------------------------------------------------------------===//
2673 let isTerminator = 1, isBarrier = 1 in {
2674 // Halt If Equal (r32 preferred slot only, no vector form)
2676 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2677 "heq\t$rA, $rB", BranchResolv,
2678 [/* no pattern to match */]>;
2681 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2682 "heqi\t$rA, $val", BranchResolv,
2683 [/* no pattern to match */]>;
2685 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2686 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2688 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2689 "hgt\t$rA, $rB", BranchResolv,
2690 [/* no pattern to match */]>;
2693 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2694 "hgti\t$rA, $val", BranchResolv,
2695 [/* no pattern to match */]>;
2698 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2699 "hlgt\t$rA, $rB", BranchResolv,
2700 [/* no pattern to match */]>;
2703 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2704 "hlgti\t$rA, $val", BranchResolv,
2705 [/* no pattern to match */]>;
2708 // Comparison operators:
2710 RRForm<0b00001011110, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2711 "ceqb\t$rT, $rA, $rB", ByteOp,
2712 [/* no pattern to match */]>;
2715 RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2716 "ceqb\t$rT, $rA, $rB", ByteOp,
2717 [/* no pattern to match: intrinsic */]>;
2720 RI10Form<0b01111110, (outs R8C:$rT), (ins R8C:$rA, s7imm:$val),
2721 "ceqbi\t$rT, $rA, $val", ByteOp,
2722 [/* no pattern to match: intrinsic */]>;
2725 RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, s7imm:$val),
2726 "ceqbi\t$rT, $rA, $val", ByteOp,
2727 [/* no pattern to match: intrinsic */]>;
2730 RRForm<0b00010011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2731 "ceqh\t$rT, $rA, $rB", ByteOp,
2732 [/* no pattern to match */]>;
2735 RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2736 "ceqh\t$rT, $rA, $rB", ByteOp,
2737 [/* no pattern to match: intrinsic */]>;
2740 RI10Form<0b10111110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2741 "ceqhi\t$rT, $rA, $val", ByteOp,
2742 [/* no pattern to match: intrinsic */]>;
2745 RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2746 "ceqhi\t$rT, $rA, $val", ByteOp,
2747 [/* no pattern to match: intrinsic */]>;
2750 RRForm<0b00000011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2751 "ceq\t$rT, $rA, $rB", ByteOp,
2752 [/* no pattern to match: intrinsic */]>;
2755 RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2756 "ceq\t$rT, $rA, $rB", ByteOp,
2757 [/* no pattern to match: intrinsic */]>;
2760 RI10Form<0b00111110, (outs R32C:$rT), (ins R32C:$rA, s10imm:$val),
2761 "ceqi\t$rT, $rA, $val", ByteOp,
2762 [/* no pattern to match: intrinsic */]>;
2765 RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2766 "ceqi\t$rT, $rA, $val", ByteOp,
2767 [/* no pattern to match: intrinsic */]>;
2770 // All calls clobber the non-callee-saved registers:
2771 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
2772 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
2773 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
2774 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
2775 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
2776 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
2777 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
2778 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
2779 // All of these instructions use $lr (aka $0)
2781 // Branch relative and set link: Used if we actually know that the target
2782 // is within [-32768, 32767] bytes of the target
2784 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
2785 "brsl\t$$lr, $func",
2786 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
2788 // Branch absolute and set link: Used if we actually know that the target
2789 // is an absolute address
2791 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
2792 "brasl\t$$lr, $func",
2793 [(SPUcall tglobaladdr:$func)]>;
2795 // Branch indirect and set link if external data. These instructions are not
2796 // actually generated, matched by an intrinsic:
2797 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
2798 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
2799 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
2800 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
2802 // Branch indirect and set link. This is the "X-form" address version of a
2805 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
2808 // Unconditional branches:
2809 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
2811 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
2815 // Unconditional, absolute address branch
2817 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
2819 [/* no pattern */]>;
2823 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
2825 // Various branches:
2827 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
2828 "brnz\t$rCond,$dest",
2830 [(brcond R32C:$rCond, bb:$dest)]>;
2833 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
2836 [/* no pattern */]>;
2839 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
2840 "brhnz\t$rCond,$dest",
2842 [(brcond R16C:$rCond, bb:$dest)]>;
2845 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
2848 [/* no pattern */]>;
2852 BICondForm<0b10010100100, "binz\t$rA, $func",
2853 [(SPUbinz R32C:$rA, R32C:$func)]>;
2856 BICondForm<0b00010100100, "biz\t$rA, $func",
2857 [(SPUbiz R32C:$rA, R32C:$func)]>;
2861 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
2862 (BRHZ R16C:$rA, bb:$dest)>;
2863 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
2864 (BRHNZ R16C:$rA, bb:$dest)>;
2866 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
2867 (BRZ R32C:$rA, bb:$dest)>;
2868 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
2869 (BRZ R32C:$rA, bb:$dest)>;
2871 let isTerminator = 1, isBarrier = 1 in {
2872 let isReturn = 1 in {
2874 RETForm<"bi\t$$lr", [(retflag)]>;
2878 //===----------------------------------------------------------------------===//
2879 // Various brcond predicates:
2880 //===----------------------------------------------------------------------===//
2882 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
2883 (BRZ R32C:$rA, bb:$dest)>;
2885 def : Pat<(brcond (i32 (seteq R32C:$rA, R32C:$rB)), bb:$dest),
2886 (BRNZ (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
2888 def : Pat<(brcond (i16 (seteq R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
2889 (BRHNZ (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
2891 def : Pat<(brcond (i16 (seteq R16C:$rA, R16C:$rB)), bb:$dest),
2892 (BRHNZ (CEQHr16 R16C:$rA, R16C:$rB), bb:$dest)>;
2895 //===----------------------------------------------------------------------===//
2896 // Single precision floating point instructions
2897 //===----------------------------------------------------------------------===//
2900 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2901 "fa\t$rT, $rA, $rB", SPrecFP,
2902 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
2905 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
2906 "fa\t$rT, $rA, $rB", SPrecFP,
2907 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
2910 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2911 "fs\t$rT, $rA, $rB", SPrecFP,
2912 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
2915 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
2916 "fs\t$rT, $rA, $rB", SPrecFP,
2917 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
2919 // Floating point reciprocal estimate
2921 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
2922 "frest\t$rT, $rA", SPrecFP,
2923 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
2926 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
2927 "frest\t$rT, $rA", SPrecFP,
2928 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
2930 // Floating point interpolate (used in conjunction with reciprocal estimate)
2932 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2933 "fi\t$rT, $rA, $rB", SPrecFP,
2934 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
2935 (v4f32 VECREG:$rB)))]>;
2938 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
2939 "fi\t$rT, $rA, $rB", SPrecFP,
2940 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
2942 // Floating Compare Equal
2944 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
2945 "fceq\t$rT, $rA, $rB", SPrecFP,
2946 [(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
2949 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
2950 "fcmeq\t$rT, $rA, $rB", SPrecFP,
2951 [(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
2954 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
2955 "fcgt\t$rT, $rA, $rB", SPrecFP,
2956 [(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
2959 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
2960 "fcmgt\t$rT, $rA, $rB", SPrecFP,
2961 [(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
2963 // FP Status and Control Register Write
2964 // Why isn't rT a don't care in the ISA?
2965 // Should we create a special RRForm_3 for this guy and zero out the rT?
2967 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
2968 "fscrwr\t$rA", SPrecFP,
2969 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
2971 // FP Status and Control Register Read
2973 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
2974 "fscrrd\t$rT", SPrecFP,
2975 [/* This instruction requires an intrinsic */]>;
2977 // llvm instruction space
2978 // How do these map onto cell instructions?
2980 // frest rC rB # c = 1/b (both lines)
2982 // fm rD rA rC # d = a * 1/b
2983 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
2984 // fma rB rB rC rD # b = b * c + d
2985 // = -(d *b -a) * c + d
2986 // = a * c - c ( a *b *c - a)
2991 // These llvm instructions will actually map to library calls.
2992 // All that's needed, then, is to check that the appropriate library is
2993 // imported and do a brsl to the proper function name.
2994 // frem # fmod(x, y): x - (x/y) * y
2995 // (Note: fmod(double, double), fmodf(float,float)
2999 // Unimplemented SPU instruction space
3000 // floating reciprocal absolute square root estimate (frsqest)
3002 // The following are probably just intrinsics
3003 // status and control register write
3004 // status and control register read
3006 //--------------------------------------
3007 // Floating point multiply instructions
3008 //--------------------------------------
3011 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3012 "fm\t$rT, $rA, $rB", SPrecFP,
3013 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
3014 (v4f32 VECREG:$rB)))]>;
3017 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3018 "fm\t$rT, $rA, $rB", SPrecFP,
3019 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
3021 // Floating point multiply and add
3022 // e.g. d = c + (a * b)
3024 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3025 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3026 [(set (v4f32 VECREG:$rT),
3027 (fadd (v4f32 VECREG:$rC),
3028 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
3031 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3032 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3033 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3035 // FP multiply and subtract
3036 // Subtracts value in rC from product
3039 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3040 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3041 [(set (v4f32 VECREG:$rT),
3042 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
3043 (v4f32 VECREG:$rC)))]>;
3046 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3047 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3049 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
3051 // Floating Negative Mulitply and Subtract
3052 // Subtracts product from value in rC
3053 // res = fneg(fms a b c)
3056 // NOTE: subtraction order
3060 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3061 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3062 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3065 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3066 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3067 [(set (v4f32 VECREG:$rT),
3068 (fsub (v4f32 VECREG:$rC),
3069 (fmul (v4f32 VECREG:$rA),
3070 (v4f32 VECREG:$rB))))]>;
3072 //--------------------------------------
3073 // Floating Point Conversions
3074 // Signed conversions:
3076 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3077 "csflt\t$rT, $rA, 0", SPrecFP,
3078 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
3080 // Convert signed integer to floating point
3082 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
3083 "csflt\t$rT, $rA, 0", SPrecFP,
3084 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
3086 // Convert unsigned into to float
3088 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3089 "cuflt\t$rT, $rA, 0", SPrecFP,
3090 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
3093 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
3094 "cuflt\t$rT, $rA, 0", SPrecFP,
3095 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
3097 // Convert float to unsigned int
3098 // Assume that scale = 0
3101 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3102 "cfltu\t$rT, $rA, 0", SPrecFP,
3103 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
3106 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3107 "cfltu\t$rT, $rA, 0", SPrecFP,
3108 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
3110 // Convert float to signed int
3111 // Assume that scale = 0
3114 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3115 "cflts\t$rT, $rA, 0", SPrecFP,
3116 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
3119 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3120 "cflts\t$rT, $rA, 0", SPrecFP,
3121 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
3123 //===----------------------------------------------------------------------==//
3124 // Single<->Double precision conversions
3125 //===----------------------------------------------------------------------==//
3127 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
3128 // v4f32, output is v2f64--which goes in the name?)
3130 // Floating point extend single to double
3131 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
3132 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
3135 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3136 "fesd\t$rT, $rA", SPrecFP,
3137 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
3140 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
3141 "fesd\t$rT, $rA", SPrecFP,
3142 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
3144 // Floating point round double to single
3146 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3147 // "frds\t$rT, $rA,", SPrecFP,
3148 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
3151 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
3152 "frds\t$rT, $rA", SPrecFP,
3153 [(set R32FP:$rT, (fround R64FP:$rA))]>;
3155 //ToDo include anyextend?
3157 //===----------------------------------------------------------------------==//
3158 // Double precision floating point instructions
3159 //===----------------------------------------------------------------------==//
3161 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3162 "dfa\t$rT, $rA, $rB", DPrecFP,
3163 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
3166 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3167 "dfa\t$rT, $rA, $rB", DPrecFP,
3168 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3171 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3172 "dfs\t$rT, $rA, $rB", DPrecFP,
3173 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
3176 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3177 "dfs\t$rT, $rA, $rB", DPrecFP,
3178 [(set (v2f64 VECREG:$rT),
3179 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3182 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3183 "dfm\t$rT, $rA, $rB", DPrecFP,
3184 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
3187 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3188 "dfm\t$rT, $rA, $rB", DPrecFP,
3189 [(set (v2f64 VECREG:$rT),
3190 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3193 RRForm<0b00111010110, (outs R64FP:$rT),
3194 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3195 "dfma\t$rT, $rA, $rB", DPrecFP,
3196 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3197 RegConstraint<"$rC = $rT">,
3201 RRForm<0b00111010110, (outs VECREG:$rT),
3202 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3203 "dfma\t$rT, $rA, $rB", DPrecFP,
3204 [(set (v2f64 VECREG:$rT),
3205 (fadd (v2f64 VECREG:$rC),
3206 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
3207 RegConstraint<"$rC = $rT">,
3211 RRForm<0b10111010110, (outs R64FP:$rT),
3212 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3213 "dfms\t$rT, $rA, $rB", DPrecFP,
3214 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
3215 RegConstraint<"$rC = $rT">,
3219 RRForm<0b10111010110, (outs VECREG:$rT),
3220 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3221 "dfms\t$rT, $rA, $rB", DPrecFP,
3222 [(set (v2f64 VECREG:$rT),
3223 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3224 (v2f64 VECREG:$rC)))]>;
3226 // FNMS: - (a * b - c)
3227 // - (a * b) + c => c - (a * b)
3229 RRForm<0b01111010110, (outs R64FP:$rT),
3230 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3231 "dfnms\t$rT, $rA, $rB", DPrecFP,
3232 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3233 RegConstraint<"$rC = $rT">,
3236 def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
3237 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
3240 RRForm<0b01111010110, (outs VECREG:$rT),
3241 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3242 "dfnms\t$rT, $rA, $rB", DPrecFP,
3243 [(set (v2f64 VECREG:$rT),
3244 (fsub (v2f64 VECREG:$rC),
3245 (fmul (v2f64 VECREG:$rA),
3246 (v2f64 VECREG:$rB))))]>,
3247 RegConstraint<"$rC = $rT">,
3250 def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3251 (v2f64 VECREG:$rC))),
3252 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
3257 RRForm<0b11111010110, (outs R64FP:$rT),
3258 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3259 "dfnma\t$rT, $rA, $rB", DPrecFP,
3260 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
3261 RegConstraint<"$rC = $rT">,
3265 RRForm<0b11111010110, (outs VECREG:$rT),
3266 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3267 "dfnma\t$rT, $rA, $rB", DPrecFP,
3268 [(set (v2f64 VECREG:$rT),
3269 (fneg (fadd (v2f64 VECREG:$rC),
3270 (fmul (v2f64 VECREG:$rA),
3271 (v2f64 VECREG:$rB)))))]>,
3272 RegConstraint<"$rC = $rT">,
3275 //===----------------------------------------------------------------------==//
3276 // Floating point negation and absolute value
3277 //===----------------------------------------------------------------------==//
3279 def : Pat<(fneg (v4f32 VECREG:$rA)),
3280 (XORfnegvec (v4f32 VECREG:$rA),
3281 (v4f32 (ILHUv4i32 0x8000)))>;
3283 def : Pat<(fneg R32FP:$rA),
3284 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
3286 def : Pat<(fneg (v2f64 VECREG:$rA)),
3287 (XORfnegvec (v2f64 VECREG:$rA),
3288 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
3290 def : Pat<(fneg R64FP:$rA),
3291 (XORfneg64 R64FP:$rA,
3292 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
3294 // Floating point absolute value
3296 def : Pat<(fabs R32FP:$rA),
3297 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
3299 def : Pat<(fabs (v4f32 VECREG:$rA)),
3300 (ANDfabsvec (v4f32 VECREG:$rA),
3301 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3303 def : Pat<(fabs R64FP:$rA),
3304 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
3306 def : Pat<(fabs (v2f64 VECREG:$rA)),
3307 (ANDfabsvec (v2f64 VECREG:$rA),
3308 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3310 //===----------------------------------------------------------------------===//
3311 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
3312 // in the odd pipeline)
3313 //===----------------------------------------------------------------------===//
3315 def ENOP : I<(outs), (ins), "enop", ExecNOP> {
3318 let Inst{0-10} = 0b10000000010;
3319 let Inst{11-17} = 0;
3320 let Inst{18-24} = 0;
3321 let Inst{25-31} = 0;
3324 def LNOP : I<(outs), (ins), "lnop", LoadNOP> {
3327 let Inst{0-10} = 0b10000000000;
3328 let Inst{11-17} = 0;
3329 let Inst{18-24} = 0;
3330 let Inst{25-31} = 0;
3333 //===----------------------------------------------------------------------===//
3334 // Bit conversions (type conversions between vector/packed types)
3335 // NOTE: Promotions are handled using the XS* instructions. Truncation
3337 //===----------------------------------------------------------------------===//
3338 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3339 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3340 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3341 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3342 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3344 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3345 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3346 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3347 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3348 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3350 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3351 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3352 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3353 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3354 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3356 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3357 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3358 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3359 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3360 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3362 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3363 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3364 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3365 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3366 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3368 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3369 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3370 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3371 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3372 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3374 def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3376 //===----------------------------------------------------------------------===//
3377 // Instruction patterns:
3378 //===----------------------------------------------------------------------===//
3380 // General 32-bit constants:
3381 def : Pat<(i32 imm:$imm),
3382 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3384 // Single precision float constants:
3385 def : Pat<(SPUFPconstant (f32 fpimm:$imm)),
3386 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3388 // General constant 32-bit vectors
3389 def : Pat<(v4i32 v4i32Imm:$imm),
3390 (IOHLvec (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
3391 (LO16_vec v4i32Imm:$imm))>;
3394 def : Pat<(i8 imm:$imm),
3397 //===----------------------------------------------------------------------===//
3398 // Call instruction patterns:
3399 //===----------------------------------------------------------------------===//
3404 //===----------------------------------------------------------------------===//
3405 // Zero/Any/Sign extensions
3406 //===----------------------------------------------------------------------===//
3408 // zext 1->32: Zero extend i1 to i32
3409 def : Pat<(SPUextract_i1_zext R32C:$rSrc),
3410 (ANDIr32 R32C:$rSrc, 0x1)>;
3412 // sext 8->32: Sign extend bytes to words
3413 def : Pat<(sext_inreg R32C:$rSrc, i8),
3414 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
3416 def : Pat<(i32 (sext R8C:$rSrc)),
3417 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
3419 def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
3420 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
3421 (v4i32 VECREG:$rSrc))))>;
3423 // zext 8->16: Zero extend bytes to halfwords
3424 def : Pat<(i16 (zext R8C:$rSrc)),
3425 (ANDHI1To2 R8C:$rSrc, 0xff)>;
3427 // zext 8->32 from preferred slot in load/store
3428 def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
3429 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
3432 // zext 8->32: Zero extend bytes to words
3433 def : Pat<(i32 (zext R8C:$rSrc)),
3434 (ANDI1To4 R8C:$rSrc, 0xff)>;
3436 // anyext 8->16: Extend 8->16 bits, irrespective of sign
3437 def : Pat<(i16 (anyext R8C:$rSrc)),
3438 (ORHI1To2 R8C:$rSrc, 0)>;
3440 // anyext 8->32: Extend 8->32 bits, irrespective of sign
3441 def : Pat<(i32 (anyext R8C:$rSrc)),
3442 (ORI1To4 R8C:$rSrc, 0)>;
3444 // zext 16->32: Zero extend halfwords to words (note that we have to juggle the
3445 // 0xffff constant since it will not fit into an immediate.)
3446 def : Pat<(i32 (zext R16C:$rSrc)),
3447 (AND2To4 R16C:$rSrc, (ILAr32 0xffff))>;
3449 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
3450 (ANDI2To4 R16C:$rSrc, 0xf)>;
3452 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
3453 (ANDI2To4 R16C:$rSrc, 0xff)>;
3455 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
3456 (ANDI2To4 R16C:$rSrc, 0xfff)>;
3458 // anyext 16->32: Extend 16->32 bits, irrespective of sign
3459 def : Pat<(i32 (anyext R16C:$rSrc)),
3460 (ORI2To4 R16C:$rSrc, 0)>;
3462 //===----------------------------------------------------------------------===//
3463 // Address translation: SPU, like PPC, has to split addresses into high and
3464 // low parts in order to load them into a register.
3465 //===----------------------------------------------------------------------===//
3467 def : Pat<(SPUhi tglobaladdr:$in, 0), (ILHUhi tglobaladdr:$in)>;
3468 def : Pat<(SPUlo tglobaladdr:$in, 0), (ILAlo tglobaladdr:$in)>;
3469 def : Pat<(SPUdform tglobaladdr:$in, imm:$imm), (ILAlsa tglobaladdr:$in)>;
3470 def : Pat<(SPUhi tconstpool:$in , 0), (ILHUhi tconstpool:$in)>;
3471 def : Pat<(SPUlo tconstpool:$in , 0), (ILAlo tconstpool:$in)>;
3472 def : Pat<(SPUdform tconstpool:$in, imm:$imm), (ILAlsa tconstpool:$in)>;
3473 def : Pat<(SPUhi tjumptable:$in, 0), (ILHUhi tjumptable:$in)>;
3474 def : Pat<(SPUlo tjumptable:$in, 0), (ILAlo tjumptable:$in)>;
3475 def : Pat<(SPUdform tjumptable:$in, imm:$imm), (ILAlsa tjumptable:$in)>;
3477 // Force load of global address to a register. These forms show up in
3478 // SPUISD::DFormAddr pseudo instructions:
3479 def : Pat<(add tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
3480 def : Pat<(add tconstpool:$in, 0), (ILAlsa tglobaladdr:$in)>;
3481 def : Pat<(add tjumptable:$in, 0), (ILAlsa tglobaladdr:$in)>;
3483 include "CellSDKIntrinsics.td"