1 //==- SPUInstrInfo.td - Describe the Cell SPU Instructions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instructions:
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 // TODO Items (not urgent today, but would be nice, low priority)
15 // ANDBI, ORBI: SPU constructs a 4-byte constant for these instructions by
16 // concatenating the byte argument b as "bbbb". Could recognize this bit pattern
17 // in 16-bit and 32-bit constants and reduce instruction count.
18 //===----------------------------------------------------------------------===//
20 //===----------------------------------------------------------------------===//
21 // Pseudo instructions:
22 //===----------------------------------------------------------------------===//
24 let hasCtrlDep = 1, Defs = [R1], Uses = [R1] in {
25 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
26 "${:comment} ADJCALLSTACKDOWN",
27 [(callseq_start imm:$amt)]>;
28 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt),
29 "${:comment} ADJCALLSTACKUP",
30 [(callseq_end imm:$amt)]>;
33 //===----------------------------------------------------------------------===//
34 // DWARF debugging Pseudo Instructions
35 //===----------------------------------------------------------------------===//
37 def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
38 "${:comment} .loc $file, $line, $col",
39 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
42 //===----------------------------------------------------------------------===//
44 // NB: The ordering is actually important, since the instruction selection
45 // will try each of the instructions in sequence, i.e., the D-form first with
46 // the 10-bit displacement, then the A-form with the 16 bit displacement, and
47 // finally the X-form with the register-register.
48 //===----------------------------------------------------------------------===//
50 let isSimpleLoad = 1 in {
51 class LoadDFormVec<ValueType vectype>
52 : RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
55 [(set (vectype VECREG:$rT), (load dform_addr:$src))]>
58 class LoadDForm<RegisterClass rclass>
59 : RI10Form<0b00101100, (outs rclass:$rT), (ins memri10:$src),
62 [(set rclass:$rT, (load dform_addr:$src))]>
67 def v16i8: LoadDFormVec<v16i8>;
68 def v8i16: LoadDFormVec<v8i16>;
69 def v4i32: LoadDFormVec<v4i32>;
70 def v2i64: LoadDFormVec<v2i64>;
71 def v4f32: LoadDFormVec<v4f32>;
72 def v2f64: LoadDFormVec<v2f64>;
74 def r128: LoadDForm<GPRC>;
75 def r64: LoadDForm<R64C>;
76 def r32: LoadDForm<R32C>;
77 def f32: LoadDForm<R32FP>;
78 def f64: LoadDForm<R64FP>;
79 def r16: LoadDForm<R16C>;
80 def r8: LoadDForm<R8C>;
83 class LoadAFormVec<ValueType vectype>
84 : RI16Form<0b100001100, (outs VECREG:$rT), (ins addr256k:$src),
87 [(set (vectype VECREG:$rT), (load aform_addr:$src))]>
90 class LoadAForm<RegisterClass rclass>
91 : RI16Form<0b100001100, (outs rclass:$rT), (ins addr256k:$src),
94 [(set rclass:$rT, (load aform_addr:$src))]>
99 def v16i8: LoadAFormVec<v16i8>;
100 def v8i16: LoadAFormVec<v8i16>;
101 def v4i32: LoadAFormVec<v4i32>;
102 def v2i64: LoadAFormVec<v2i64>;
103 def v4f32: LoadAFormVec<v4f32>;
104 def v2f64: LoadAFormVec<v2f64>;
106 def r128: LoadAForm<GPRC>;
107 def r64: LoadAForm<R64C>;
108 def r32: LoadAForm<R32C>;
109 def f32: LoadAForm<R32FP>;
110 def f64: LoadAForm<R64FP>;
111 def r16: LoadAForm<R16C>;
112 def r8: LoadAForm<R8C>;
115 class LoadXFormVec<ValueType vectype>
116 : RRForm<0b00100011100, (outs VECREG:$rT), (ins memrr:$src),
119 [(set (vectype VECREG:$rT), (load xform_addr:$src))]>
122 class LoadXForm<RegisterClass rclass>
123 : RRForm<0b00100011100, (outs rclass:$rT), (ins memrr:$src),
126 [(set rclass:$rT, (load xform_addr:$src))]>
129 multiclass LoadXForms
131 def v16i8: LoadXFormVec<v16i8>;
132 def v8i16: LoadXFormVec<v8i16>;
133 def v4i32: LoadXFormVec<v4i32>;
134 def v2i64: LoadXFormVec<v2i64>;
135 def v4f32: LoadXFormVec<v4f32>;
136 def v2f64: LoadXFormVec<v2f64>;
138 def r128: LoadXForm<GPRC>;
139 def r64: LoadXForm<R64C>;
140 def r32: LoadXForm<R32C>;
141 def f32: LoadXForm<R32FP>;
142 def f64: LoadXForm<R64FP>;
143 def r16: LoadXForm<R16C>;
144 def r8: LoadXForm<R8C>;
147 defm LQA : LoadAForms;
148 defm LQD : LoadDForms;
149 defm LQX : LoadXForms;
151 /* Load quadword, PC relative: Not much use at this point in time.
152 Might be of use later for relocatable code. It's effectively the
153 same as LQA, but uses PC-relative addressing.
154 def LQR : RI16Form<0b111001100, (outs VECREG:$rT), (ins s16imm:$disp),
155 "lqr\t$rT, $disp", LoadStore,
156 [(set VECREG:$rT, (load iaddr:$disp))]>;
160 //===----------------------------------------------------------------------===//
162 //===----------------------------------------------------------------------===//
163 class StoreDFormVec<ValueType vectype>
164 : RI10Form<0b00100100, (outs), (ins VECREG:$rT, memri10:$src),
167 [(store (vectype VECREG:$rT), dform_addr:$src)]>
170 class StoreDForm<RegisterClass rclass>
171 : RI10Form<0b00100100, (outs), (ins rclass:$rT, memri10:$src),
174 [(store rclass:$rT, dform_addr:$src)]>
177 multiclass StoreDForms
179 def v16i8: StoreDFormVec<v16i8>;
180 def v8i16: StoreDFormVec<v8i16>;
181 def v4i32: StoreDFormVec<v4i32>;
182 def v2i64: StoreDFormVec<v2i64>;
183 def v4f32: StoreDFormVec<v4f32>;
184 def v2f64: StoreDFormVec<v2f64>;
186 def r128: StoreDForm<GPRC>;
187 def r64: StoreDForm<R64C>;
188 def r32: StoreDForm<R32C>;
189 def f32: StoreDForm<R32FP>;
190 def f64: StoreDForm<R64FP>;
191 def r16: StoreDForm<R16C>;
192 def r8: StoreDForm<R8C>;
195 class StoreAFormVec<ValueType vectype>
196 : RI16Form<0b0010010, (outs), (ins VECREG:$rT, addr256k:$src),
199 [(store (vectype VECREG:$rT), aform_addr:$src)]>
202 class StoreAForm<RegisterClass rclass>
203 : RI16Form<0b001001, (outs), (ins rclass:$rT, addr256k:$src),
206 [(store rclass:$rT, aform_addr:$src)]>
209 multiclass StoreAForms
211 def v16i8: StoreAFormVec<v16i8>;
212 def v8i16: StoreAFormVec<v8i16>;
213 def v4i32: StoreAFormVec<v4i32>;
214 def v2i64: StoreAFormVec<v2i64>;
215 def v4f32: StoreAFormVec<v4f32>;
216 def v2f64: StoreAFormVec<v2f64>;
218 def r128: StoreAForm<GPRC>;
219 def r64: StoreAForm<R64C>;
220 def r32: StoreAForm<R32C>;
221 def f32: StoreAForm<R32FP>;
222 def f64: StoreAForm<R64FP>;
223 def r16: StoreAForm<R16C>;
224 def r8: StoreAForm<R8C>;
227 class StoreXFormVec<ValueType vectype>
228 : RRForm<0b00100100, (outs), (ins VECREG:$rT, memrr:$src),
231 [(store (vectype VECREG:$rT), xform_addr:$src)]>
234 class StoreXForm<RegisterClass rclass>
235 : RRForm<0b00100100, (outs), (ins rclass:$rT, memrr:$src),
238 [(store rclass:$rT, xform_addr:$src)]>
241 multiclass StoreXForms
243 def v16i8: StoreXFormVec<v16i8>;
244 def v8i16: StoreXFormVec<v8i16>;
245 def v4i32: StoreXFormVec<v4i32>;
246 def v2i64: StoreXFormVec<v2i64>;
247 def v4f32: StoreXFormVec<v4f32>;
248 def v2f64: StoreXFormVec<v2f64>;
250 def r128: StoreXForm<GPRC>;
251 def r64: StoreXForm<R64C>;
252 def r32: StoreXForm<R32C>;
253 def f32: StoreXForm<R32FP>;
254 def f64: StoreXForm<R64FP>;
255 def r16: StoreXForm<R16C>;
256 def r8: StoreXForm<R8C>;
259 defm STQD : StoreDForms;
260 defm STQA : StoreAForms;
261 defm STQX : StoreXForms;
263 /* Store quadword, PC relative: Not much use at this point in time. Might
264 be useful for relocatable code.
265 def STQR : RI16Form<0b111000100, (outs), (ins VECREG:$rT, s16imm:$disp),
266 "stqr\t$rT, $disp", LoadStore,
267 [(store VECREG:$rT, iaddr:$disp)]>;
270 //===----------------------------------------------------------------------===//
271 // Generate Controls for Insertion:
272 //===----------------------------------------------------------------------===//
275 RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
276 "cbd\t$rT, $src", ShuffleOp,
277 [(set (v16i8 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
279 def CBX : RRForm<0b00101011100, (outs VECREG:$rT), (ins memrr:$src),
280 "cbx\t$rT, $src", ShuffleOp,
281 [(set (v16i8 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
283 def CHD : RI7Form<0b10101111100, (outs VECREG:$rT), (ins memri7:$src),
284 "chd\t$rT, $src", ShuffleOp,
285 [(set (v8i16 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
287 def CHX : RRForm<0b10101011100, (outs VECREG:$rT), (ins memrr:$src),
288 "chx\t$rT, $src", ShuffleOp,
289 [(set (v8i16 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
291 def CWD : RI7Form<0b01101111100, (outs VECREG:$rT), (ins memri7:$src),
292 "cwd\t$rT, $src", ShuffleOp,
293 [(set (v4i32 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
295 def CWX : RRForm<0b01101011100, (outs VECREG:$rT), (ins memrr:$src),
296 "cwx\t$rT, $src", ShuffleOp,
297 [(set (v4i32 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
299 def CDD : RI7Form<0b11101111100, (outs VECREG:$rT), (ins memri7:$src),
300 "cdd\t$rT, $src", ShuffleOp,
301 [(set (v2i64 VECREG:$rT), (SPUvecinsmask dform2_addr:$src))]>;
303 def CDX : RRForm<0b11101011100, (outs VECREG:$rT), (ins memrr:$src),
304 "cdx\t$rT, $src", ShuffleOp,
305 [(set (v2i64 VECREG:$rT), (SPUvecinsmask xform_addr:$src))]>;
307 //===----------------------------------------------------------------------===//
308 // Constant formation:
309 //===----------------------------------------------------------------------===//
312 RI16Form<0b110000010, (outs VECREG:$rT), (ins s16imm:$val),
313 "ilh\t$rT, $val", ImmLoad,
314 [(set (v8i16 VECREG:$rT), (v8i16 v8i16SExt16Imm:$val))]>;
317 RI16Form<0b110000010, (outs R16C:$rT), (ins s16imm:$val),
318 "ilh\t$rT, $val", ImmLoad,
319 [(set R16C:$rT, immSExt16:$val)]>;
321 // Cell SPU doesn't have a native 8-bit immediate load, but ILH works ("with
322 // the right constant")
324 RI16Form<0b110000010, (outs R8C:$rT), (ins s16imm_i8:$val),
325 "ilh\t$rT, $val", ImmLoad,
326 [(set R8C:$rT, immSExt8:$val)]>;
328 // IL does sign extension!
330 RI16Form<0b100000010, (outs R64C:$rT), (ins s16imm_i64:$val),
331 "il\t$rT, $val", ImmLoad,
332 [(set R64C:$rT, immSExt16:$val)]>;
335 RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm_i64:$val),
336 "il\t$rT, $val", ImmLoad,
337 [(set VECREG:$rT, (v2i64 v2i64SExt16Imm:$val))]>;
340 RI16Form<0b100000010, (outs VECREG:$rT), (ins s16imm:$val),
341 "il\t$rT, $val", ImmLoad,
342 [(set VECREG:$rT, (v4i32 v4i32SExt16Imm:$val))]>;
345 RI16Form<0b100000010, (outs R32C:$rT), (ins s16imm_i32:$val),
346 "il\t$rT, $val", ImmLoad,
347 [(set R32C:$rT, immSExt16:$val)]>;
350 RI16Form<0b100000010, (outs R32FP:$rT), (ins s16imm_f32:$val),
351 "il\t$rT, $val", ImmLoad,
352 [(set R32FP:$rT, fpimmSExt16:$val)]>;
355 RI16Form<0b100000010, (outs R64FP:$rT), (ins s16imm_f64:$val),
356 "il\t$rT, $val", ImmLoad,
357 [(set R64FP:$rT, fpimmSExt16:$val)]>;
360 RI16Form<0b010000010, (outs VECREG:$rT), (ins u16imm:$val),
361 "ilhu\t$rT, $val", ImmLoad,
362 [(set VECREG:$rT, (v4i32 immILHUvec:$val))]>;
365 RI16Form<0b010000010, (outs R32C:$rT), (ins u16imm:$val),
366 "ilhu\t$rT, $val", ImmLoad,
367 [(set R32C:$rT, hi16:$val)]>;
369 // ILHUf32: Used to custom lower float constant loads
371 RI16Form<0b010000010, (outs R32FP:$rT), (ins f16imm:$val),
372 "ilhu\t$rT, $val", ImmLoad,
373 [(set R32FP:$rT, hi16_f32:$val)]>;
375 // ILHUhi: Used for loading high portion of an address. Note the symbolHi
376 // printer used for the operand.
378 RI16Form<0b010000010, (outs R32C:$rT), (ins symbolHi:$val),
379 "ilhu\t$rT, $val", ImmLoad,
380 [(set R32C:$rT, hi16:$val)]>;
382 // Immediate load address (can also be used to load 18-bit unsigned constants,
383 // see the zext 16->32 pattern)
384 class ILAInst<dag OOL, dag IOL, list<dag> pattern>:
385 RI18Form<0b1000010, OOL, IOL, "ila\t$rT, $val",
388 multiclass ImmLoadAddress
390 def v2i64: ILAInst<(outs VECREG:$rT), (ins u18imm:$val),
391 [(set (v2i64 VECREG:$rT), v2i64Uns18Imm:$val)]>;
393 def v4i32: ILAInst<(outs VECREG:$rT), (ins u18imm:$val),
394 [(set (v4i32 VECREG:$rT), v4i32Uns18Imm:$val)]>;
396 def r64: ILAInst<(outs R64C:$rT), (ins u18imm_i64:$val),
397 [(set R64C:$rT, imm18:$val)]>;
399 def r32: ILAInst<(outs R32C:$rT), (ins u18imm:$val),
400 [(set R32C:$rT, imm18:$val)]>;
402 def f32: ILAInst<(outs R32FP:$rT), (ins f18imm:$val),
403 [(set R32FP:$rT, fpimm18:$val)]>;
405 def f64: ILAInst<(outs R64FP:$rT), (ins f18imm_f64:$val),
406 [(set R64FP:$rT, fpimm18:$val)]>;
408 def lo: ILAInst<(outs R32C:$rT), (ins symbolLo:$val),
409 [(set R32C:$rT, imm18:$val)]>;
411 def lsa: ILAInst<(outs R32C:$rT), (ins symbolLSA:$val),
415 defm ILA : ImmLoadAddress;
417 // Immediate OR, Halfword Lower: The "other" part of loading large constants
418 // into 32-bit registers. See the anonymous pattern Pat<(i32 imm:$imm), ...>
419 // Note that these are really two operand instructions, but they're encoded
420 // as three operands with the first two arguments tied-to each other.
423 RI16Form<0b100000110, (outs VECREG:$rT), (ins VECREG:$rS, u16imm:$val),
424 "iohl\t$rT, $val", ImmLoad,
425 [/* insert intrinsic here */]>,
426 RegConstraint<"$rS = $rT">,
430 RI16Form<0b100000110, (outs R32C:$rT), (ins R32C:$rS, i32imm:$val),
431 "iohl\t$rT, $val", ImmLoad,
432 [/* insert intrinsic here */]>,
433 RegConstraint<"$rS = $rT">,
437 RI16Form<0b100000110, (outs R32FP:$rT), (ins R32FP:$rS, f32imm:$val),
438 "iohl\t$rT, $val", ImmLoad,
439 [/* insert intrinsic here */]>,
440 RegConstraint<"$rS = $rT">,
444 RI16Form<0b100000110, (outs R32C:$rT), (ins R32C:$rS, symbolLo:$val),
445 "iohl\t$rT, $val", ImmLoad,
447 RegConstraint<"$rS = $rT">,
450 // Form select mask for bytes using immediate, used in conjunction with the
453 class FSMBIVec<ValueType vectype>
454 : RI16Form<0b101001100, (outs VECREG:$rT), (ins u16imm:$val),
457 [(set (vectype VECREG:$rT), (SPUfsmbi immU16:$val))]>
460 multiclass FormSelectMaskBytesImm
462 def v16i8: FSMBIVec<v16i8>;
463 def v8i16: FSMBIVec<v8i16>;
464 def v4i32: FSMBIVec<v4i32>;
465 def v2i64: FSMBIVec<v2i64>;
468 defm FSMBI : FormSelectMaskBytesImm;
470 // fsmb: Form select mask for bytes. N.B. Input operand, $rA, is 16-bits
472 RRForm_1<0b01101101100, (outs VECREG:$rT), (ins R16C:$rA),
473 "fsmb\t$rT, $rA", SelectOp,
476 // fsmh: Form select mask for halfwords. N.B., Input operand, $rA, is
477 // only 8-bits wide (even though it's input as 16-bits here)
479 RRForm_1<0b10101101100, (outs VECREG:$rT), (ins R16C:$rA),
480 "fsmh\t$rT, $rA", SelectOp,
483 // fsm: Form select mask for words. Like the other fsm* instructions,
484 // only the lower 4 bits of $rA are significant.
486 RRForm_1<0b00101101100, (outs VECREG:$rT), (ins R16C:$rA),
487 "fsm\t$rT, $rA", SelectOp,
490 //===----------------------------------------------------------------------===//
491 // Integer and Logical Operations:
492 //===----------------------------------------------------------------------===//
495 RRForm<0b00010011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
496 "ah\t$rT, $rA, $rB", IntegerOp,
497 [(set (v8i16 VECREG:$rT), (int_spu_si_ah VECREG:$rA, VECREG:$rB))]>;
499 def : Pat<(add (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
500 (AHv8i16 VECREG:$rA, VECREG:$rB)>;
503 RRForm<0b00010011000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
504 "ah\t$rT, $rA, $rB", IntegerOp,
505 [(set R16C:$rT, (add R16C:$rA, R16C:$rB))]>;
508 RI10Form<0b10111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
509 "ahi\t$rT, $rA, $val", IntegerOp,
510 [(set (v8i16 VECREG:$rT), (add (v8i16 VECREG:$rA),
511 v8i16SExt10Imm:$val))]>;
514 RI10Form<0b10111000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
515 "ahi\t$rT, $rA, $val", IntegerOp,
516 [(set R16C:$rT, (add R16C:$rA, v8i16SExt10Imm:$val))]>;
519 RRForm<0b00000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
520 "a\t$rT, $rA, $rB", IntegerOp,
521 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
523 def : Pat<(add (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
524 (Avec VECREG:$rA, VECREG:$rB)>;
527 RRForm<0b00000011000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
528 "a\t$rT, $rA, $rB", IntegerOp,
529 [(set R32C:$rT, (add R32C:$rA, R32C:$rB))]>;
532 RRForm<0b00000011000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
533 "a\t$rT, $rA, $rB", IntegerOp,
534 [(set R8C:$rT, (add R8C:$rA, R8C:$rB))]>;
537 RI10Form<0b00111000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
538 "ai\t$rT, $rA, $val", IntegerOp,
539 [(set (v4i32 VECREG:$rT), (add (v4i32 VECREG:$rA),
540 v4i32SExt10Imm:$val))]>;
543 RI10Form<0b00111000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
544 "ai\t$rT, $rA, $val", IntegerOp,
545 [(set R32C:$rT, (add R32C:$rA, i32ImmSExt10:$val))]>;
548 RRForm<0b00010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
549 "sfh\t$rT, $rA, $rB", IntegerOp,
550 [(set (v8i16 VECREG:$rT), (sub (v8i16 VECREG:$rA),
551 (v8i16 VECREG:$rB)))]>;
554 RRForm<0b00010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
555 "sfh\t$rT, $rA, $rB", IntegerOp,
556 [(set R16C:$rT, (sub R16C:$rA, R16C:$rB))]>;
559 RI10Form<0b10110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
560 "sfhi\t$rT, $rA, $val", IntegerOp,
561 [(set (v8i16 VECREG:$rT), (sub v8i16SExt10Imm:$val,
562 (v8i16 VECREG:$rA)))]>;
564 def SFHIr16 : RI10Form<0b10110000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
565 "sfhi\t$rT, $rA, $val", IntegerOp,
566 [(set R16C:$rT, (sub i16ImmSExt10:$val, R16C:$rA))]>;
568 def SFvec : RRForm<0b00000010000, (outs VECREG:$rT),
569 (ins VECREG:$rA, VECREG:$rB),
570 "sf\t$rT, $rA, $rB", IntegerOp,
571 [(set (v4i32 VECREG:$rT), (sub (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
573 def SFr32 : RRForm<0b00000010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
574 "sf\t$rT, $rA, $rB", IntegerOp,
575 [(set R32C:$rT, (sub R32C:$rA, R32C:$rB))]>;
578 RI10Form<0b00110000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
579 "sfi\t$rT, $rA, $val", IntegerOp,
580 [(set (v4i32 VECREG:$rT), (sub v4i32SExt10Imm:$val,
581 (v4i32 VECREG:$rA)))]>;
583 def SFIr32 : RI10Form<0b00110000, (outs R32C:$rT),
584 (ins R32C:$rA, s10imm_i32:$val),
585 "sfi\t$rT, $rA, $val", IntegerOp,
586 [(set R32C:$rT, (sub i32ImmSExt10:$val, R32C:$rA))]>;
588 // ADDX: only available in vector form, doesn't match a pattern.
590 RRForm<0b00000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
592 "addx\t$rT, $rA, $rB", IntegerOp,
594 RegConstraint<"$rCarry = $rT">,
597 // CG: only available in vector form, doesn't match a pattern.
599 RRForm<0b01000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
601 "cg\t$rT, $rA, $rB", IntegerOp,
603 RegConstraint<"$rCarry = $rT">,
606 // SFX: only available in vector form, doesn't match a pattern
608 RRForm<0b10000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
610 "sfx\t$rT, $rA, $rB", IntegerOp,
612 RegConstraint<"$rCarry = $rT">,
615 // BG: only available in vector form, doesn't match a pattern.
617 RRForm<0b01000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
619 "bg\t$rT, $rA, $rB", IntegerOp,
621 RegConstraint<"$rCarry = $rT">,
624 // BGX: only available in vector form, doesn't match a pattern.
626 RRForm<0b11000010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB,
628 "bgx\t$rT, $rA, $rB", IntegerOp,
630 RegConstraint<"$rCarry = $rT">,
633 // Halfword multiply variants:
634 // N.B: These can be used to build up larger quantities (16x16 -> 32)
637 RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
638 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
639 [(set (v8i16 VECREG:$rT), (SPUmpy_v8i16 (v8i16 VECREG:$rA),
640 (v8i16 VECREG:$rB)))]>;
643 RRForm<0b00100011110, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
644 "mpy\t$rT, $rA, $rB", IntegerMulDiv,
645 [(set R16C:$rT, (mul R16C:$rA, R16C:$rB))]>;
648 RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
649 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
650 [(set (v4i32 VECREG:$rT),
651 (SPUmpyu_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
654 RRForm<0b00110011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
655 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
656 [(set R32C:$rT, (mul (zext R16C:$rA),
660 RRForm<0b00110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
661 "mpyu\t$rT, $rA, $rB", IntegerMulDiv,
662 [(set R32C:$rT, (SPUmpyu_i32 R32C:$rA, R32C:$rB))]>;
664 // mpyi: multiply 16 x s10imm -> 32 result (custom lowering for 32 bit result,
665 // this only produces the lower 16 bits)
667 RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
668 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
669 [(set (v8i16 VECREG:$rT), (mul (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
672 RI10Form<0b00101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
673 "mpyi\t$rT, $rA, $val", IntegerMulDiv,
674 [(set R16C:$rT, (mul R16C:$rA, i16ImmSExt10:$val))]>;
676 // mpyui: same issues as other multiplies, plus, this doesn't match a
677 // pattern... but may be used during target DAG selection or lowering
679 RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
680 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
684 RI10Form<0b10101110, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
685 "mpyui\t$rT, $rA, $val", IntegerMulDiv,
688 // mpya: 16 x 16 + 16 -> 32 bit result
690 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
691 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
692 [(set (v4i32 VECREG:$rT), (add (v4i32 (bitconvert (mul (v8i16 VECREG:$rA),
693 (v8i16 VECREG:$rB)))),
694 (v4i32 VECREG:$rC)))]>;
697 RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
698 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
699 [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
702 def : Pat<(add (mul (sext R16C:$rA), (sext R16C:$rB)), R32C:$rC),
703 (MPYAr32 R16C:$rA, R16C:$rB, R32C:$rC)>;
705 def MPYAr32_sextinreg:
706 RRRForm<0b0011, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
707 "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
708 [(set R32C:$rT, (add (mul (sext_inreg R32C:$rA, i16),
709 (sext_inreg R32C:$rB, i16)),
713 // RRRForm<0b0011, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB, R32C:$rC),
714 // "mpya\t$rT, $rA, $rB, $rC", IntegerMulDiv,
715 // [(set R32C:$rT, (add (sext (mul R16C:$rA, R16C:$rB)),
718 // mpyh: multiply high, used to synthesize 32-bit multiplies
720 RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
721 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
722 [(set (v4i32 VECREG:$rT),
723 (SPUmpyh_v4i32 (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
726 RRForm<0b10100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
727 "mpyh\t$rT, $rA, $rB", IntegerMulDiv,
728 [(set R32C:$rT, (SPUmpyh_i32 R32C:$rA, R32C:$rB))]>;
730 // mpys: multiply high and shift right (returns the top half of
731 // a 16-bit multiply, sign extended to 32 bits.)
733 RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
734 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
738 RRForm<0b11100011110, (outs R32C:$rT), (ins R16C:$rA, R16C:$rB),
739 "mpys\t$rT, $rA, $rB", IntegerMulDiv,
742 // mpyhh: multiply high-high (returns the 32-bit result from multiplying
743 // the top 16 bits of the $rA, $rB)
745 RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
746 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
747 [(set (v8i16 VECREG:$rT),
748 (SPUmpyhh_v8i16 (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
751 RRForm<0b01100011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
752 "mpyhh\t$rT, $rA, $rB", IntegerMulDiv,
755 // mpyhha: Multiply high-high, add to $rT:
757 RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
758 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
762 RRForm<0b01100010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
763 "mpyhha\t$rT, $rA, $rB", IntegerMulDiv,
766 // mpyhhu: Multiply high-high, unsigned
768 RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
769 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
773 RRForm<0b01110011110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
774 "mpyhhu\t$rT, $rA, $rB", IntegerMulDiv,
777 // mpyhhau: Multiply high-high, unsigned
779 RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
780 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
784 RRForm<0b01110010110, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
785 "mpyhhau\t$rT, $rA, $rB", IntegerMulDiv,
788 // clz: Count leading zeroes
790 RRForm_1<0b10100101010, (outs VECREG:$rT), (ins VECREG:$rA),
791 "clz\t$rT, $rA", IntegerOp,
795 RRForm_1<0b10100101010, (outs R32C:$rT), (ins R32C:$rA),
796 "clz\t$rT, $rA", IntegerOp,
797 [(set R32C:$rT, (ctlz R32C:$rA))]>;
799 // cntb: Count ones in bytes (aka "population count")
800 // NOTE: This instruction is really a vector instruction, but the custom
801 // lowering code uses it in unorthodox ways to support CTPOP for other
804 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
805 "cntb\t$rT, $rA", IntegerOp,
806 [(set (v16i8 VECREG:$rT), (SPUcntb_v16i8 (v16i8 VECREG:$rA)))]>;
809 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
810 "cntb\t$rT, $rA", IntegerOp,
811 [(set (v8i16 VECREG:$rT), (SPUcntb_v8i16 (v8i16 VECREG:$rA)))]>;
814 RRForm_1<0b00101101010, (outs VECREG:$rT), (ins VECREG:$rA),
815 "cntb\t$rT, $rA", IntegerOp,
816 [(set (v4i32 VECREG:$rT), (SPUcntb_v4i32 (v4i32 VECREG:$rA)))]>;
818 // gbb: Gather all low order bits from each byte in $rA into a single 16-bit
819 // quantity stored into $rT
821 RRForm_1<0b01001101100, (outs R16C:$rT), (ins VECREG:$rA),
822 "gbb\t$rT, $rA", GatherOp,
825 // gbh: Gather all low order bits from each halfword in $rA into a single
826 // 8-bit quantity stored in $rT
828 RRForm_1<0b10001101100, (outs R16C:$rT), (ins VECREG:$rA),
829 "gbh\t$rT, $rA", GatherOp,
832 // gb: Gather all low order bits from each word in $rA into a single
833 // 4-bit quantity stored in $rT
835 RRForm_1<0b00001101100, (outs R16C:$rT), (ins VECREG:$rA),
836 "gb\t$rT, $rA", GatherOp,
839 // avgb: average bytes
841 RRForm<0b11001011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
842 "avgb\t$rT, $rA, $rB", ByteOp,
845 // absdb: absolute difference of bytes
847 RRForm<0b11001010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
848 "absdb\t$rT, $rA, $rB", ByteOp,
851 // sumb: sum bytes into halfwords
853 RRForm<0b11001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
854 "sumb\t$rT, $rA, $rB", ByteOp,
857 // Sign extension operations:
859 RRForm_1<0b01101101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
860 "xsbh\t$rDst, $rSrc", IntegerOp,
861 [(set (v8i16 VECREG:$rDst), (sext (v16i8 VECREG:$rSrc)))]>;
863 // Ordinary form for XSBH
865 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R16C:$rSrc),
866 "xsbh\t$rDst, $rSrc", IntegerOp,
867 [(set R16C:$rDst, (sext_inreg R16C:$rSrc, i8))]>;
870 RRForm_1<0b01101101010, (outs R16C:$rDst), (ins R8C:$rSrc),
871 "xsbh\t$rDst, $rSrc", IntegerOp,
872 [(set R16C:$rDst, (sext R8C:$rSrc))]>;
874 // 32-bit form for XSBH: used to sign extend 8-bit quantities to 16-bit
875 // quantities to 32-bit quantities via a 32-bit register (see the sext 8->32
876 // pattern below). Intentionally doesn't match a pattern because we want the
877 // sext 8->32 pattern to do the work for us, namely because we need the extra
880 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
881 "xsbh\t$rDst, $rSrc", IntegerOp,
882 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i8))]>;
884 // Sign extend halfwords to words:
886 RRForm_1<0b01101101010, (outs VECREG:$rDest), (ins VECREG:$rSrc),
887 "xshw\t$rDest, $rSrc", IntegerOp,
888 [(set (v4i32 VECREG:$rDest), (sext (v8i16 VECREG:$rSrc)))]>;
891 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R32C:$rSrc),
892 "xshw\t$rDst, $rSrc", IntegerOp,
893 [(set R32C:$rDst, (sext_inreg R32C:$rSrc, i16))]>;
896 RRForm_1<0b01101101010, (outs R32C:$rDst), (ins R16C:$rSrc),
897 "xshw\t$rDst, $rSrc", IntegerOp,
898 [(set R32C:$rDst, (sext R16C:$rSrc))]>;
901 RRForm_1<0b01100101010, (outs VECREG:$rDst), (ins VECREG:$rSrc),
902 "xswd\t$rDst, $rSrc", IntegerOp,
903 [(set (v2i64 VECREG:$rDst), (sext (v4i32 VECREG:$rSrc)))]>;
906 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R64C:$rSrc),
907 "xswd\t$rDst, $rSrc", IntegerOp,
908 [(set R64C:$rDst, (sext_inreg R64C:$rSrc, i32))]>;
911 RRForm_1<0b01100101010, (outs R64C:$rDst), (ins R32C:$rSrc),
912 "xswd\t$rDst, $rSrc", IntegerOp,
913 [(set R64C:$rDst, (SPUsext32_to_64 R32C:$rSrc))]>;
915 def : Pat<(sext R32C:$inp),
916 (XSWDr32 R32C:$inp)>;
920 class ANDInst<dag OOL, dag IOL, list<dag> pattern> :
921 RRForm<0b10000011000, OOL, IOL, "and\t$rT, $rA, $rB",
924 class ANDVecInst<ValueType vectype>:
925 ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
926 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
927 (vectype VECREG:$rB)))]>;
929 multiclass BitwiseAnd
931 def v16i8: ANDVecInst<v16i8>;
932 def v8i16: ANDVecInst<v8i16>;
933 def v4i32: ANDVecInst<v4i32>;
934 def v2i64: ANDVecInst<v2i64>;
936 def r64: ANDInst<(outs R64C:$rT), (ins R64C:$rA, R64C:$rB),
937 [(set R64C:$rT, (and R64C:$rA, R64C:$rB))]>;
939 def r32: ANDInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
940 [(set R32C:$rT, (and R32C:$rA, R32C:$rB))]>;
942 def r16: ANDInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
943 [(set R16C:$rT, (and R16C:$rA, R16C:$rB))]>;
945 def r8: ANDInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
946 [(set R8C:$rT, (and R8C:$rA, R8C:$rB))]>;
948 //===---------------------------------------------
949 // Special instructions to perform the fabs instruction
950 def fabs32: ANDInst<(outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
951 [/* Intentionally does not match a pattern */]>;
953 def fabs64: ANDInst<(outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
954 [/* Intentionally does not match a pattern */]>;
956 // Could use v4i32, but won't for clarity
957 def fabsvec: ANDInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
958 [/* Intentionally does not match a pattern */]>;
960 //===---------------------------------------------
962 // Hacked form of AND to zero-extend 16-bit quantities to 32-bit
963 // quantities -- see 16->32 zext pattern.
965 // This pattern is somewhat artificial, since it might match some
966 // compiler generated pattern but it is unlikely to do so.
968 def i16i32: ANDInst<(outs R32C:$rT), (ins R16C:$rA, R32C:$rB),
969 [(set R32C:$rT, (and (zext R16C:$rA), R32C:$rB))]>;
972 defm AND : BitwiseAnd;
974 // N.B.: vnot_conv is one of those special target selection pattern fragments,
975 // in which we expect there to be a bit_convert on the constant. Bear in mind
976 // that llvm translates "not <reg>" to "xor <reg>, -1" (or in this case, a
977 // constant -1 vector.)
979 class ANDCInst<dag OOL, dag IOL, list<dag> pattern>:
980 RRForm<0b10000011010, OOL, IOL, "andc\t$rT, $rA, $rB",
983 class ANDCVecInst<ValueType vectype>:
984 ANDCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
985 [(set (vectype VECREG:$rT), (and (vectype VECREG:$rA),
986 (vnot (vectype VECREG:$rB))))]>;
988 class ANDCRegInst<RegisterClass rclass>:
989 ANDCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
990 [(set rclass:$rT, (and rclass:$rA, (not rclass:$rB)))]>;
992 multiclass AndComplement
994 def v16i8: ANDCVecInst<v16i8>;
995 def v8i16: ANDCVecInst<v8i16>;
996 def v4i32: ANDCVecInst<v4i32>;
997 def v2i64: ANDCVecInst<v2i64>;
999 def r128: ANDCRegInst<GPRC>;
1000 def r64: ANDCRegInst<R64C>;
1001 def r32: ANDCRegInst<R32C>;
1002 def r16: ANDCRegInst<R16C>;
1003 def r8: ANDCRegInst<R8C>;
1006 defm ANDC : AndComplement;
1008 class ANDBIInst<dag OOL, dag IOL, list<dag> pattern>:
1009 RI10Form<0b01101000, OOL, IOL, "andbi\t$rT, $rA, $val",
1010 IntegerOp, pattern>;
1012 multiclass AndByteImm
1014 def v16i8: ANDBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1015 [(set (v16i8 VECREG:$rT),
1016 (and (v16i8 VECREG:$rA),
1017 (v16i8 v16i8U8Imm:$val)))]>;
1019 def r8: ANDBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1020 [(set R8C:$rT, (and R8C:$rA, immU8:$val))]>;
1023 defm ANDBI : AndByteImm;
1025 class ANDHIInst<dag OOL, dag IOL, list<dag> pattern> :
1026 RI10Form<0b10101000, OOL, IOL, "andhi\t$rT, $rA, $val",
1027 IntegerOp, pattern>;
1029 multiclass AndHalfwordImm
1031 def v8i16: ANDHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1032 [(set (v8i16 VECREG:$rT),
1033 (and (v8i16 VECREG:$rA), v8i16SExt10Imm:$val))]>;
1035 def r16: ANDHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1036 [(set R16C:$rT, (and R16C:$rA, i16ImmUns10:$val))]>;
1038 // Zero-extend i8 to i16:
1039 def i8i16: ANDHIInst<(outs R16C:$rT), (ins R8C:$rA, u10imm:$val),
1040 [(set R16C:$rT, (and (zext R8C:$rA), i16ImmUns10:$val))]>;
1043 defm ANDHI : AndHalfwordImm;
1045 class ANDIInst<dag OOL, dag IOL, list<dag> pattern> :
1046 RI10Form<0b00101000, OOL, IOL, "andi\t$rT, $rA, $val",
1047 IntegerOp, pattern>;
1049 multiclass AndWordImm
1051 def v4i32: ANDIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
1052 [(set (v4i32 VECREG:$rT),
1053 (and (v4i32 VECREG:$rA), v4i32SExt10Imm:$val))]>;
1055 def r32: ANDIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1056 [(set R32C:$rT, (and R32C:$rA, i32ImmSExt10:$val))]>;
1058 // Hacked form of ANDI to zero-extend i8 quantities to i32. See the zext 8->32
1060 def i8i32: ANDIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1062 (and (zext R8C:$rA), i32ImmSExt10:$val))]>;
1064 // Hacked form of ANDI to zero-extend i16 quantities to i32. See the
1065 // zext 16->32 pattern below.
1067 // Note that this pattern is somewhat artificial, since it might match
1068 // something the compiler generates but is unlikely to occur in practice.
1069 def i16i32: ANDIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1071 (and (zext R16C:$rA), i32ImmSExt10:$val))]>;
1074 defm ANDI : AndWordImm;
1076 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1077 // Bitwise OR group:
1078 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
1080 // Bitwise "or" (N.B.: These are also register-register copy instructions...)
1081 class ORInst<dag OOL, dag IOL, list<dag> pattern>:
1082 RRForm<0b10000010000, OOL, IOL, "or\t$rT, $rA, $rB",
1083 IntegerOp, pattern>;
1085 class ORVecInst<ValueType vectype>:
1086 ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1087 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1088 (vectype VECREG:$rB)))]>;
1090 class ORRegInst<RegisterClass rclass>:
1091 ORInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1092 [(set rclass:$rT, (or rclass:$rA, rclass:$rB))]>;
1094 class ORPromoteScalar<RegisterClass rclass>:
1095 ORInst<(outs VECREG:$rT), (ins rclass:$rA, rclass:$rB),
1096 [/* no pattern */]>;
1098 class ORExtractElt<RegisterClass rclass>:
1099 ORInst<(outs rclass:$rT), (ins VECREG:$rA, VECREG:$rB),
1100 [/* no pattern */]>;
1102 multiclass BitwiseOr
1104 def v16i8: ORVecInst<v16i8>;
1105 def v8i16: ORVecInst<v8i16>;
1106 def v4i32: ORVecInst<v4i32>;
1107 def v2i64: ORVecInst<v2i64>;
1109 def v4f32: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1110 [(set (v4f32 VECREG:$rT),
1111 (v4f32 (bitconvert (or (v4i32 VECREG:$rA),
1112 (v4i32 VECREG:$rB)))))]>;
1114 def v2f64: ORInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1115 [(set (v2f64 VECREG:$rT),
1116 (v2f64 (bitconvert (or (v2i64 VECREG:$rA),
1117 (v2i64 VECREG:$rB)))))]>;
1119 def r64: ORRegInst<R64C>;
1120 def r32: ORRegInst<R32C>;
1121 def r16: ORRegInst<R16C>;
1122 def r8: ORRegInst<R8C>;
1124 // OR instructions used to copy f32 and f64 registers.
1125 def f32: ORInst<(outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
1126 [/* no pattern */]>;
1128 def f64: ORInst<(outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
1129 [/* no pattern */]>;
1131 // scalar->vector promotion:
1132 def v16i8_i8: ORPromoteScalar<R8C>;
1133 def v8i16_i16: ORPromoteScalar<R16C>;
1134 def v4i32_i32: ORPromoteScalar<R32C>;
1135 def v2i64_i64: ORPromoteScalar<R64C>;
1136 def v4f32_f32: ORPromoteScalar<R32FP>;
1137 def v2f64_f64: ORPromoteScalar<R64FP>;
1139 // extract element 0:
1140 def i8_v16i8: ORExtractElt<R8C>;
1141 def i16_v8i16: ORExtractElt<R16C>;
1142 def i32_v4i32: ORExtractElt<R32C>;
1143 def i64_v2i64: ORExtractElt<R64C>;
1144 def f32_v4f32: ORExtractElt<R32FP>;
1145 def f64_v2f64: ORExtractElt<R64FP>;
1148 defm OR : BitwiseOr;
1150 // scalar->vector promotion patterns:
1151 def : Pat<(v16i8 (SPUpromote_scalar R8C:$rA)),
1152 (ORv16i8_i8 R8C:$rA, R8C:$rA)>;
1154 def : Pat<(v8i16 (SPUpromote_scalar R16C:$rA)),
1155 (ORv8i16_i16 R16C:$rA, R16C:$rA)>;
1157 def : Pat<(v4i32 (SPUpromote_scalar R32C:$rA)),
1158 (ORv4i32_i32 R32C:$rA, R32C:$rA)>;
1160 def : Pat<(v2i64 (SPUpromote_scalar R64C:$rA)),
1161 (ORv2i64_i64 R64C:$rA, R64C:$rA)>;
1163 def : Pat<(v4f32 (SPUpromote_scalar R32FP:$rA)),
1164 (ORv4f32_f32 R32FP:$rA, R32FP:$rA)>;
1166 def : Pat<(v2f64 (SPUpromote_scalar R64FP:$rA)),
1167 (ORv2f64_f64 R64FP:$rA, R64FP:$rA)>;
1169 // ORi*_v*: Used to extract vector element 0 (the preferred slot)
1171 def : Pat<(SPUextract_elt0 (v16i8 VECREG:$rA)),
1172 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1174 def : Pat<(SPUextract_elt0_chained (v16i8 VECREG:$rA)),
1175 (ORi8_v16i8 VECREG:$rA, VECREG:$rA)>;
1177 def : Pat<(SPUextract_elt0 (v8i16 VECREG:$rA)),
1178 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1180 def : Pat<(SPUextract_elt0_chained (v8i16 VECREG:$rA)),
1181 (ORi16_v8i16 VECREG:$rA, VECREG:$rA)>;
1183 def : Pat<(SPUextract_elt0 (v4i32 VECREG:$rA)),
1184 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1186 def : Pat<(SPUextract_elt0_chained (v4i32 VECREG:$rA)),
1187 (ORi32_v4i32 VECREG:$rA, VECREG:$rA)>;
1189 def : Pat<(SPUextract_elt0 (v2i64 VECREG:$rA)),
1190 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1192 def : Pat<(SPUextract_elt0_chained (v2i64 VECREG:$rA)),
1193 (ORi64_v2i64 VECREG:$rA, VECREG:$rA)>;
1195 def : Pat<(SPUextract_elt0 (v4f32 VECREG:$rA)),
1196 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1198 def : Pat<(SPUextract_elt0_chained (v4f32 VECREG:$rA)),
1199 (ORf32_v4f32 VECREG:$rA, VECREG:$rA)>;
1201 def : Pat<(SPUextract_elt0 (v2f64 VECREG:$rA)),
1202 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1204 def : Pat<(SPUextract_elt0_chained (v2f64 VECREG:$rA)),
1205 (ORf64_v2f64 VECREG:$rA, VECREG:$rA)>;
1207 // ORC: Bitwise "or" with complement (c = a | ~b)
1209 class ORCInst<dag OOL, dag IOL, list<dag> pattern>:
1210 RRForm<0b10010010000, OOL, IOL, "orc\t$rT, $rA, $rB",
1211 IntegerOp, pattern>;
1213 class ORCVecInst<ValueType vectype>:
1214 ORCInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1215 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1216 (vnot (vectype VECREG:$rB))))]>;
1218 class ORCRegInst<RegisterClass rclass>:
1219 ORCInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
1220 [(set rclass:$rT, (or rclass:$rA, (not rclass:$rB)))]>;
1222 multiclass BitwiseOrComplement
1224 def v16i8: ORCVecInst<v16i8>;
1225 def v8i16: ORCVecInst<v8i16>;
1226 def v4i32: ORCVecInst<v4i32>;
1227 def v2i64: ORCVecInst<v2i64>;
1229 def r64: ORCRegInst<R64C>;
1230 def r32: ORCRegInst<R32C>;
1231 def r16: ORCRegInst<R16C>;
1232 def r8: ORCRegInst<R8C>;
1235 defm ORC : BitwiseOrComplement;
1237 // OR byte immediate
1238 class ORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1239 RI10Form<0b01100000, OOL, IOL, "orbi\t$rT, $rA, $val",
1240 IntegerOp, pattern>;
1242 class ORBIVecInst<ValueType vectype, PatLeaf immpred>:
1243 ORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1244 [(set (v16i8 VECREG:$rT), (or (vectype VECREG:$rA),
1245 (vectype immpred:$val)))]>;
1247 multiclass BitwiseOrByteImm
1249 def v16i8: ORBIVecInst<v16i8, v16i8U8Imm>;
1251 def r8: ORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1252 [(set R8C:$rT, (or R8C:$rA, immU8:$val))]>;
1255 defm ORBI : BitwiseOrByteImm;
1257 // OR halfword immediate
1258 class ORHIInst<dag OOL, dag IOL, list<dag> pattern>:
1259 RI10Form<0b10100000, OOL, IOL, "orhi\t$rT, $rA, $val",
1260 IntegerOp, pattern>;
1262 class ORHIVecInst<ValueType vectype, PatLeaf immpred>:
1263 ORHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1264 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1267 multiclass BitwiseOrHalfwordImm
1269 def v8i16: ORHIVecInst<v8i16, v8i16Uns10Imm>;
1271 def r16: ORHIInst<(outs R16C:$rT), (ins R16C:$rA, u10imm:$val),
1272 [(set R16C:$rT, (or R16C:$rA, i16ImmUns10:$val))]>;
1274 // Specialized ORHI form used to promote 8-bit registers to 16-bit
1275 def i8i16: ORHIInst<(outs R16C:$rT), (ins R8C:$rA, s10imm:$val),
1276 [(set R16C:$rT, (or (anyext R8C:$rA),
1277 i16ImmSExt10:$val))]>;
1280 defm ORHI : BitwiseOrHalfwordImm;
1282 class ORIInst<dag OOL, dag IOL, list<dag> pattern>:
1283 RI10Form<0b00100000, OOL, IOL, "ori\t$rT, $rA, $val",
1284 IntegerOp, pattern>;
1286 class ORIVecInst<ValueType vectype, PatLeaf immpred>:
1287 ORIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1288 [(set (vectype VECREG:$rT), (or (vectype VECREG:$rA),
1291 // Bitwise "or" with immediate
1292 multiclass BitwiseOrImm
1294 def v4i32: ORIVecInst<v4i32, v4i32Uns10Imm>;
1296 def r32: ORIInst<(outs R32C:$rT), (ins R32C:$rA, u10imm_i32:$val),
1297 [(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
1299 // i16i32: hacked version of the ori instruction to extend 16-bit quantities
1300 // to 32-bit quantities. used exclusively to match "anyext" conversions (vide
1301 // infra "anyext 16->32" pattern.)
1302 def i16i32: ORIInst<(outs R32C:$rT), (ins R16C:$rA, s10imm_i32:$val),
1303 [(set R32C:$rT, (or (anyext R16C:$rA),
1304 i32ImmSExt10:$val))]>;
1306 // i8i32: Hacked version of the ORI instruction to extend 16-bit quantities
1307 // to 32-bit quantities. Used exclusively to match "anyext" conversions (vide
1308 // infra "anyext 16->32" pattern.)
1309 def i8i32: ORIInst<(outs R32C:$rT), (ins R8C:$rA, s10imm_i32:$val),
1310 [(set R32C:$rT, (or (anyext R8C:$rA),
1311 i32ImmSExt10:$val))]>;
1314 defm ORI : BitwiseOrImm;
1316 // ORX: "or" across the vector: or's $rA's word slots leaving the result in
1317 // $rT[0], slots 1-3 are zeroed.
1319 // FIXME: Needs to match an intrinsic pattern.
1321 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1322 "orx\t$rT, $rA, $rB", IntegerOp,
1327 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1328 "xor\t$rT, $rA, $rB", IntegerOp,
1329 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
1332 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1333 "xor\t$rT, $rA, $rB", IntegerOp,
1334 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
1337 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1338 "xor\t$rT, $rA, $rB", IntegerOp,
1339 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
1342 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1343 "xor\t$rT, $rA, $rB", IntegerOp,
1344 [(set R32C:$rT, (xor R32C:$rA, R32C:$rB))]>;
1346 //==----------------------------------------------------------
1347 // Special forms for floating point instructions.
1348 // Bitwise ORs and ANDs don't make sense for normal floating
1349 // point numbers. These operations (fneg and fabs), however,
1350 // require bitwise logical ops to manipulate the sign bit.
1352 RRForm<0b10010010000, (outs R32FP:$rT), (ins R32FP:$rA, R32C:$rB),
1353 "xor\t$rT, $rA, $rB", IntegerOp,
1354 [/* Intentionally does not match a pattern, see fneg32 */]>;
1356 // KLUDGY! Better way to do this without a VECREG? bitconvert?
1357 // VECREG is assumed to contain two identical 64-bit masks, so
1358 // it doesn't matter which word we select for the xor
1360 RRForm<0b10010010000, (outs R64FP:$rT), (ins R64FP:$rA, VECREG:$rB),
1361 "xor\t$rT, $rA, $rB", IntegerOp,
1362 [/* Intentionally does not match a pattern, see fneg64 */]>;
1364 // Could use XORv4i32, but will use this for clarity
1366 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1367 "xor\t$rT, $rA, $rB", IntegerOp,
1368 [/* Intentionally does not match a pattern, see fneg{32,64} */]>;
1370 //==----------------------------------------------------------
1373 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1374 "xor\t$rT, $rA, $rB", IntegerOp,
1375 [(set R16C:$rT, (xor R16C:$rA, R16C:$rB))]>;
1378 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1379 "xor\t$rT, $rA, $rB", IntegerOp,
1380 [(set R8C:$rT, (xor R8C:$rA, R8C:$rB))]>;
1382 class XORBIInst<dag OOL, dag IOL, list<dag> pattern>:
1383 RI10Form<0b01100000, OOL, IOL, "xorbi\t$rT, $rA, $val",
1384 IntegerOp, pattern>;
1386 multiclass XorByteImm
1389 XORBIInst<(outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1390 [(set (v16i8 VECREG:$rT), (xor (v16i8 VECREG:$rA), v16i8U8Imm:$val))]>;
1393 XORBIInst<(outs R8C:$rT), (ins R8C:$rA, u10imm_i8:$val),
1394 [(set R8C:$rT, (xor R8C:$rA, immU8:$val))]>;
1397 defm XORBI : XorByteImm;
1400 RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1401 "xorhi\t$rT, $rA, $val", IntegerOp,
1402 [(set (v8i16 VECREG:$rT), (xor (v8i16 VECREG:$rA),
1403 v8i16SExt10Imm:$val))]>;
1406 RI10Form<0b10100000, (outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
1407 "xorhi\t$rT, $rA, $val", IntegerOp,
1408 [(set R16C:$rT, (xor R16C:$rA, i16ImmSExt10:$val))]>;
1411 RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm:$val),
1412 "xori\t$rT, $rA, $val", IntegerOp,
1413 [(set (v4i32 VECREG:$rT), (xor (v4i32 VECREG:$rA),
1414 v4i32SExt10Imm:$val))]>;
1417 RI10Form<0b00100000, (outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
1418 "xori\t$rT, $rA, $val", IntegerOp,
1419 [(set R32C:$rT, (xor R32C:$rA, i32ImmSExt10:$val))]>;
1423 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1424 "nand\t$rT, $rA, $rB", IntegerOp,
1425 [(set (v16i8 VECREG:$rT), (vnot (and (v16i8 VECREG:$rA),
1426 (v16i8 VECREG:$rB))))]>;
1429 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1430 "nand\t$rT, $rA, $rB", IntegerOp,
1431 [(set (v8i16 VECREG:$rT), (vnot (and (v8i16 VECREG:$rA),
1432 (v8i16 VECREG:$rB))))]>;
1435 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1436 "nand\t$rT, $rA, $rB", IntegerOp,
1437 [(set (v4i32 VECREG:$rT), (vnot (and (v4i32 VECREG:$rA),
1438 (v4i32 VECREG:$rB))))]>;
1441 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1442 "nand\t$rT, $rA, $rB", IntegerOp,
1443 [(set R32C:$rT, (not (and R32C:$rA, R32C:$rB)))]>;
1446 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1447 "nand\t$rT, $rA, $rB", IntegerOp,
1448 [(set R16C:$rT, (not (and R16C:$rA, R16C:$rB)))]>;
1451 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1452 "nand\t$rT, $rA, $rB", IntegerOp,
1453 [(set R8C:$rT, (not (and R8C:$rA, R8C:$rB)))]>;
1457 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1458 "nor\t$rT, $rA, $rB", IntegerOp,
1459 [(set (v16i8 VECREG:$rT), (vnot (or (v16i8 VECREG:$rA),
1460 (v16i8 VECREG:$rB))))]>;
1463 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1464 "nor\t$rT, $rA, $rB", IntegerOp,
1465 [(set (v8i16 VECREG:$rT), (vnot (or (v8i16 VECREG:$rA),
1466 (v8i16 VECREG:$rB))))]>;
1469 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1470 "nor\t$rT, $rA, $rB", IntegerOp,
1471 [(set (v4i32 VECREG:$rT), (vnot (or (v4i32 VECREG:$rA),
1472 (v4i32 VECREG:$rB))))]>;
1475 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1476 "nor\t$rT, $rA, $rB", IntegerOp,
1477 [(set R32C:$rT, (not (or R32C:$rA, R32C:$rB)))]>;
1480 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1481 "nor\t$rT, $rA, $rB", IntegerOp,
1482 [(set R16C:$rT, (not (or R16C:$rA, R16C:$rB)))]>;
1485 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1486 "nor\t$rT, $rA, $rB", IntegerOp,
1487 [(set R8C:$rT, (not (or R8C:$rA, R8C:$rB)))]>;
1489 // EQV: Equivalence (1 for each same bit, otherwise 0)
1491 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1492 "eqv\t$rT, $rA, $rB", IntegerOp,
1493 [(set (v16i8 VECREG:$rT), (or (and (v16i8 VECREG:$rA),
1494 (v16i8 VECREG:$rB)),
1495 (and (vnot (v16i8 VECREG:$rA)),
1496 (vnot (v16i8 VECREG:$rB)))))]>;
1498 def : Pat<(xor (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rB))),
1499 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1501 def : Pat<(xor (vnot (v16i8 VECREG:$rA)), (v16i8 VECREG:$rB)),
1502 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1505 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1506 "eqv\t$rT, $rA, $rB", IntegerOp,
1507 [(set (v8i16 VECREG:$rT), (or (and (v8i16 VECREG:$rA),
1508 (v8i16 VECREG:$rB)),
1509 (and (vnot (v8i16 VECREG:$rA)),
1510 (vnot (v8i16 VECREG:$rB)))))]>;
1512 def : Pat<(xor (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rB))),
1513 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1515 def : Pat<(xor (vnot (v8i16 VECREG:$rA)), (v8i16 VECREG:$rB)),
1516 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1519 RRForm<0b10010010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
1520 "eqv\t$rT, $rA, $rB", IntegerOp,
1521 [(set (v4i32 VECREG:$rT), (or (and (v4i32 VECREG:$rA),
1522 (v4i32 VECREG:$rB)),
1523 (and (vnot (v4i32 VECREG:$rA)),
1524 (vnot (v4i32 VECREG:$rB)))))]>;
1526 def : Pat<(xor (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rB))),
1527 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1529 def : Pat<(xor (vnot (v4i32 VECREG:$rA)), (v4i32 VECREG:$rB)),
1530 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1533 RRForm<0b10010010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
1534 "eqv\t$rT, $rA, $rB", IntegerOp,
1535 [(set R32C:$rT, (or (and R32C:$rA, R32C:$rB),
1536 (and (not R32C:$rA), (not R32C:$rB))))]>;
1538 def : Pat<(xor R32C:$rA, (not R32C:$rB)),
1539 (EQVr32 R32C:$rA, R32C:$rB)>;
1541 def : Pat<(xor (not R32C:$rA), R32C:$rB),
1542 (EQVr32 R32C:$rA, R32C:$rB)>;
1545 RRForm<0b10010010000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1546 "eqv\t$rT, $rA, $rB", IntegerOp,
1547 [(set R16C:$rT, (or (and R16C:$rA, R16C:$rB),
1548 (and (not R16C:$rA), (not R16C:$rB))))]>;
1550 def : Pat<(xor R16C:$rA, (not R16C:$rB)),
1551 (EQVr16 R16C:$rA, R16C:$rB)>;
1553 def : Pat<(xor (not R16C:$rA), R16C:$rB),
1554 (EQVr16 R16C:$rA, R16C:$rB)>;
1557 RRForm<0b10010010000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
1558 "eqv\t$rT, $rA, $rB", IntegerOp,
1559 [(set R8C:$rT, (or (and R8C:$rA, R8C:$rB),
1560 (and (not R8C:$rA), (not R8C:$rB))))]>;
1562 def : Pat<(xor R8C:$rA, (not R8C:$rB)),
1563 (EQVr8 R8C:$rA, R8C:$rB)>;
1565 def : Pat<(xor (not R8C:$rA), R8C:$rB),
1566 (EQVr8 R8C:$rA, R8C:$rB)>;
1568 // gcc optimizes (p & q) | (~p & ~q) -> ~(p | q) | (p & q), so match that
1570 def : Pat<(or (vnot (or (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))),
1571 (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rB))),
1572 (EQVv16i8 VECREG:$rA, VECREG:$rB)>;
1574 def : Pat<(or (vnot (or (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))),
1575 (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rB))),
1576 (EQVv8i16 VECREG:$rA, VECREG:$rB)>;
1578 def : Pat<(or (vnot (or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))),
1579 (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB))),
1580 (EQVv4i32 VECREG:$rA, VECREG:$rB)>;
1582 def : Pat<(or (not (or R32C:$rA, R32C:$rB)), (and R32C:$rA, R32C:$rB)),
1583 (EQVr32 R32C:$rA, R32C:$rB)>;
1585 def : Pat<(or (not (or R16C:$rA, R16C:$rB)), (and R16C:$rA, R16C:$rB)),
1586 (EQVr16 R16C:$rA, R16C:$rB)>;
1588 def : Pat<(or (not (or R8C:$rA, R8C:$rB)), (and R8C:$rA, R8C:$rB)),
1589 (EQVr8 R8C:$rA, R8C:$rB)>;
1593 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1594 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1595 [(set (v16i8 VECREG:$rT),
1596 (SPUselb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB),
1597 (v16i8 VECREG:$rC)))]>;
1599 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1600 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1601 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1603 def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1604 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1605 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1607 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1608 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1609 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1611 def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1612 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1613 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1615 def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1616 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1617 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1619 def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1620 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1621 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1623 def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1624 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1625 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1627 def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1628 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1629 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1631 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1632 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1633 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1635 def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1636 (and (v16i8 VECREG:$rB), (vnot (v16i8 VECREG:$rC)))),
1637 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1639 def : Pat<(or (and (v16i8 VECREG:$rA), (v16i8 VECREG:$rC)),
1640 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1641 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1643 def : Pat<(or (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rA)),
1644 (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rB))),
1645 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1647 def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1648 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1649 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1651 def : Pat<(or (and (v16i8 VECREG:$rA), (vnot (v16i8 VECREG:$rC))),
1652 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1653 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1655 def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1656 (and (v16i8 VECREG:$rB), (v16i8 VECREG:$rC))),
1657 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1659 def : Pat<(or (and (vnot (v16i8 VECREG:$rC)), (v16i8 VECREG:$rA)),
1660 (and (v16i8 VECREG:$rC), (v16i8 VECREG:$rB))),
1661 (SELBv16i8 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1664 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1665 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1666 [(set (v8i16 VECREG:$rT),
1667 (SPUselb (v8i16 VECREG:$rA), (v8i16 VECREG:$rB),
1668 (v8i16 VECREG:$rC)))]>;
1670 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1671 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1672 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1674 def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1675 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1676 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1678 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1679 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1680 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1682 def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1683 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1684 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1686 def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1687 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1688 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1690 def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1691 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1692 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1694 def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1695 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1696 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1698 def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1699 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1700 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1702 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1703 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1704 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1706 def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1707 (and (v8i16 VECREG:$rB), (vnot (v8i16 VECREG:$rC)))),
1708 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1710 def : Pat<(or (and (v8i16 VECREG:$rA), (v8i16 VECREG:$rC)),
1711 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1712 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1714 def : Pat<(or (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rA)),
1715 (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rB))),
1716 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1718 def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1719 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1720 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1722 def : Pat<(or (and (v8i16 VECREG:$rA), (vnot (v8i16 VECREG:$rC))),
1723 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1724 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1726 def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1727 (and (v8i16 VECREG:$rB), (v8i16 VECREG:$rC))),
1728 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1730 def : Pat<(or (and (vnot (v8i16 VECREG:$rC)), (v8i16 VECREG:$rA)),
1731 (and (v8i16 VECREG:$rC), (v8i16 VECREG:$rB))),
1732 (SELBv8i16 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1735 RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1736 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1737 [(set (v4i32 VECREG:$rT),
1738 (SPUselb (v4i32 VECREG:$rA), (v4i32 VECREG:$rB),
1739 (v4i32 VECREG:$rC)))]>;
1741 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1742 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1743 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1745 def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1746 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1747 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1749 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1750 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1751 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1753 def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1754 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1755 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1757 def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1758 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1759 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1761 def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1762 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1763 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1765 def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1766 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1767 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1769 def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1770 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1771 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1773 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1774 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1775 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1777 def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1778 (and (v4i32 VECREG:$rB), (vnot (v4i32 VECREG:$rC)))),
1779 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1781 def : Pat<(or (and (v4i32 VECREG:$rA), (v4i32 VECREG:$rC)),
1782 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1783 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1785 def : Pat<(or (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rA)),
1786 (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rB))),
1787 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1789 def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1790 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1791 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1793 def : Pat<(or (and (v4i32 VECREG:$rA), (vnot (v4i32 VECREG:$rC))),
1794 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1795 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1797 def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1798 (and (v4i32 VECREG:$rB), (v4i32 VECREG:$rC))),
1799 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1801 def : Pat<(or (and (vnot (v4i32 VECREG:$rC)), (v4i32 VECREG:$rA)),
1802 (and (v4i32 VECREG:$rC), (v4i32 VECREG:$rB))),
1803 (SELBv4i32 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1806 RRRForm<0b1000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB, R32C:$rC),
1807 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1810 // And the various patterns that can be matched... (all 8 of them :-)
1811 def : Pat<(or (and R32C:$rA, R32C:$rC),
1812 (and R32C:$rB, (not R32C:$rC))),
1813 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1815 def : Pat<(or (and R32C:$rC, R32C:$rA),
1816 (and R32C:$rB, (not R32C:$rC))),
1817 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1819 def : Pat<(or (and R32C:$rA, R32C:$rC),
1820 (and (not R32C:$rC), R32C:$rB)),
1821 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1823 def : Pat<(or (and R32C:$rC, R32C:$rA),
1824 (and (not R32C:$rC), R32C:$rB)),
1825 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1827 def : Pat<(or (and R32C:$rA, (not R32C:$rC)),
1828 (and R32C:$rB, R32C:$rC)),
1829 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1831 def : Pat<(or (and R32C:$rA, (not R32C:$rC)),
1832 (and R32C:$rC, R32C:$rB)),
1833 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1835 def : Pat<(or (and (not R32C:$rC), R32C:$rA),
1836 (and R32C:$rB, R32C:$rC)),
1837 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1839 def : Pat<(or (and (not R32C:$rC), R32C:$rA),
1840 (and R32C:$rC, R32C:$rB)),
1841 (SELBr32 R32C:$rA, R32C:$rB, R32C:$rC)>;
1844 RRRForm<0b1000, (outs R16C:$rT), (ins R16C:$rA, R16C:$rB, R16C:$rC),
1845 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1848 def : Pat<(or (and R16C:$rA, R16C:$rC),
1849 (and R16C:$rB, (not R16C:$rC))),
1850 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1852 def : Pat<(or (and R16C:$rC, R16C:$rA),
1853 (and R16C:$rB, (not R16C:$rC))),
1854 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1856 def : Pat<(or (and R16C:$rA, R16C:$rC),
1857 (and (not R16C:$rC), R16C:$rB)),
1858 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1860 def : Pat<(or (and R16C:$rC, R16C:$rA),
1861 (and (not R16C:$rC), R16C:$rB)),
1862 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1864 def : Pat<(or (and R16C:$rA, (not R16C:$rC)),
1865 (and R16C:$rB, R16C:$rC)),
1866 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1868 def : Pat<(or (and R16C:$rA, (not R16C:$rC)),
1869 (and R16C:$rC, R16C:$rB)),
1870 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1872 def : Pat<(or (and (not R16C:$rC), R16C:$rA),
1873 (and R16C:$rB, R16C:$rC)),
1874 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1876 def : Pat<(or (and (not R16C:$rC), R16C:$rA),
1877 (and R16C:$rC, R16C:$rB)),
1878 (SELBr16 R16C:$rA, R16C:$rB, R16C:$rC)>;
1881 RRRForm<0b1000, (outs R8C:$rT), (ins R8C:$rA, R8C:$rB, R8C:$rC),
1882 "selb\t$rT, $rA, $rB, $rC", IntegerOp,
1885 def : Pat<(or (and R8C:$rA, R8C:$rC),
1886 (and R8C:$rB, (not R8C:$rC))),
1887 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
1889 def : Pat<(or (and R8C:$rC, R8C:$rA),
1890 (and R8C:$rB, (not R8C:$rC))),
1891 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
1893 def : Pat<(or (and R8C:$rA, R8C:$rC),
1894 (and (not R8C:$rC), R8C:$rB)),
1895 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
1897 def : Pat<(or (and R8C:$rC, R8C:$rA),
1898 (and (not R8C:$rC), R8C:$rB)),
1899 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
1901 def : Pat<(or (and R8C:$rA, (not R8C:$rC)),
1902 (and R8C:$rB, R8C:$rC)),
1903 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
1905 def : Pat<(or (and R8C:$rA, (not R8C:$rC)),
1906 (and R8C:$rC, R8C:$rB)),
1907 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
1909 def : Pat<(or (and (not R8C:$rC), R8C:$rA),
1910 (and R8C:$rB, R8C:$rC)),
1911 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
1913 def : Pat<(or (and (not R8C:$rC), R8C:$rA),
1914 (and R8C:$rC, R8C:$rB)),
1915 (SELBr8 R8C:$rA, R8C:$rB, R8C:$rC)>;
1917 //===----------------------------------------------------------------------===//
1918 // Vector shuffle...
1919 //===----------------------------------------------------------------------===//
1920 // SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
1921 // See the SPUshuffle SDNode operand above, which sets up the DAG pattern
1922 // matcher to emit something when the LowerVECTOR_SHUFFLE generates a node with
1923 // the SPUISD::SHUFB opcode.
1924 //===----------------------------------------------------------------------===//
1926 class SHUFBInst<dag OOL, dag IOL, list<dag> pattern>:
1927 RRRForm<0b1000, OOL, IOL, "shufb\t$rT, $rA, $rB, $rC",
1928 IntegerOp, pattern>;
1930 class SHUFBVecInst<ValueType vectype>:
1931 SHUFBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
1932 [(set (vectype VECREG:$rT), (SPUshuffle (vectype VECREG:$rA),
1933 (vectype VECREG:$rB),
1934 (vectype VECREG:$rC)))]>;
1936 // It's this pattern that's probably the most useful, since SPUISelLowering
1937 // methods create a v16i8 vector for $rC:
1938 class SHUFBVecPat1<ValueType vectype, SPUInstr inst>:
1939 Pat<(SPUshuffle (vectype VECREG:$rA), (vectype VECREG:$rB),
1940 (v16i8 VECREG:$rC)),
1941 (inst VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
1943 multiclass ShuffleBytes
1945 def v16i8 : SHUFBVecInst<v16i8>;
1946 def v8i16 : SHUFBVecInst<v8i16>;
1947 def v4i32 : SHUFBVecInst<v4i32>;
1948 def v2i64 : SHUFBVecInst<v2i64>;
1950 def v4f32 : SHUFBVecInst<v4f32>;
1951 def v2f64 : SHUFBVecInst<v2f64>;
1954 defm SHUFB : ShuffleBytes;
1956 def : SHUFBVecPat1<v8i16, SHUFBv16i8>;
1957 def : SHUFBVecPat1<v4i32, SHUFBv16i8>;
1958 def : SHUFBVecPat1<v2i64, SHUFBv16i8>;
1959 def : SHUFBVecPat1<v4f32, SHUFBv16i8>;
1960 def : SHUFBVecPat1<v2f64, SHUFBv16i8>;
1962 //===----------------------------------------------------------------------===//
1963 // Shift and rotate group:
1964 //===----------------------------------------------------------------------===//
1966 class SHLHInst<dag OOL, dag IOL, list<dag> pattern>:
1967 RRForm<0b11111010000, OOL, IOL, "shlh\t$rT, $rA, $rB",
1968 RotateShift, pattern>;
1970 class SHLHVecInst<ValueType vectype>:
1971 SHLHInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
1972 [(set (vectype VECREG:$rT),
1973 (SPUvec_shl (vectype VECREG:$rA), R16C:$rB))]>;
1975 // $rB gets promoted to 32-bit register type when confronted with
1976 // this llvm assembly code:
1978 // define i16 @shlh_i16_1(i16 %arg1, i16 %arg2) {
1979 // %A = shl i16 %arg1, %arg2
1983 multiclass ShiftLeftHalfword
1985 def v8i16: SHLHVecInst<v8i16>;
1986 def r16: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
1987 [(set R16C:$rT, (shl R16C:$rA, R16C:$rB))]>;
1988 def r16_r32: SHLHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
1989 [(set R16C:$rT, (shl R16C:$rA, R32C:$rB))]>;
1992 defm SHLH : ShiftLeftHalfword;
1994 //===----------------------------------------------------------------------===//
1996 class SHLHIInst<dag OOL, dag IOL, list<dag> pattern>:
1997 RI7Form<0b11111010000, OOL, IOL, "shlhi\t$rT, $rA, $val",
1998 RotateShift, pattern>;
2000 class SHLHIVecInst<ValueType vectype>:
2001 SHLHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2002 [(set (vectype VECREG:$rT),
2003 (SPUvec_shl (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2005 multiclass ShiftLeftHalfwordImm
2007 def v8i16: SHLHIVecInst<v8i16>;
2008 def r16: SHLHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2009 [(set R16C:$rT, (shl R16C:$rA, (i16 uimm7:$val)))]>;
2012 defm SHLHI : ShiftLeftHalfwordImm;
2014 def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
2015 (SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
2017 def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
2018 (SHLHIr16 R16C:$rA, uimm7:$val)>;
2020 //===----------------------------------------------------------------------===//
2022 class SHLInst<dag OOL, dag IOL, list<dag> pattern>:
2023 RRForm<0b11111010000, OOL, IOL, "shl\t$rT, $rA, $rB",
2024 RotateShift, pattern>;
2026 multiclass ShiftLeftWord
2029 SHLInst<(outs VECREG:$rT), (ins VECREG:$rA, R16C:$rB),
2030 [(set (v4i32 VECREG:$rT),
2031 (SPUvec_shl (v4i32 VECREG:$rA), R16C:$rB))]>;
2033 SHLInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2034 [(set R32C:$rT, (shl R32C:$rA, R32C:$rB))]>;
2037 defm SHL: ShiftLeftWord;
2039 //===----------------------------------------------------------------------===//
2041 class SHLIInst<dag OOL, dag IOL, list<dag> pattern>:
2042 RI7Form<0b11111010000, OOL, IOL, "shli\t$rT, $rA, $val",
2043 RotateShift, pattern>;
2045 multiclass ShiftLeftWordImm
2048 SHLIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2049 [(set (v4i32 VECREG:$rT),
2050 (SPUvec_shl (v4i32 VECREG:$rA), (i32 uimm7:$val)))]>;
2053 SHLIInst<(outs R32C:$rT), (ins R32C:$rA, u7imm_i32:$val),
2054 [(set R32C:$rT, (shl R32C:$rA, (i32 uimm7:$val)))]>;
2057 defm SHLI : ShiftLeftWordImm;
2059 //===----------------------------------------------------------------------===//
2060 // SHLQBI vec form: Note that this will shift the entire vector (the 128-bit
2061 // register) to the left. Vector form is here to ensure type correctness.
2063 // The shift count is in the lowest 3 bits (29-31) of $rB, so only a bit shift
2064 // of 7 bits is actually possible.
2066 // Note also that SHLQBI/SHLQBII are used in conjunction with SHLQBY/SHLQBYI
2067 // to shift i64 and i128. SHLQBI is the residual left over after shifting by
2068 // bytes with SHLQBY.
2070 class SHLQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2071 RRForm<0b11011011100, OOL, IOL, "shlqbi\t$rT, $rA, $rB",
2072 RotateShift, pattern>;
2074 class SHLQBIVecInst<ValueType vectype>:
2075 SHLQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2076 [(set (vectype VECREG:$rT),
2077 (SPUshlquad_l_bits (vectype VECREG:$rA), R32C:$rB))]>;
2079 multiclass ShiftLeftQuadByBits
2081 def v16i8: SHLQBIVecInst<v16i8>;
2082 def v8i16: SHLQBIVecInst<v8i16>;
2083 def v4i32: SHLQBIVecInst<v4i32>;
2084 def v2i64: SHLQBIVecInst<v2i64>;
2087 defm SHLQBI : ShiftLeftQuadByBits;
2089 // See note above on SHLQBI. In this case, the predicate actually does then
2090 // enforcement, whereas with SHLQBI, we have to "take it on faith."
2091 class SHLQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2092 RI7Form<0b11011111100, OOL, IOL, "shlqbii\t$rT, $rA, $val",
2093 RotateShift, pattern>;
2095 class SHLQBIIVecInst<ValueType vectype>:
2096 SHLQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2097 [(set (vectype VECREG:$rT),
2098 (SPUshlquad_l_bits (vectype VECREG:$rA), (i32 bitshift:$val)))]>;
2100 multiclass ShiftLeftQuadByBitsImm
2102 def v16i8 : SHLQBIIVecInst<v16i8>;
2103 def v8i16 : SHLQBIIVecInst<v8i16>;
2104 def v4i32 : SHLQBIIVecInst<v4i32>;
2105 def v2i64 : SHLQBIIVecInst<v2i64>;
2108 defm SHLQBII : ShiftLeftQuadByBitsImm;
2110 // SHLQBY, SHLQBYI vector forms: Shift the entire vector to the left by bytes,
2111 // not by bits. See notes above on SHLQBI.
2113 class SHLQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2114 RI7Form<0b11111011100, OOL, IOL, "shlqbyi\t$rT, $rA, $rB",
2115 RotateShift, pattern>;
2117 class SHLQBYVecInst<ValueType vectype>:
2118 SHLQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2119 [(set (vectype VECREG:$rT),
2120 (SPUshlquad_l_bytes (vectype VECREG:$rA), R32C:$rB))]>;
2122 multiclass ShiftLeftQuadBytes
2124 def v16i8: SHLQBYVecInst<v16i8>;
2125 def v8i16: SHLQBYVecInst<v8i16>;
2126 def v4i32: SHLQBYVecInst<v4i32>;
2127 def v2i64: SHLQBYVecInst<v2i64>;
2128 def r128: SHLQBYInst<(outs GPRC:$rT), (ins GPRC:$rA, R32C:$rB),
2129 [(set GPRC:$rT, (SPUshlquad_l_bytes GPRC:$rA, R32C:$rB))]>;
2132 defm SHLQBY: ShiftLeftQuadBytes;
2134 class SHLQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2135 RI7Form<0b11111111100, OOL, IOL, "shlqbyi\t$rT, $rA, $val",
2136 RotateShift, pattern>;
2138 class SHLQBYIVecInst<ValueType vectype>:
2139 SHLQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm_i32:$val),
2140 [(set (vectype VECREG:$rT),
2141 (SPUshlquad_l_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2143 multiclass ShiftLeftQuadBytesImm
2145 def v16i8: SHLQBYIVecInst<v16i8>;
2146 def v8i16: SHLQBYIVecInst<v8i16>;
2147 def v4i32: SHLQBYIVecInst<v4i32>;
2148 def v2i64: SHLQBYIVecInst<v2i64>;
2149 def r128: SHLQBYIInst<(outs GPRC:$rT), (ins GPRC:$rA, u7imm_i32:$val),
2151 (SPUshlquad_l_bytes GPRC:$rA, (i32 uimm7:$val)))]>;
2154 defm SHLQBYI : ShiftLeftQuadBytesImm;
2156 // Special form for truncating i64 to i32:
2157 def SHLQBYItrunc64: SHLQBYIInst<(outs R32C:$rT), (ins R64C:$rA, u7imm_i32:$val),
2158 [/* no pattern, see below */]>;
2160 def : Pat<(trunc R64C:$rSrc),
2161 (SHLQBYItrunc64 R64C:$rSrc, 4)>;
2163 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2165 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2166 class ROTHInst<dag OOL, dag IOL, list<dag> pattern>:
2167 RRForm<0b00111010000, OOL, IOL, "roth\t$rT, $rA, $rB",
2168 RotateShift, pattern>;
2170 class ROTHVecInst<ValueType vectype>:
2171 ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2172 [(set (vectype VECREG:$rT),
2173 (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
2175 class ROTHRegInst<RegisterClass rclass>:
2176 ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2177 [(set rclass:$rT, (rotl rclass:$rA, rclass:$rB))]>;
2179 multiclass RotateLeftHalfword
2181 def v8i16: ROTHVecInst<v8i16>;
2182 def r16: ROTHRegInst<R16C>;
2185 defm ROTH: RotateLeftHalfword;
2187 def ROTHr16_r32: ROTHInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2188 [(set R16C:$rT, (rotl R16C:$rA, R32C:$rB))]>;
2190 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2191 // Rotate halfword, immediate:
2192 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2193 class ROTHIInst<dag OOL, dag IOL, list<dag> pattern>:
2194 RI7Form<0b00111110000, OOL, IOL, "rothi\t$rT, $rA, $val",
2195 RotateShift, pattern>;
2197 class ROTHIVecInst<ValueType vectype>:
2198 ROTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2199 [(set (vectype VECREG:$rT),
2200 (SPUvec_rotl VECREG:$rA, (i16 uimm7:$val)))]>;
2202 multiclass RotateLeftHalfwordImm
2204 def v8i16: ROTHIVecInst<v8i16>;
2205 def r16: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm:$val),
2206 [(set R16C:$rT, (rotl R16C:$rA, (i16 uimm7:$val)))]>;
2207 def r16_r32: ROTHIInst<(outs R16C:$rT), (ins R16C:$rA, u7imm_i32:$val),
2208 [(set R16C:$rT, (rotl R16C:$rA, (i32 uimm7:$val)))]>;
2211 defm ROTHI: RotateLeftHalfwordImm;
2213 def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
2214 (ROTHIv8i16 VECREG:$rA, imm:$val)>;
2216 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2218 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2220 class ROTInst<dag OOL, dag IOL, list<dag> pattern>:
2221 RRForm<0b00011010000, OOL, IOL, "rot\t$rT, $rA, $rB",
2222 RotateShift, pattern>;
2224 class ROTVecInst<ValueType vectype>:
2225 ROTInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2226 [(set (vectype VECREG:$rT),
2227 (SPUvec_rotl (vectype VECREG:$rA), R32C:$rB))]>;
2229 class ROTRegInst<RegisterClass rclass>:
2230 ROTInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2232 (rotl rclass:$rA, R32C:$rB))]>;
2234 multiclass RotateLeftWord
2236 def v4i32: ROTVecInst<v4i32>;
2237 def r32: ROTRegInst<R32C>;
2240 defm ROT: RotateLeftWord;
2242 // The rotate amount is in the same bits whether we've got an 8-bit, 16-bit or
2244 def ROTr32_r16_anyext:
2245 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R16C:$rB),
2246 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R16C:$rB))))]>;
2248 def : Pat<(rotl R32C:$rA, (i32 (zext R16C:$rB))),
2249 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2251 def : Pat<(rotl R32C:$rA, (i32 (sext R16C:$rB))),
2252 (ROTr32_r16_anyext R32C:$rA, R16C:$rB)>;
2254 def ROTr32_r8_anyext:
2255 ROTInst<(outs R32C:$rT), (ins R32C:$rA, R8C:$rB),
2256 [(set R32C:$rT, (rotl R32C:$rA, (i32 (anyext R8C:$rB))))]>;
2258 def : Pat<(rotl R32C:$rA, (i32 (zext R8C:$rB))),
2259 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2261 def : Pat<(rotl R32C:$rA, (i32 (sext R8C:$rB))),
2262 (ROTr32_r8_anyext R32C:$rA, R8C:$rB)>;
2264 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2265 // Rotate word, immediate
2266 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2268 class ROTIInst<dag OOL, dag IOL, list<dag> pattern>:
2269 RI7Form<0b00011110000, OOL, IOL, "roti\t$rT, $rA, $val",
2270 RotateShift, pattern>;
2272 class ROTIVecInst<ValueType vectype, Operand optype, ValueType inttype, PatLeaf pred>:
2273 ROTIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2274 [(set (vectype VECREG:$rT),
2275 (SPUvec_rotl (vectype VECREG:$rA), (inttype pred:$val)))]>;
2277 class ROTIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2278 ROTIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2279 [(set rclass:$rT, (rotl rclass:$rA, (inttype pred:$val)))]>;
2281 multiclass RotateLeftWordImm
2283 def v4i32: ROTIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2284 def v4i32_i16: ROTIVecInst<v4i32, u7imm, i16, uimm7>;
2285 def v4i32_i8: ROTIVecInst<v4i32, u7imm_i8, i8, uimm7>;
2287 def r32: ROTIRegInst<R32C, u7imm_i32, i32, uimm7>;
2288 def r32_i16: ROTIRegInst<R32C, u7imm, i16, uimm7>;
2289 def r32_i8: ROTIRegInst<R32C, u7imm_i8, i8, uimm7>;
2292 defm ROTI : RotateLeftWordImm;
2294 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2295 // Rotate quad by byte (count)
2296 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2298 class ROTQBYInst<dag OOL, dag IOL, list<dag> pattern>:
2299 RRForm<0b00111011100, OOL, IOL, "rotqby\t$rT, $rA, $rB",
2300 RotateShift, pattern>;
2302 class ROTQBYVecInst<ValueType vectype>:
2303 ROTQBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2304 [(set (vectype VECREG:$rT),
2305 (SPUrotbytes_left (vectype VECREG:$rA), R32C:$rB))]>;
2307 multiclass RotateQuadLeftByBytes
2309 def v16i8: ROTQBYVecInst<v16i8>;
2310 def v8i16: ROTQBYVecInst<v8i16>;
2311 def v4i32: ROTQBYVecInst<v4i32>;
2312 def v2i64: ROTQBYVecInst<v2i64>;
2315 defm ROTQBY: RotateQuadLeftByBytes;
2317 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), R32C:$rB),
2318 (ROTQBYv16i8 VECREG:$rA, R32C:$rB)>;
2319 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), R32C:$rB),
2320 (ROTQBYv8i16 VECREG:$rA, R32C:$rB)>;
2321 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), R32C:$rB),
2322 (ROTQBYv4i32 VECREG:$rA, R32C:$rB)>;
2323 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), R32C:$rB),
2324 (ROTQBYv2i64 VECREG:$rA, R32C:$rB)>;
2326 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2327 // Rotate quad by byte (count), immediate
2328 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2330 class ROTQBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2331 RI7Form<0b00111111100, OOL, IOL, "rotqbyi\t$rT, $rA, $val",
2332 RotateShift, pattern>;
2334 class ROTQBYIVecInst<ValueType vectype>:
2335 ROTQBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2336 [(set (vectype VECREG:$rT),
2337 (SPUrotbytes_left (vectype VECREG:$rA), (i16 uimm7:$val)))]>;
2339 multiclass RotateQuadByBytesImm
2341 def v16i8: ROTQBYIVecInst<v16i8>;
2342 def v8i16: ROTQBYIVecInst<v8i16>;
2343 def v4i32: ROTQBYIVecInst<v4i32>;
2344 def v2i64: ROTQBYIVecInst<v2i64>;
2347 defm ROTQBYI: RotateQuadByBytesImm;
2349 def : Pat<(SPUrotbytes_left_chained (v16i8 VECREG:$rA), (i16 uimm7:$val)),
2350 (ROTQBYIv16i8 VECREG:$rA, uimm7:$val)>;
2351 def : Pat<(SPUrotbytes_left_chained (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2352 (ROTQBYIv8i16 VECREG:$rA, uimm7:$val)>;
2353 def : Pat<(SPUrotbytes_left_chained (v4i32 VECREG:$rA), (i16 uimm7:$val)),
2354 (ROTQBYIv4i32 VECREG:$rA, uimm7:$val)>;
2355 def : Pat<(SPUrotbytes_left_chained (v2i64 VECREG:$rA), (i16 uimm7:$val)),
2356 (ROTQBYIv2i64 VECREG:$rA, uimm7:$val)>;
2358 // See ROTQBY note above.
2360 RI7Form<0b00110011100, (outs VECREG:$rT), (ins VECREG:$rA, u7imm:$val),
2361 "rotqbybi\t$rT, $rA, $val", RotateShift,
2364 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2365 // See ROTQBY note above.
2367 // Assume that the user of this instruction knows to shift the rotate count
2369 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2371 class ROTQBIInst<dag OOL, dag IOL, list<dag> pattern>:
2372 RRForm<0b00011011100, OOL, IOL, "rotqbi\t$rT, $rA, $rB",
2373 RotateShift, pattern>;
2375 class ROTQBIVecInst<ValueType vectype>:
2376 ROTQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2377 [/* no pattern yet */]>;
2379 class ROTQBIRegInst<RegisterClass rclass>:
2380 ROTQBIInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),
2381 [/* no pattern yet */]>;
2383 multiclass RotateQuadByBitCount
2385 def v16i8: ROTQBIVecInst<v16i8>;
2386 def v8i16: ROTQBIVecInst<v8i16>;
2387 def v4i32: ROTQBIVecInst<v4i32>;
2388 def v2i64: ROTQBIVecInst<v2i64>;
2390 def r128: ROTQBIRegInst<GPRC>;
2391 def r64: ROTQBIRegInst<R64C>;
2394 defm ROTQBI: RotateQuadByBitCount;
2396 class ROTQBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2397 RI7Form<0b00011111100, OOL, IOL, "rotqbii\t$rT, $rA, $val",
2398 RotateShift, pattern>;
2400 class ROTQBIIVecInst<ValueType vectype, Operand optype, ValueType inttype,
2402 ROTQBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, optype:$val),
2403 [/* no pattern yet */]>;
2405 class ROTQBIIRegInst<RegisterClass rclass, Operand optype, ValueType inttype,
2407 ROTQBIIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2408 [/* no pattern yet */]>;
2410 multiclass RotateQuadByBitCountImm
2412 def v16i8: ROTQBIIVecInst<v16i8, u7imm_i32, i32, uimm7>;
2413 def v8i16: ROTQBIIVecInst<v8i16, u7imm_i32, i32, uimm7>;
2414 def v4i32: ROTQBIIVecInst<v4i32, u7imm_i32, i32, uimm7>;
2415 def v2i64: ROTQBIIVecInst<v2i64, u7imm_i32, i32, uimm7>;
2417 def r128: ROTQBIIRegInst<GPRC, u7imm_i32, i32, uimm7>;
2418 def r64: ROTQBIIRegInst<R64C, u7imm_i32, i32, uimm7>;
2421 defm ROTQBII : RotateQuadByBitCountImm;
2423 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2424 // ROTHM v8i16 form:
2425 // NOTE(1): No vector rotate is generated by the C/C++ frontend (today),
2426 // so this only matches a synthetically generated/lowered code
2428 // NOTE(2): $rB must be negated before the right rotate!
2429 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2431 class ROTHMInst<dag OOL, dag IOL, list<dag> pattern>:
2432 RRForm<0b10111010000, OOL, IOL, "rothm\t$rT, $rA, $rB",
2433 RotateShift, pattern>;
2436 ROTHMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2437 [/* see patterns below - $rB must be negated */]>;
2439 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R32C:$rB),
2440 (ROTHMv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2442 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R16C:$rB),
2443 (ROTHMv8i16 VECREG:$rA,
2444 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2446 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), R8C:$rB),
2447 (ROTHMv8i16 VECREG:$rA,
2448 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2450 // ROTHM r16 form: Rotate 16-bit quantity to right, zero fill at the left
2451 // Note: This instruction doesn't match a pattern because rB must be negated
2452 // for the instruction to work. Thus, the pattern below the instruction!
2455 ROTHMInst<(outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2456 [/* see patterns below - $rB must be negated! */]>;
2458 def : Pat<(srl R16C:$rA, R32C:$rB),
2459 (ROTHMr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2461 def : Pat<(srl R16C:$rA, R16C:$rB),
2463 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2465 def : Pat<(srl R16C:$rA, R8C:$rB),
2467 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB) ), 0))>;
2469 // ROTHMI v8i16 form: See the comment for ROTHM v8i16. The difference here is
2470 // that the immediate can be complemented, so that the user doesn't have to
2473 class ROTHMIInst<dag OOL, dag IOL, list<dag> pattern>:
2474 RI7Form<0b10111110000, OOL, IOL, "rothmi\t$rT, $rA, $val",
2475 RotateShift, pattern>;
2478 ROTHMIInst<(outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2479 [/* no pattern */]>;
2481 def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
2482 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2484 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
2485 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2487 def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
2488 (ROTHMIv8i16 VECREG:$rA, imm:$val)>;
2491 ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
2492 [/* no pattern */]>;
2494 def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
2495 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2497 def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
2498 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2500 def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
2501 (ROTHMIr16 R16C:$rA, uimm7:$val)>;
2503 // ROTM v4i32 form: See the ROTHM v8i16 comments.
2504 class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
2505 RRForm<0b10011010000, OOL, IOL, "rotm\t$rT, $rA, $rB",
2506 RotateShift, pattern>;
2509 ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2510 [/* see patterns below - $rB must be negated */]>;
2512 def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
2513 (ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2515 def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
2516 (ROTMv4i32 VECREG:$rA,
2517 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2519 def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
2520 (ROTMv4i32 VECREG:$rA,
2521 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2524 ROTMInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2525 [/* see patterns below - $rB must be negated */]>;
2527 def : Pat<(srl R32C:$rA, R32C:$rB),
2528 (ROTMr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2530 def : Pat<(srl R32C:$rA, R16C:$rB),
2532 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2534 def : Pat<(srl R32C:$rA, R8C:$rB),
2536 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2538 // ROTMI v4i32 form: See the comment for ROTHM v8i16.
2540 RI7Form<0b10011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2541 "rotmi\t$rT, $rA, $val", RotateShift,
2542 [(set (v4i32 VECREG:$rT),
2543 (SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
2545 def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
2546 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2548 def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
2549 (ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
2551 // ROTMI r32 form: know how to complement the immediate value.
2553 RI7Form<0b10011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2554 "rotmi\t$rT, $rA, $val", RotateShift,
2555 [(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
2557 def : Pat<(srl R32C:$rA, (i16 imm:$val)),
2558 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2560 def : Pat<(srl R32C:$rA, (i8 imm:$val)),
2561 (ROTMIr32 R32C:$rA, uimm7:$val)>;
2563 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2564 // ROTQMBYvec: This is a vector form merely so that when used in an
2565 // instruction pattern, type checking will succeed. This instruction assumes
2566 // that the user knew to negate $rB.
2568 // Using the SPUrotquad_rz_bytes target-specific DAG node, the patterns
2569 // ensure that $rB is negated.
2570 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2572 class ROTQMBYInst<dag OOL, dag IOL, list<dag> pattern>:
2573 RRForm<0b10111011100, OOL, IOL, "rotqmby\t$rT, $rA, $rB",
2574 RotateShift, pattern>;
2576 class ROTQMBYVecInst<ValueType vectype>:
2577 ROTQMBYInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2578 [/* no pattern, $rB must be negated */]>;
2580 class ROTQMBYRegInst<RegisterClass rclass>:
2581 ROTQMBYInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2583 (SPUrotquad_rz_bytes rclass:$rA, R32C:$rB))]>;
2585 multiclass RotateQuadBytes
2587 def v16i8: ROTQMBYVecInst<v16i8>;
2588 def v8i16: ROTQMBYVecInst<v8i16>;
2589 def v4i32: ROTQMBYVecInst<v4i32>;
2590 def v2i64: ROTQMBYVecInst<v2i64>;
2592 def r128: ROTQMBYRegInst<GPRC>;
2593 def r64: ROTQMBYRegInst<R64C>;
2596 defm ROTQMBY : RotateQuadBytes;
2598 def : Pat<(SPUrotquad_rz_bytes (v16i8 VECREG:$rA), R32C:$rB),
2599 (ROTQMBYv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2600 def : Pat<(SPUrotquad_rz_bytes (v8i16 VECREG:$rA), R32C:$rB),
2601 (ROTQMBYv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2602 def : Pat<(SPUrotquad_rz_bytes (v4i32 VECREG:$rA), R32C:$rB),
2603 (ROTQMBYv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2604 def : Pat<(SPUrotquad_rz_bytes (v2i64 VECREG:$rA), R32C:$rB),
2605 (ROTQMBYv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2606 def : Pat<(SPUrotquad_rz_bytes GPRC:$rA, R32C:$rB),
2607 (ROTQMBYr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2608 def : Pat<(SPUrotquad_rz_bytes R64C:$rA, R32C:$rB),
2609 (ROTQMBYr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2611 class ROTQMBYIInst<dag OOL, dag IOL, list<dag> pattern>:
2612 RI7Form<0b10111111100, OOL, IOL, "rotqmbyi\t$rT, $rA, $val",
2613 RotateShift, pattern>;
2615 class ROTQMBYIVecInst<ValueType vectype>:
2616 ROTQMBYIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2617 [(set (vectype VECREG:$rT),
2618 (SPUrotquad_rz_bytes (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2620 class ROTQMBYIRegInst<RegisterClass rclass, Operand optype, ValueType inttype, PatLeaf pred>:
2621 ROTQMBYIInst<(outs rclass:$rT), (ins rclass:$rA, optype:$val),
2623 (SPUrotquad_rz_bytes rclass:$rA, (inttype pred:$val)))]>;
2625 multiclass RotateQuadBytesImm
2627 def v16i8: ROTQMBYIVecInst<v16i8>;
2628 def v8i16: ROTQMBYIVecInst<v8i16>;
2629 def v4i32: ROTQMBYIVecInst<v4i32>;
2630 def v2i64: ROTQMBYIVecInst<v2i64>;
2632 def r128: ROTQMBYIRegInst<GPRC, rotNeg7imm, i32, uimm7>;
2633 def r64: ROTQMBYIRegInst<R64C, rotNeg7imm, i32, uimm7>;
2636 defm ROTQMBYI : RotateQuadBytesImm;
2639 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2640 // Rotate right and mask by bit count
2641 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2643 class ROTQMBYBIInst<dag OOL, dag IOL, list<dag> pattern>:
2644 RRForm<0b10110011100, OOL, IOL, "rotqmbybi\t$rT, $rA, $rB",
2645 RotateShift, pattern>;
2647 class ROTQMBYBIVecInst<ValueType vectype>:
2648 ROTQMBYBIInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2649 [/* no pattern, intrinsic? */]>;
2651 multiclass RotateMaskQuadByBitCount
2653 def v16i8: ROTQMBYBIVecInst<v16i8>;
2654 def v8i16: ROTQMBYBIVecInst<v8i16>;
2655 def v4i32: ROTQMBYBIVecInst<v4i32>;
2656 def v2i64: ROTQMBYBIVecInst<v2i64>;
2659 defm ROTQMBYBI: RotateMaskQuadByBitCount;
2661 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2662 // Rotate quad and mask by bits
2663 // Note that the rotate amount has to be negated
2664 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2666 class ROTQMBIInst<dag OOL, dag IOL, list<dag> pattern>:
2667 RRForm<0b10011011100, OOL, IOL, "rotqmbi\t$rT, $rA, $rB",
2668 RotateShift, pattern>;
2670 class ROTQMBIVecInst<ValueType vectype>:
2671 ROTQMBIInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2672 [/* no pattern */]>;
2674 class ROTQMBIRegInst<RegisterClass rclass>:
2675 ROTQMBIInst<(outs rclass:$rT), (ins rclass:$rA, R32C:$rB),
2676 [/* no pattern */]>;
2678 multiclass RotateMaskQuadByBits
2680 def v16i8: ROTQMBIVecInst<v16i8>;
2681 def v8i16: ROTQMBIVecInst<v8i16>;
2682 def v4i32: ROTQMBIVecInst<v4i32>;
2683 def v2i64: ROTQMBIVecInst<v2i64>;
2685 def r128: ROTQMBIRegInst<GPRC>;
2686 def r64: ROTQMBIRegInst<R64C>;
2689 defm ROTQMBI: RotateMaskQuadByBits;
2691 def : Pat<(SPUrotquad_rz_bits (v16i8 VECREG:$rA), R32C:$rB),
2692 (ROTQMBIv16i8 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2693 def : Pat<(SPUrotquad_rz_bits (v8i16 VECREG:$rA), R32C:$rB),
2694 (ROTQMBIv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2695 def : Pat<(SPUrotquad_rz_bits (v4i32 VECREG:$rA), R32C:$rB),
2696 (ROTQMBIv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2697 def : Pat<(SPUrotquad_rz_bits (v2i64 VECREG:$rA), R32C:$rB),
2698 (ROTQMBIv2i64 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2699 def : Pat<(SPUrotquad_rz_bits GPRC:$rA, R32C:$rB),
2700 (ROTQMBIr128 GPRC:$rA, (SFIr32 R32C:$rB, 0))>;
2701 def : Pat<(SPUrotquad_rz_bits R64C:$rA, R32C:$rB),
2702 (ROTQMBIr64 R64C:$rA, (SFIr32 R32C:$rB, 0))>;
2704 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2705 // Rotate quad and mask by bits, immediate
2706 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2708 class ROTQMBIIInst<dag OOL, dag IOL, list<dag> pattern>:
2709 RI7Form<0b10011111100, OOL, IOL, "rotqmbii\t$rT, $rA, $val",
2710 RotateShift, pattern>;
2712 class ROTQMBIIVecInst<ValueType vectype>:
2713 ROTQMBIIInst<(outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2714 [(set (vectype VECREG:$rT),
2715 (SPUrotquad_rz_bits (vectype VECREG:$rA), (i32 uimm7:$val)))]>;
2717 class ROTQMBIIRegInst<RegisterClass rclass>:
2718 ROTQMBIIInst<(outs rclass:$rT), (ins rclass:$rA, rotNeg7imm:$val),
2720 (SPUrotquad_rz_bits rclass:$rA, (i32 uimm7:$val)))]>;
2722 multiclass RotateMaskQuadByBitsImm
2724 def v16i8: ROTQMBIIVecInst<v16i8>;
2725 def v8i16: ROTQMBIIVecInst<v8i16>;
2726 def v4i32: ROTQMBIIVecInst<v4i32>;
2727 def v2i64: ROTQMBIIVecInst<v2i64>;
2729 def r128: ROTQMBIIRegInst<GPRC>;
2730 def r64: ROTQMBIIRegInst<R64C>;
2733 defm ROTQMBII: RotateMaskQuadByBitsImm;
2735 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2736 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
2739 RRForm<0b01111010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2740 "rotmah\t$rT, $rA, $rB", RotateShift,
2741 [/* see patterns below - $rB must be negated */]>;
2743 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2744 (ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
2746 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2747 (ROTMAHv8i16 VECREG:$rA,
2748 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2750 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2751 (ROTMAHv8i16 VECREG:$rA,
2752 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2755 RRForm<0b01111010000, (outs R16C:$rT), (ins R16C:$rA, R32C:$rB),
2756 "rotmah\t$rT, $rA, $rB", RotateShift,
2757 [/* see patterns below - $rB must be negated */]>;
2759 def : Pat<(sra R16C:$rA, R32C:$rB),
2760 (ROTMAHr16 R16C:$rA, (SFIr32 R32C:$rB, 0))>;
2762 def : Pat<(sra R16C:$rA, R16C:$rB),
2763 (ROTMAHr16 R16C:$rA,
2764 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2766 def : Pat<(sra R16C:$rA, R8C:$rB),
2767 (ROTMAHr16 R16C:$rA,
2768 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2771 RRForm<0b01111110000, (outs VECREG:$rT), (ins VECREG:$rA, rothNeg7imm:$val),
2772 "rotmahi\t$rT, $rA, $val", RotateShift,
2773 [(set (v8i16 VECREG:$rT),
2774 (SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
2776 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
2777 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2779 def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
2780 (ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
2783 RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
2784 "rotmahi\t$rT, $rA, $val", RotateShift,
2785 [(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
2787 def : Pat<(sra R16C:$rA, (i32 imm:$val)),
2788 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2790 def : Pat<(sra R16C:$rA, (i8 imm:$val)),
2791 (ROTMAHIr16 R16C:$rA, uimm7:$val)>;
2794 RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
2795 "rotma\t$rT, $rA, $rB", RotateShift,
2796 [/* see patterns below - $rB must be negated */]>;
2798 def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
2799 (ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
2801 def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
2802 (ROTMAv4i32 (v4i32 VECREG:$rA),
2803 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2805 def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
2806 (ROTMAv4i32 (v4i32 VECREG:$rA),
2807 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2810 RRForm<0b01011010000, (outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2811 "rotma\t$rT, $rA, $rB", RotateShift,
2812 [/* see patterns below - $rB must be negated */]>;
2814 def : Pat<(sra R32C:$rA, R32C:$rB),
2815 (ROTMAr32 R32C:$rA, (SFIr32 R32C:$rB, 0))>;
2817 def : Pat<(sra R32C:$rA, R16C:$rB),
2819 (SFIr32 (XSHWr16 R16C:$rB), 0))>;
2821 def : Pat<(sra R32C:$rA, R8C:$rB),
2823 (SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
2826 RRForm<0b01011110000, (outs VECREG:$rT), (ins VECREG:$rA, rotNeg7imm:$val),
2827 "rotmai\t$rT, $rA, $val", RotateShift,
2828 [(set (v4i32 VECREG:$rT),
2829 (SPUvec_sra VECREG:$rA, (i32 uimm7:$val)))]>;
2831 def : Pat<(SPUvec_sra VECREG:$rA, (i16 uimm7:$val)),
2832 (ROTMAIv4i32 VECREG:$rA, uimm7:$val)>;
2835 RRForm<0b01011110000, (outs R32C:$rT), (ins R32C:$rA, rotNeg7imm:$val),
2836 "rotmai\t$rT, $rA, $val", RotateShift,
2837 [(set R32C:$rT, (sra R32C:$rA, (i32 uimm7:$val)))]>;
2839 def : Pat<(sra R32C:$rA, (i16 uimm7:$val)),
2840 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2842 def : Pat<(sra R32C:$rA, (i8 uimm7:$val)),
2843 (ROTMAIr32 R32C:$rA, uimm7:$val)>;
2845 //===----------------------------------------------------------------------===//
2846 // Branch and conditionals:
2847 //===----------------------------------------------------------------------===//
2849 let isTerminator = 1, isBarrier = 1 in {
2850 // Halt If Equal (r32 preferred slot only, no vector form)
2852 RRForm_3<0b00011011110, (outs), (ins R32C:$rA, R32C:$rB),
2853 "heq\t$rA, $rB", BranchResolv,
2854 [/* no pattern to match */]>;
2857 RI10Form_2<0b11111110, (outs), (ins R32C:$rA, s10imm:$val),
2858 "heqi\t$rA, $val", BranchResolv,
2859 [/* no pattern to match */]>;
2861 // HGT/HGTI: These instructions use signed arithmetic for the comparison,
2862 // contrasting with HLGT/HLGTI, which use unsigned comparison:
2864 RRForm_3<0b00011010010, (outs), (ins R32C:$rA, R32C:$rB),
2865 "hgt\t$rA, $rB", BranchResolv,
2866 [/* no pattern to match */]>;
2869 RI10Form_2<0b11110010, (outs), (ins R32C:$rA, s10imm:$val),
2870 "hgti\t$rA, $val", BranchResolv,
2871 [/* no pattern to match */]>;
2874 RRForm_3<0b00011011010, (outs), (ins R32C:$rA, R32C:$rB),
2875 "hlgt\t$rA, $rB", BranchResolv,
2876 [/* no pattern to match */]>;
2879 RI10Form_2<0b11111010, (outs), (ins R32C:$rA, s10imm:$val),
2880 "hlgti\t$rA, $val", BranchResolv,
2881 [/* no pattern to match */]>;
2884 //------------------------------------------------------------------------
2885 // Comparison operators:
2886 //------------------------------------------------------------------------
2888 class CEQBInst<dag OOL, dag IOL, list<dag> pattern> :
2889 RRForm<0b00001011110, OOL, IOL, "ceqb\t$rT, $rA, $rB",
2892 multiclass CmpEqualByte
2895 CEQBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2896 [(set (v16i8 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2897 (v8i16 VECREG:$rB)))]>;
2900 CEQBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2901 [(set R8C:$rT, (seteq R8C:$rA, R8C:$rB))]>;
2904 class CEQBIInst<dag OOL, dag IOL, list<dag> pattern> :
2905 RI10Form<0b01111110, OOL, IOL, "ceqbi\t$rT, $rA, $val",
2908 multiclass CmpEqualByteImm
2911 CEQBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
2912 [(set (v16i8 VECREG:$rT), (seteq (v16i8 VECREG:$rA),
2913 v16i8SExt8Imm:$val))]>;
2915 CEQBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
2916 [(set R8C:$rT, (seteq R8C:$rA, immSExt8:$val))]>;
2919 class CEQHInst<dag OOL, dag IOL, list<dag> pattern> :
2920 RRForm<0b00010011110, OOL, IOL, "ceqh\t$rT, $rA, $rB",
2923 multiclass CmpEqualHalfword
2925 def v8i16 : CEQHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2926 [(set (v8i16 VECREG:$rT), (seteq (v8i16 VECREG:$rA),
2927 (v8i16 VECREG:$rB)))]>;
2929 def r16 : CEQHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
2930 [(set R16C:$rT, (seteq R16C:$rA, R16C:$rB))]>;
2933 class CEQHIInst<dag OOL, dag IOL, list<dag> pattern> :
2934 RI10Form<0b10111110, OOL, IOL, "ceqhi\t$rT, $rA, $val",
2937 multiclass CmpEqualHalfwordImm
2939 def v8i16 : CEQHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2940 [(set (v8i16 VECREG:$rT),
2941 (seteq (v8i16 VECREG:$rA),
2942 (v8i16 v8i16SExt10Imm:$val)))]>;
2943 def r16 : CEQHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
2944 [(set R16C:$rT, (seteq R16C:$rA, i16ImmSExt10:$val))]>;
2947 class CEQInst<dag OOL, dag IOL, list<dag> pattern> :
2948 RRForm<0b00000011110, OOL, IOL, "ceq\t$rT, $rA, $rB",
2951 multiclass CmpEqualWord
2953 def v4i32 : CEQInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2954 [(set (v4i32 VECREG:$rT),
2955 (seteq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
2957 def r32 : CEQInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
2958 [(set R32C:$rT, (seteq R32C:$rA, R32C:$rB))]>;
2961 class CEQIInst<dag OOL, dag IOL, list<dag> pattern> :
2962 RI10Form<0b00111110, OOL, IOL, "ceqi\t$rT, $rA, $val",
2965 multiclass CmpEqualWordImm
2967 def v4i32 : CEQIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
2968 [(set (v4i32 VECREG:$rT),
2969 (seteq (v4i32 VECREG:$rA),
2970 (v4i32 v4i32SExt16Imm:$val)))]>;
2972 def r32: CEQIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
2973 [(set R32C:$rT, (seteq R32C:$rA, i32ImmSExt10:$val))]>;
2976 class CGTBInst<dag OOL, dag IOL, list<dag> pattern> :
2977 RRForm<0b00001010010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
2980 multiclass CmpGtrByte
2983 CGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
2984 [(set (v16i8 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
2985 (v8i16 VECREG:$rB)))]>;
2988 CGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
2989 [(set R8C:$rT, (setgt R8C:$rA, R8C:$rB))]>;
2992 class CGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
2993 RI10Form<0b01110010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
2996 multiclass CmpGtrByteImm
2999 CGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3000 [(set (v16i8 VECREG:$rT), (setgt (v16i8 VECREG:$rA),
3001 v16i8SExt8Imm:$val))]>;
3003 CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3004 [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
3007 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
3008 RRForm<0b00010010010, OOL, IOL, "cgth\t$rT, $rA, $rB",
3011 multiclass CmpGtrHalfword
3013 def v8i16 : CGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3014 [(set (v8i16 VECREG:$rT), (setgt (v8i16 VECREG:$rA),
3015 (v8i16 VECREG:$rB)))]>;
3017 def r16 : CGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3018 [(set R16C:$rT, (setgt R16C:$rA, R16C:$rB))]>;
3021 class CGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
3022 RI10Form<0b10110010, OOL, IOL, "cgthi\t$rT, $rA, $val",
3025 multiclass CmpGtrHalfwordImm
3027 def v8i16 : CGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3028 [(set (v8i16 VECREG:$rT),
3029 (setgt (v8i16 VECREG:$rA),
3030 (v8i16 v8i16SExt10Imm:$val)))]>;
3031 def r16 : CGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3032 [(set R16C:$rT, (setgt R16C:$rA, i16ImmSExt10:$val))]>;
3035 class CGTInst<dag OOL, dag IOL, list<dag> pattern> :
3036 RRForm<0b00000010010, OOL, IOL, "cgt\t$rT, $rA, $rB",
3039 multiclass CmpGtrWord
3041 def v4i32 : CGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3042 [(set (v4i32 VECREG:$rT),
3043 (setgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3045 def r32 : CGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3046 [(set R32C:$rT, (setgt R32C:$rA, R32C:$rB))]>;
3049 class CGTIInst<dag OOL, dag IOL, list<dag> pattern> :
3050 RI10Form<0b00110010, OOL, IOL, "cgti\t$rT, $rA, $val",
3053 multiclass CmpGtrWordImm
3055 def v4i32 : CGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3056 [(set (v4i32 VECREG:$rT),
3057 (setgt (v4i32 VECREG:$rA),
3058 (v4i32 v4i32SExt16Imm:$val)))]>;
3060 def r32: CGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3061 [(set R32C:$rT, (setgt R32C:$rA, i32ImmSExt10:$val))]>;
3064 class CLGTBInst<dag OOL, dag IOL, list<dag> pattern> :
3065 RRForm<0b00001011010, OOL, IOL, "cgtb\t$rT, $rA, $rB",
3068 multiclass CmpLGtrByte
3071 CLGTBInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3072 [(set (v16i8 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3073 (v8i16 VECREG:$rB)))]>;
3076 CLGTBInst<(outs R8C:$rT), (ins R8C:$rA, R8C:$rB),
3077 [(set R8C:$rT, (setugt R8C:$rA, R8C:$rB))]>;
3080 class CLGTBIInst<dag OOL, dag IOL, list<dag> pattern> :
3081 RI10Form<0b01111010, OOL, IOL, "cgtbi\t$rT, $rA, $val",
3084 multiclass CmpLGtrByteImm
3087 CLGTBIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm_i8:$val),
3088 [(set (v16i8 VECREG:$rT), (setugt (v16i8 VECREG:$rA),
3089 v16i8SExt8Imm:$val))]>;
3091 CLGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
3092 [(set R8C:$rT, (setugt R8C:$rA, immSExt8:$val))]>;
3095 class CLGTHInst<dag OOL, dag IOL, list<dag> pattern> :
3096 RRForm<0b00010011010, OOL, IOL, "cgth\t$rT, $rA, $rB",
3099 multiclass CmpLGtrHalfword
3101 def v8i16 : CLGTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3102 [(set (v8i16 VECREG:$rT), (setugt (v8i16 VECREG:$rA),
3103 (v8i16 VECREG:$rB)))]>;
3105 def r16 : CLGTHInst<(outs R16C:$rT), (ins R16C:$rA, R16C:$rB),
3106 [(set R16C:$rT, (setugt R16C:$rA, R16C:$rB))]>;
3109 class CLGTHIInst<dag OOL, dag IOL, list<dag> pattern> :
3110 RI10Form<0b10111010, OOL, IOL, "cgthi\t$rT, $rA, $val",
3113 multiclass CmpLGtrHalfwordImm
3115 def v8i16 : CLGTHIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3116 [(set (v8i16 VECREG:$rT),
3117 (setugt (v8i16 VECREG:$rA),
3118 (v8i16 v8i16SExt10Imm:$val)))]>;
3119 def r16 : CLGTHIInst<(outs R16C:$rT), (ins R16C:$rA, s10imm:$val),
3120 [(set R16C:$rT, (setugt R16C:$rA, i16ImmSExt10:$val))]>;
3123 class CLGTInst<dag OOL, dag IOL, list<dag> pattern> :
3124 RRForm<0b00000011010, OOL, IOL, "cgt\t$rT, $rA, $rB",
3127 multiclass CmpLGtrWord
3129 def v4i32 : CLGTInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3130 [(set (v4i32 VECREG:$rT),
3131 (setugt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
3133 def r32 : CLGTInst<(outs R32C:$rT), (ins R32C:$rA, R32C:$rB),
3134 [(set R32C:$rT, (setugt R32C:$rA, R32C:$rB))]>;
3137 class CLGTIInst<dag OOL, dag IOL, list<dag> pattern> :
3138 RI10Form<0b00111010, OOL, IOL, "cgti\t$rT, $rA, $val",
3141 multiclass CmpLGtrWordImm
3143 def v4i32 : CLGTIInst<(outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
3144 [(set (v4i32 VECREG:$rT),
3145 (setugt (v4i32 VECREG:$rA),
3146 (v4i32 v4i32SExt16Imm:$val)))]>;
3148 def r32: CLGTIInst<(outs R32C:$rT), (ins R32C:$rA, s10imm_i32:$val),
3149 [(set R32C:$rT, (setugt R32C:$rA, i32ImmSExt10:$val))]>;
3152 defm CEQB : CmpEqualByte;
3153 defm CEQBI : CmpEqualByteImm;
3154 defm CEQH : CmpEqualHalfword;
3155 defm CEQHI : CmpEqualHalfwordImm;
3156 defm CEQ : CmpEqualWord;
3157 defm CEQI : CmpEqualWordImm;
3158 defm CGTB : CmpGtrByte;
3159 defm CGTBI : CmpGtrByteImm;
3160 defm CGTH : CmpGtrHalfword;
3161 defm CGTHI : CmpGtrHalfwordImm;
3162 defm CGT : CmpGtrWord;
3163 defm CGTI : CmpGtrWordImm;
3164 defm CLGTB : CmpLGtrByte;
3165 defm CLGTBI : CmpLGtrByteImm;
3166 defm CLGTH : CmpLGtrHalfword;
3167 defm CLGTHI : CmpLGtrHalfwordImm;
3168 defm CLGT : CmpLGtrWord;
3169 defm CLGTI : CmpLGtrWordImm;
3171 // For SETCC primitives not supported above (setlt, setle, setge, etc.)
3172 // define a pattern to generate the right code, as a binary operator
3173 // (in a manner of speaking.)
3175 class SETCCNegCond<PatFrag cond, RegisterClass rclass, dag pattern>:
3176 Pat<(cond rclass:$rA, rclass:$rB), pattern>;
3178 class SETCCBinOpReg<PatFrag cond, RegisterClass rclass,
3179 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3180 Pat<(cond rclass:$rA, rclass:$rB),
3181 (binop (cmpOp1 rclass:$rA, rclass:$rB),
3182 (cmpOp2 rclass:$rA, rclass:$rB))>;
3184 class SETCCBinOpImm<PatFrag cond, RegisterClass rclass, PatLeaf immpred,
3186 SPUInstr binop, SPUInstr cmpOp1, SPUInstr cmpOp2>:
3187 Pat<(cond rclass:$rA, (immtype immpred:$imm)),
3188 (binop (cmpOp1 rclass:$rA, (immtype immpred:$imm)),
3189 (cmpOp2 rclass:$rA, (immtype immpred:$imm)))>;
3191 def CGTEQBr8: SETCCBinOpReg<setge, R8C, ORr8, CGTBr8, CEQBr8>;
3192 def CGTEQBIr8: SETCCBinOpImm<setge, R8C, immSExt8, i8, ORr8, CGTBIr8, CEQBIr8>;
3193 def CLTBr8: SETCCBinOpReg<setlt, R8C, NORr8, CGTBr8, CEQBr8>;
3194 def CLTBIr8: SETCCBinOpImm<setlt, R8C, immSExt8, i8, NORr8, CGTBIr8, CEQBIr8>;
3195 def CLTEQr8: Pat<(setle R8C:$rA, R8C:$rB),
3196 (XORBIr8 (CGTBIr8 R8C:$rA, R8C:$rB), 0xff)>;
3197 def CLTEQIr8: Pat<(setle R8C:$rA, immU8:$imm),
3198 (XORBIr8 (CGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3200 def CGTEQHr16: SETCCBinOpReg<setge, R16C, ORr16, CGTHr16, CEQHr16>;
3201 def CGTEQHIr16: SETCCBinOpImm<setge, R16C, i16ImmUns10, i16,
3202 ORr16, CGTHIr16, CEQHIr16>;
3203 def CLTEQr16: Pat<(setle R16C:$rA, R16C:$rB),
3204 (XORHIr16 (CGTHIr16 R16C:$rA, R16C:$rB), 0xffff)>;
3205 def CLTEQIr16: Pat<(setle R16C:$rA, i16ImmUns10:$imm),
3206 (XORHIr16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3209 def CGTEQHr32: SETCCBinOpReg<setge, R32C, ORr32, CGTr32, CEQr32>;
3210 def CGTEQHIr32: SETCCBinOpImm<setge, R32C, i32ImmUns10, i32,
3211 ORr32, CGTIr32, CEQIr32>;
3212 def CLTEQr32: Pat<(setle R32C:$rA, R32C:$rB),
3213 (XORIr32 (CGTIr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3214 def CLTEQIr32: Pat<(setle R32C:$rA, i32ImmUns10:$imm),
3215 (XORIr32 (CGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3217 def CLGTEQBr8: SETCCBinOpReg<setuge, R8C, ORr8, CLGTBr8, CEQBr8>;
3218 def CLGTEQBIr8: SETCCBinOpImm<setuge, R8C, immSExt8, i8, ORr8, CLGTBIr8, CEQBIr8>;
3219 def CLLTBr8: SETCCBinOpReg<setult, R8C, NORr8, CLGTBr8, CEQBr8>;
3220 def CLLTBIr8: SETCCBinOpImm<setult, R8C, immSExt8, i8, NORr8, CLGTBIr8, CEQBIr8>;
3221 def CLLTEQr8: Pat<(setule R8C:$rA, R8C:$rB),
3222 (XORBIr8 (CLGTBIr8 R8C:$rA, R8C:$rB), 0xff)>;
3223 def CLLTEQIr8: Pat<(setule R8C:$rA, immU8:$imm),
3224 (XORBIr8 (CLGTBIr8 R8C:$rA, immU8:$imm), 0xff)>;
3226 def CLGTEQHr16: SETCCBinOpReg<setuge, R16C, ORr16, CLGTHr16, CEQHr16>;
3227 def CLGTEQHIr16: SETCCBinOpImm<setuge, R16C, i16ImmUns10, i16,
3228 ORr16, CLGTHIr16, CEQHIr16>;
3229 def CLLTEQr16: Pat<(setule R16C:$rA, R16C:$rB),
3230 (XORHIr16 (CLGTHIr16 R16C:$rA, R16C:$rB), 0xffff)>;
3231 def CLLTEQIr16: Pat<(setule R16C:$rA, i16ImmUns10:$imm),
3232 (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
3235 def CLGTEQHr32: SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
3236 def CLGTEQHIr32: SETCCBinOpImm<setuge, R32C, i32ImmUns10, i32,
3237 ORr32, CLGTIr32, CEQIr32>;
3238 def CLLTEQr32: Pat<(setule R32C:$rA, R32C:$rB),
3239 (XORIr32 (CLGTIr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
3240 def CLLTEQIr32: Pat<(setule R32C:$rA, i32ImmUns10:$imm),
3241 (XORIr32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$imm), 0xffffffff)>;
3243 //-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
3246 // All calls clobber the non-callee-saved registers:
3247 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
3248 R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,
3249 R20,R21,R22,R23,R24,R25,R26,R27,R28,R29,
3250 R30,R31,R32,R33,R34,R35,R36,R37,R38,R39,
3251 R40,R41,R42,R43,R44,R45,R46,R47,R48,R49,
3252 R50,R51,R52,R53,R54,R55,R56,R57,R58,R59,
3253 R60,R61,R62,R63,R64,R65,R66,R67,R68,R69,
3254 R70,R71,R72,R73,R74,R75,R76,R77,R78,R79],
3255 // All of these instructions use $lr (aka $0)
3257 // Branch relative and set link: Used if we actually know that the target
3258 // is within [-32768, 32767] bytes of the target
3260 BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops),
3261 "brsl\t$$lr, $func",
3262 [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>;
3264 // Branch absolute and set link: Used if we actually know that the target
3265 // is an absolute address
3267 BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops),
3268 "brasl\t$$lr, $func",
3269 [(SPUcall (SPUaform tglobaladdr:$func, 0))]>;
3271 // Branch indirect and set link if external data. These instructions are not
3272 // actually generated, matched by an intrinsic:
3273 def BISLED_00: BISLEDForm<0b11, "bisled\t$$lr, $func", [/* empty pattern */]>;
3274 def BISLED_E0: BISLEDForm<0b10, "bisled\t$$lr, $func", [/* empty pattern */]>;
3275 def BISLED_0D: BISLEDForm<0b01, "bisled\t$$lr, $func", [/* empty pattern */]>;
3276 def BISLED_ED: BISLEDForm<0b00, "bisled\t$$lr, $func", [/* empty pattern */]>;
3278 // Branch indirect and set link. This is the "X-form" address version of a
3281 BIForm<0b10010101100, "bisl\t$$lr, $func", [(SPUcall R32C:$func)]>;
3284 // Unconditional branches:
3285 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
3287 UncondBranch<0b001001100, (outs), (ins brtarget:$dest),
3291 // Unconditional, absolute address branch
3293 UncondBranch<0b001100000, (outs), (ins brtarget:$dest),
3295 [/* no pattern */]>;
3299 BIForm<0b00010101100, "bi\t$func", [(brind R32C:$func)]>;
3301 // Various branches:
3303 RI16Form<0b010000100, (outs), (ins R32C:$rCond, brtarget:$dest),
3304 "brnz\t$rCond,$dest",
3306 [(brcond R32C:$rCond, bb:$dest)]>;
3309 RI16Form<0b000000100, (outs), (ins R32C:$rT, brtarget:$dest),
3312 [/* no pattern */]>;
3315 RI16Form<0b011000100, (outs), (ins R16C:$rCond, brtarget:$dest),
3316 "brhnz\t$rCond,$dest",
3318 [(brcond R16C:$rCond, bb:$dest)]>;
3321 RI16Form<0b001000100, (outs), (ins R16C:$rT, brtarget:$dest),
3324 [/* no pattern */]>;
3328 BICondForm<0b10010100100, "binz\t$rA, $func",
3329 [(SPUbinz R32C:$rA, R32C:$func)]>;
3332 BICondForm<0b00010100100, "biz\t$rA, $func",
3333 [(SPUbiz R32C:$rA, R32C:$func)]>;
3337 //===----------------------------------------------------------------------===//
3338 // setcc and brcond patterns:
3339 //===----------------------------------------------------------------------===//
3341 def : Pat<(brcond (i16 (seteq R16C:$rA, 0)), bb:$dest),
3342 (BRHZ R16C:$rA, bb:$dest)>;
3343 def : Pat<(brcond (i16 (setne R16C:$rA, 0)), bb:$dest),
3344 (BRHNZ R16C:$rA, bb:$dest)>;
3346 def : Pat<(brcond (i32 (seteq R32C:$rA, 0)), bb:$dest),
3347 (BRZ R32C:$rA, bb:$dest)>;
3348 def : Pat<(brcond (i32 (setne R32C:$rA, 0)), bb:$dest),
3349 (BRNZ R32C:$rA, bb:$dest)>;
3351 multiclass BranchCondEQ<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3353 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3354 (brinst16 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3356 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3357 (brinst16 (CEQHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3359 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3360 (brinst32 (CEQIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3362 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3363 (brinst32 (CEQr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3366 defm BRCONDeq : BranchCondEQ<seteq, BRHZ, BRZ>;
3367 defm BRCONDne : BranchCondEQ<setne, BRHNZ, BRNZ>;
3369 multiclass BranchCondLGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3371 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3372 (brinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3374 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3375 (brinst16 (CLGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3377 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3378 (brinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3380 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3381 (brinst32 (CLGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3384 defm BRCONDugt : BranchCondLGT<setugt, BRHNZ, BRNZ>;
3385 defm BRCONDule : BranchCondLGT<setule, BRHZ, BRZ>;
3387 multiclass BranchCondLGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3388 SPUInstr orinst32, SPUInstr brinst32>
3390 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3391 (brinst16 (orinst16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3392 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3395 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3396 (brinst16 (orinst16 (CLGTHr16 R16C:$rA, R16:$rB),
3397 (CEQHr16 R16C:$rA, R16:$rB)),
3400 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3401 (brinst32 (orinst32 (CLGTIr32 R32C:$rA, i32ImmSExt10:$val),
3402 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3405 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3406 (brinst32 (orinst32 (CLGTr32 R32C:$rA, R32C:$rB),
3407 (CEQr32 R32C:$rA, R32C:$rB)),
3411 defm BRCONDuge : BranchCondLGTEQ<setuge, ORr16, BRHNZ, ORr32, BRNZ>;
3412 defm BRCONDult : BranchCondLGTEQ<setult, ORr16, BRHZ, ORr32, BRZ>;
3414 multiclass BranchCondGT<PatFrag cond, SPUInstr brinst16, SPUInstr brinst32>
3416 def r16imm : Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3417 (brinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val), bb:$dest)>;
3419 def r16 : Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3420 (brinst16 (CGTHr16 R16C:$rA, R16:$rB), bb:$dest)>;
3422 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3423 (brinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val), bb:$dest)>;
3425 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3426 (brinst32 (CGTr32 R32C:$rA, R32C:$rB), bb:$dest)>;
3429 defm BRCONDgt : BranchCondGT<setgt, BRHNZ, BRNZ>;
3430 defm BRCONDle : BranchCondGT<setle, BRHZ, BRZ>;
3432 multiclass BranchCondGTEQ<PatFrag cond, SPUInstr orinst16, SPUInstr brinst16,
3433 SPUInstr orinst32, SPUInstr brinst32>
3435 def r16imm: Pat<(brcond (i16 (cond R16C:$rA, i16ImmSExt10:$val)), bb:$dest),
3436 (brinst16 (orinst16 (CGTHIr16 R16C:$rA, i16ImmSExt10:$val),
3437 (CEQHIr16 R16C:$rA, i16ImmSExt10:$val)),
3440 def r16: Pat<(brcond (i16 (cond R16C:$rA, R16C:$rB)), bb:$dest),
3441 (brinst16 (orinst16 (CGTHr16 R16C:$rA, R16:$rB),
3442 (CEQHr16 R16C:$rA, R16:$rB)),
3445 def r32imm : Pat<(brcond (i32 (cond R32C:$rA, i32ImmSExt10:$val)), bb:$dest),
3446 (brinst32 (orinst32 (CGTIr32 R32C:$rA, i32ImmSExt10:$val),
3447 (CEQIr32 R32C:$rA, i32ImmSExt10:$val)),
3450 def r32 : Pat<(brcond (i32 (cond R32C:$rA, R32C:$rB)), bb:$dest),
3451 (brinst32 (orinst32 (CGTr32 R32C:$rA, R32C:$rB),
3452 (CEQr32 R32C:$rA, R32C:$rB)),
3456 defm BRCONDge : BranchCondGTEQ<setge, ORr16, BRHNZ, ORr32, BRNZ>;
3457 defm BRCONDlt : BranchCondGTEQ<setlt, ORr16, BRHZ, ORr32, BRZ>;
3459 let isTerminator = 1, isBarrier = 1 in {
3460 let isReturn = 1 in {
3462 RETForm<"bi\t$$lr", [(retflag)]>;
3466 //===----------------------------------------------------------------------===//
3467 // Single precision floating point instructions
3468 //===----------------------------------------------------------------------===//
3471 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3472 "fa\t$rT, $rA, $rB", SPrecFP,
3473 [(set (v4f32 VECREG:$rT), (fadd (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3476 RRForm<0b00100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3477 "fa\t$rT, $rA, $rB", SPrecFP,
3478 [(set R32FP:$rT, (fadd R32FP:$rA, R32FP:$rB))]>;
3481 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3482 "fs\t$rT, $rA, $rB", SPrecFP,
3483 [(set (v4f32 VECREG:$rT), (fsub (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)))]>;
3486 RRForm<0b10100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3487 "fs\t$rT, $rA, $rB", SPrecFP,
3488 [(set R32FP:$rT, (fsub R32FP:$rA, R32FP:$rB))]>;
3490 // Floating point reciprocal estimate
3492 RRForm_1<0b00011101100, (outs VECREG:$rT), (ins VECREG:$rA),
3493 "frest\t$rT, $rA", SPrecFP,
3494 [(set (v4f32 VECREG:$rT), (SPUreciprocalEst (v4f32 VECREG:$rA)))]>;
3497 RRForm_1<0b00011101100, (outs R32FP:$rT), (ins R32FP:$rA),
3498 "frest\t$rT, $rA", SPrecFP,
3499 [(set R32FP:$rT, (SPUreciprocalEst R32FP:$rA))]>;
3501 // Floating point interpolate (used in conjunction with reciprocal estimate)
3503 RRForm<0b00101011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3504 "fi\t$rT, $rA, $rB", SPrecFP,
3505 [(set (v4f32 VECREG:$rT), (SPUinterpolate (v4f32 VECREG:$rA),
3506 (v4f32 VECREG:$rB)))]>;
3509 RRForm<0b00101011110, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3510 "fi\t$rT, $rA, $rB", SPrecFP,
3511 [(set R32FP:$rT, (SPUinterpolate R32FP:$rA, R32FP:$rB))]>;
3513 // Floating Compare Equal
3515 RRForm<0b01000011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3516 "fceq\t$rT, $rA, $rB", SPrecFP,
3517 [(set R32C:$rT, (setoeq R32FP:$rA, R32FP:$rB))]>;
3520 RRForm<0b01010011110, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3521 "fcmeq\t$rT, $rA, $rB", SPrecFP,
3522 [(set R32C:$rT, (setoeq (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3525 RRForm<0b01000011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3526 "fcgt\t$rT, $rA, $rB", SPrecFP,
3527 [(set R32C:$rT, (setogt R32FP:$rA, R32FP:$rB))]>;
3530 RRForm<0b01010011010, (outs R32C:$rT), (ins R32FP:$rA, R32FP:$rB),
3531 "fcmgt\t$rT, $rA, $rB", SPrecFP,
3532 [(set R32C:$rT, (setogt (fabs R32FP:$rA), (fabs R32FP:$rB)))]>;
3534 // FP Status and Control Register Write
3535 // Why isn't rT a don't care in the ISA?
3536 // Should we create a special RRForm_3 for this guy and zero out the rT?
3538 RRForm_1<0b01011101110, (outs R32FP:$rT), (ins R32FP:$rA),
3539 "fscrwr\t$rA", SPrecFP,
3540 [/* This instruction requires an intrinsic. Note: rT is unused. */]>;
3542 // FP Status and Control Register Read
3544 RRForm_2<0b01011101110, (outs R32FP:$rT), (ins),
3545 "fscrrd\t$rT", SPrecFP,
3546 [/* This instruction requires an intrinsic */]>;
3548 // llvm instruction space
3549 // How do these map onto cell instructions?
3551 // frest rC rB # c = 1/b (both lines)
3553 // fm rD rA rC # d = a * 1/b
3554 // fnms rB rD rB rA # b = - (d * b - a) --should == 0 in a perfect world
3555 // fma rB rB rC rD # b = b * c + d
3556 // = -(d *b -a) * c + d
3557 // = a * c - c ( a *b *c - a)
3562 // These llvm instructions will actually map to library calls.
3563 // All that's needed, then, is to check that the appropriate library is
3564 // imported and do a brsl to the proper function name.
3565 // frem # fmod(x, y): x - (x/y) * y
3566 // (Note: fmod(double, double), fmodf(float,float)
3570 // Unimplemented SPU instruction space
3571 // floating reciprocal absolute square root estimate (frsqest)
3573 // The following are probably just intrinsics
3574 // status and control register write
3575 // status and control register read
3577 //--------------------------------------
3578 // Floating point multiply instructions
3579 //--------------------------------------
3582 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3583 "fm\t$rT, $rA, $rB", SPrecFP,
3584 [(set (v4f32 VECREG:$rT), (fmul (v4f32 VECREG:$rA),
3585 (v4f32 VECREG:$rB)))]>;
3588 RRForm<0b01100011010, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
3589 "fm\t$rT, $rA, $rB", SPrecFP,
3590 [(set R32FP:$rT, (fmul R32FP:$rA, R32FP:$rB))]>;
3592 // Floating point multiply and add
3593 // e.g. d = c + (a * b)
3595 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3596 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3597 [(set (v4f32 VECREG:$rT),
3598 (fadd (v4f32 VECREG:$rC),
3599 (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB))))]>;
3602 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3603 "fma\t$rT, $rA, $rB, $rC", SPrecFP,
3604 [(set R32FP:$rT, (fadd R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3606 // FP multiply and subtract
3607 // Subtracts value in rC from product
3610 RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3611 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3612 [(set (v4f32 VECREG:$rT),
3613 (fsub (fmul (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
3614 (v4f32 VECREG:$rC)))]>;
3617 RRRForm<0b0111, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3618 "fms\t$rT, $rA, $rB, $rC", SPrecFP,
3620 (fsub (fmul R32FP:$rA, R32FP:$rB), R32FP:$rC))]>;
3622 // Floating Negative Mulitply and Subtract
3623 // Subtracts product from value in rC
3624 // res = fneg(fms a b c)
3627 // NOTE: subtraction order
3631 RRRForm<0b1101, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB, R32FP:$rC),
3632 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3633 [(set R32FP:$rT, (fsub R32FP:$rC, (fmul R32FP:$rA, R32FP:$rB)))]>;
3636 RRRForm<0b1101, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3637 "fnms\t$rT, $rA, $rB, $rC", SPrecFP,
3638 [(set (v4f32 VECREG:$rT),
3639 (fsub (v4f32 VECREG:$rC),
3640 (fmul (v4f32 VECREG:$rA),
3641 (v4f32 VECREG:$rB))))]>;
3643 //--------------------------------------
3644 // Floating Point Conversions
3645 // Signed conversions:
3647 CVTIntFPForm<0b0101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3648 "csflt\t$rT, $rA, 0", SPrecFP,
3649 [(set (v4f32 VECREG:$rT), (sint_to_fp (v4i32 VECREG:$rA)))]>;
3651 // Convert signed integer to floating point
3653 CVTIntFPForm<0b0101101110, (outs R32FP:$rT), (ins R32C:$rA),
3654 "csflt\t$rT, $rA, 0", SPrecFP,
3655 [(set R32FP:$rT, (sint_to_fp R32C:$rA))]>;
3657 // Convert unsigned into to float
3659 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3660 "cuflt\t$rT, $rA, 0", SPrecFP,
3661 [(set (v4f32 VECREG:$rT), (uint_to_fp (v4i32 VECREG:$rA)))]>;
3664 CVTIntFPForm<0b1101101110, (outs R32FP:$rT), (ins R32C:$rA),
3665 "cuflt\t$rT, $rA, 0", SPrecFP,
3666 [(set R32FP:$rT, (uint_to_fp R32C:$rA))]>;
3668 // Convert float to unsigned int
3669 // Assume that scale = 0
3672 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3673 "cfltu\t$rT, $rA, 0", SPrecFP,
3674 [(set (v4i32 VECREG:$rT), (fp_to_uint (v4f32 VECREG:$rA)))]>;
3677 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3678 "cfltu\t$rT, $rA, 0", SPrecFP,
3679 [(set R32C:$rT, (fp_to_uint R32FP:$rA))]>;
3681 // Convert float to signed int
3682 // Assume that scale = 0
3685 CVTIntFPForm<0b1101101110, (outs VECREG:$rT), (ins VECREG:$rA),
3686 "cflts\t$rT, $rA, 0", SPrecFP,
3687 [(set (v4i32 VECREG:$rT), (fp_to_sint (v4f32 VECREG:$rA)))]>;
3690 CVTIntFPForm<0b1101101110, (outs R32C:$rT), (ins R32FP:$rA),
3691 "cflts\t$rT, $rA, 0", SPrecFP,
3692 [(set R32C:$rT, (fp_to_sint R32FP:$rA))]>;
3694 //===----------------------------------------------------------------------==//
3695 // Single<->Double precision conversions
3696 //===----------------------------------------------------------------------==//
3698 // NOTE: We use "vec" name suffix here to avoid confusion (e.g. input is a
3699 // v4f32, output is v2f64--which goes in the name?)
3701 // Floating point extend single to double
3702 // NOTE: Not sure if passing in v4f32 to FESDvec is correct since it
3703 // operates on two double-word slots (i.e. 1st and 3rd fp numbers
3706 RRForm_1<0b00011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3707 "fesd\t$rT, $rA", SPrecFP,
3708 [(set (v2f64 VECREG:$rT), (fextend (v4f32 VECREG:$rA)))]>;
3711 RRForm_1<0b00011101110, (outs R64FP:$rT), (ins R32FP:$rA),
3712 "fesd\t$rT, $rA", SPrecFP,
3713 [(set R64FP:$rT, (fextend R32FP:$rA))]>;
3715 // Floating point round double to single
3717 // RRForm_1<0b10011101110, (outs VECREG:$rT), (ins VECREG:$rA),
3718 // "frds\t$rT, $rA,", SPrecFP,
3719 // [(set (v4f32 R32FP:$rT), (fround (v2f64 R64FP:$rA)))]>;
3722 RRForm_1<0b10011101110, (outs R32FP:$rT), (ins R64FP:$rA),
3723 "frds\t$rT, $rA", SPrecFP,
3724 [(set R32FP:$rT, (fround R64FP:$rA))]>;
3726 //ToDo include anyextend?
3728 //===----------------------------------------------------------------------==//
3729 // Double precision floating point instructions
3730 //===----------------------------------------------------------------------==//
3732 RRForm<0b00110011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3733 "dfa\t$rT, $rA, $rB", DPrecFP,
3734 [(set R64FP:$rT, (fadd R64FP:$rA, R64FP:$rB))]>;
3737 RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3738 "dfa\t$rT, $rA, $rB", DPrecFP,
3739 [(set (v2f64 VECREG:$rT), (fadd (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3742 RRForm<0b10100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3743 "dfs\t$rT, $rA, $rB", DPrecFP,
3744 [(set R64FP:$rT, (fsub R64FP:$rA, R64FP:$rB))]>;
3747 RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3748 "dfs\t$rT, $rA, $rB", DPrecFP,
3749 [(set (v2f64 VECREG:$rT),
3750 (fsub (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3753 RRForm<0b01100011010, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
3754 "dfm\t$rT, $rA, $rB", DPrecFP,
3755 [(set R64FP:$rT, (fmul R64FP:$rA, R64FP:$rB))]>;
3758 RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
3759 "dfm\t$rT, $rA, $rB", DPrecFP,
3760 [(set (v2f64 VECREG:$rT),
3761 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)))]>;
3764 RRForm<0b00111010110, (outs R64FP:$rT),
3765 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3766 "dfma\t$rT, $rA, $rB", DPrecFP,
3767 [(set R64FP:$rT, (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3768 RegConstraint<"$rC = $rT">,
3772 RRForm<0b00111010110, (outs VECREG:$rT),
3773 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3774 "dfma\t$rT, $rA, $rB", DPrecFP,
3775 [(set (v2f64 VECREG:$rT),
3776 (fadd (v2f64 VECREG:$rC),
3777 (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB))))]>,
3778 RegConstraint<"$rC = $rT">,
3782 RRForm<0b10111010110, (outs R64FP:$rT),
3783 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3784 "dfms\t$rT, $rA, $rB", DPrecFP,
3785 [(set R64FP:$rT, (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))]>,
3786 RegConstraint<"$rC = $rT">,
3790 RRForm<0b10111010110, (outs VECREG:$rT),
3791 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3792 "dfms\t$rT, $rA, $rB", DPrecFP,
3793 [(set (v2f64 VECREG:$rT),
3794 (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3795 (v2f64 VECREG:$rC)))]>;
3797 // FNMS: - (a * b - c)
3798 // - (a * b) + c => c - (a * b)
3800 RRForm<0b01111010110, (outs R64FP:$rT),
3801 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3802 "dfnms\t$rT, $rA, $rB", DPrecFP,
3803 [(set R64FP:$rT, (fsub R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB)))]>,
3804 RegConstraint<"$rC = $rT">,
3807 def : Pat<(fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)),
3808 (FNMSf64 R64FP:$rA, R64FP:$rB, R64FP:$rC)>;
3811 RRForm<0b01111010110, (outs VECREG:$rT),
3812 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3813 "dfnms\t$rT, $rA, $rB", DPrecFP,
3814 [(set (v2f64 VECREG:$rT),
3815 (fsub (v2f64 VECREG:$rC),
3816 (fmul (v2f64 VECREG:$rA),
3817 (v2f64 VECREG:$rB))))]>,
3818 RegConstraint<"$rC = $rT">,
3821 def : Pat<(fneg (fsub (fmul (v2f64 VECREG:$rA), (v2f64 VECREG:$rB)),
3822 (v2f64 VECREG:$rC))),
3823 (FNMSv2f64 VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
3828 RRForm<0b11111010110, (outs R64FP:$rT),
3829 (ins R64FP:$rA, R64FP:$rB, R64FP:$rC),
3830 "dfnma\t$rT, $rA, $rB", DPrecFP,
3831 [(set R64FP:$rT, (fneg (fadd R64FP:$rC, (fmul R64FP:$rA, R64FP:$rB))))]>,
3832 RegConstraint<"$rC = $rT">,
3836 RRForm<0b11111010110, (outs VECREG:$rT),
3837 (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
3838 "dfnma\t$rT, $rA, $rB", DPrecFP,
3839 [(set (v2f64 VECREG:$rT),
3840 (fneg (fadd (v2f64 VECREG:$rC),
3841 (fmul (v2f64 VECREG:$rA),
3842 (v2f64 VECREG:$rB)))))]>,
3843 RegConstraint<"$rC = $rT">,
3846 //===----------------------------------------------------------------------==//
3847 // Floating point negation and absolute value
3848 //===----------------------------------------------------------------------==//
3850 def : Pat<(fneg (v4f32 VECREG:$rA)),
3851 (XORfnegvec (v4f32 VECREG:$rA),
3852 (v4f32 (ILHUv4i32 0x8000)))>;
3854 def : Pat<(fneg R32FP:$rA),
3855 (XORfneg32 R32FP:$rA, (ILHUr32 0x8000))>;
3857 def : Pat<(fneg (v2f64 VECREG:$rA)),
3858 (XORfnegvec (v2f64 VECREG:$rA),
3859 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80)))>;
3861 def : Pat<(fneg R64FP:$rA),
3862 (XORfneg64 R64FP:$rA,
3863 (ANDBIv16i8 (FSMBIv16i8 0x8080), 0x80))>;
3865 // Floating point absolute value
3867 def : Pat<(fabs R32FP:$rA),
3868 (ANDfabs32 R32FP:$rA, (IOHLr32 (ILHUr32 0x7fff), 0xffff))>;
3870 def : Pat<(fabs (v4f32 VECREG:$rA)),
3871 (ANDfabsvec (v4f32 VECREG:$rA),
3872 (v4f32 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3874 def : Pat<(fabs R64FP:$rA),
3875 (ANDfabs64 R64FP:$rA, (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f))>;
3877 def : Pat<(fabs (v2f64 VECREG:$rA)),
3878 (ANDfabsvec (v2f64 VECREG:$rA),
3879 (v2f64 (ANDBIv16i8 (FSMBIv16i8 0xffff), 0x7f)))>;
3881 //===----------------------------------------------------------------------===//
3882 // Execution, Load NOP (execute NOPs belong in even pipeline, load NOPs belong
3883 // in the odd pipeline)
3884 //===----------------------------------------------------------------------===//
3886 def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> {
3889 let Inst{0-10} = 0b10000000010;
3890 let Inst{11-17} = 0;
3891 let Inst{18-24} = 0;
3892 let Inst{25-31} = 0;
3895 def LNOP : SPUInstr<(outs), (ins), "lnop", LoadNOP> {
3898 let Inst{0-10} = 0b10000000000;
3899 let Inst{11-17} = 0;
3900 let Inst{18-24} = 0;
3901 let Inst{25-31} = 0;
3904 //===----------------------------------------------------------------------===//
3905 // Bit conversions (type conversions between vector/packed types)
3906 // NOTE: Promotions are handled using the XS* instructions. Truncation
3908 //===----------------------------------------------------------------------===//
3909 def : Pat<(v16i8 (bitconvert (v8i16 VECREG:$src))), (v16i8 VECREG:$src)>;
3910 def : Pat<(v16i8 (bitconvert (v4i32 VECREG:$src))), (v16i8 VECREG:$src)>;
3911 def : Pat<(v16i8 (bitconvert (v2i64 VECREG:$src))), (v16i8 VECREG:$src)>;
3912 def : Pat<(v16i8 (bitconvert (v4f32 VECREG:$src))), (v16i8 VECREG:$src)>;
3913 def : Pat<(v16i8 (bitconvert (v2f64 VECREG:$src))), (v16i8 VECREG:$src)>;
3915 def : Pat<(v8i16 (bitconvert (v16i8 VECREG:$src))), (v8i16 VECREG:$src)>;
3916 def : Pat<(v8i16 (bitconvert (v4i32 VECREG:$src))), (v8i16 VECREG:$src)>;
3917 def : Pat<(v8i16 (bitconvert (v2i64 VECREG:$src))), (v8i16 VECREG:$src)>;
3918 def : Pat<(v8i16 (bitconvert (v4f32 VECREG:$src))), (v8i16 VECREG:$src)>;
3919 def : Pat<(v8i16 (bitconvert (v2f64 VECREG:$src))), (v8i16 VECREG:$src)>;
3921 def : Pat<(v4i32 (bitconvert (v16i8 VECREG:$src))), (v4i32 VECREG:$src)>;
3922 def : Pat<(v4i32 (bitconvert (v8i16 VECREG:$src))), (v4i32 VECREG:$src)>;
3923 def : Pat<(v4i32 (bitconvert (v2i64 VECREG:$src))), (v4i32 VECREG:$src)>;
3924 def : Pat<(v4i32 (bitconvert (v4f32 VECREG:$src))), (v4i32 VECREG:$src)>;
3925 def : Pat<(v4i32 (bitconvert (v2f64 VECREG:$src))), (v4i32 VECREG:$src)>;
3927 def : Pat<(v2i64 (bitconvert (v16i8 VECREG:$src))), (v2i64 VECREG:$src)>;
3928 def : Pat<(v2i64 (bitconvert (v8i16 VECREG:$src))), (v2i64 VECREG:$src)>;
3929 def : Pat<(v2i64 (bitconvert (v4i32 VECREG:$src))), (v2i64 VECREG:$src)>;
3930 def : Pat<(v2i64 (bitconvert (v4f32 VECREG:$src))), (v2i64 VECREG:$src)>;
3931 def : Pat<(v2i64 (bitconvert (v2f64 VECREG:$src))), (v2i64 VECREG:$src)>;
3933 def : Pat<(v4f32 (bitconvert (v16i8 VECREG:$src))), (v4f32 VECREG:$src)>;
3934 def : Pat<(v4f32 (bitconvert (v8i16 VECREG:$src))), (v4f32 VECREG:$src)>;
3935 def : Pat<(v4f32 (bitconvert (v2i64 VECREG:$src))), (v4f32 VECREG:$src)>;
3936 def : Pat<(v4f32 (bitconvert (v4i32 VECREG:$src))), (v4f32 VECREG:$src)>;
3937 def : Pat<(v4f32 (bitconvert (v2f64 VECREG:$src))), (v4f32 VECREG:$src)>;
3939 def : Pat<(v2f64 (bitconvert (v16i8 VECREG:$src))), (v2f64 VECREG:$src)>;
3940 def : Pat<(v2f64 (bitconvert (v8i16 VECREG:$src))), (v2f64 VECREG:$src)>;
3941 def : Pat<(v2f64 (bitconvert (v4i32 VECREG:$src))), (v2f64 VECREG:$src)>;
3942 def : Pat<(v2f64 (bitconvert (v2i64 VECREG:$src))), (v2f64 VECREG:$src)>;
3943 def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
3945 def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
3946 def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
3948 //===----------------------------------------------------------------------===//
3949 // Instruction patterns:
3950 //===----------------------------------------------------------------------===//
3952 // General 32-bit constants:
3953 def : Pat<(i32 imm:$imm),
3954 (IOHLr32 (ILHUr32 (HI16 imm:$imm)), (LO16 imm:$imm))>;
3956 // Single precision float constants:
3957 def : Pat<(f32 fpimm:$imm),
3958 (IOHLf32 (ILHUf32 (HI16_f32 fpimm:$imm)), (LO16_f32 fpimm:$imm))>;
3960 // General constant 32-bit vectors
3961 def : Pat<(v4i32 v4i32Imm:$imm),
3962 (IOHLvec (v4i32 (ILHUv4i32 (HI16_vec v4i32Imm:$imm))),
3963 (LO16_vec v4i32Imm:$imm))>;
3966 def : Pat<(i8 imm:$imm),
3969 //===----------------------------------------------------------------------===//
3970 // Call instruction patterns:
3971 //===----------------------------------------------------------------------===//
3976 //===----------------------------------------------------------------------===//
3977 // Zero/Any/Sign extensions
3978 //===----------------------------------------------------------------------===//
3980 // zext 1->32: Zero extend i1 to i32
3981 def : Pat<(SPUextract_i1_zext R32C:$rSrc),
3982 (ANDIr32 R32C:$rSrc, 0x1)>;
3984 // sext 8->32: Sign extend bytes to words
3985 def : Pat<(sext_inreg R32C:$rSrc, i8),
3986 (XSHWr32 (XSBHr32 R32C:$rSrc))>;
3988 def : Pat<(i32 (sext R8C:$rSrc)),
3989 (XSHWr16 (XSBHr8 R8C:$rSrc))>;
3991 def : Pat<(SPUextract_i8_sext VECREG:$rSrc),
3992 (XSHWr32 (XSBHr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc),
3993 (v4i32 VECREG:$rSrc))))>;
3995 // zext 8->16: Zero extend bytes to halfwords
3996 def : Pat<(i16 (zext R8C:$rSrc)),
3997 (ANDHIi8i16 R8C:$rSrc, 0xff)>;
3999 // zext 8->32 from preferred slot in load/store
4000 def : Pat<(SPUextract_i8_zext VECREG:$rSrc),
4001 (ANDIr32 (ORi32_v4i32 (v4i32 VECREG:$rSrc), (v4i32 VECREG:$rSrc)),
4004 // zext 8->32: Zero extend bytes to words
4005 def : Pat<(i32 (zext R8C:$rSrc)),
4006 (ANDIi8i32 R8C:$rSrc, 0xff)>;
4008 // anyext 8->16: Extend 8->16 bits, irrespective of sign
4009 def : Pat<(i16 (anyext R8C:$rSrc)),
4010 (ORHIi8i16 R8C:$rSrc, 0)>;
4012 // anyext 8->32: Extend 8->32 bits, irrespective of sign
4013 def : Pat<(i32 (anyext R8C:$rSrc)),
4014 (ORIi8i32 R8C:$rSrc, 0)>;
4016 // zext 16->32: Zero extend halfwords to words
4017 def : Pat<(i32 (zext R16C:$rSrc)),
4018 (ANDi16i32 R16C:$rSrc, (ILAr32 0xffff))>;
4020 def : Pat<(i32 (zext (and R16C:$rSrc, 0xf))),
4021 (ANDIi16i32 R16C:$rSrc, 0xf)>;
4023 def : Pat<(i32 (zext (and R16C:$rSrc, 0xff))),
4024 (ANDIi16i32 R16C:$rSrc, 0xff)>;
4026 def : Pat<(i32 (zext (and R16C:$rSrc, 0xfff))),
4027 (ANDIi16i32 R16C:$rSrc, 0xfff)>;
4029 // anyext 16->32: Extend 16->32 bits, irrespective of sign
4030 def : Pat<(i32 (anyext R16C:$rSrc)),
4031 (ORIi16i32 R16C:$rSrc, 0)>;
4033 //===----------------------------------------------------------------------===//
4034 // Address generation: SPU, like PPC, has to split addresses into high and
4035 // low parts in order to load them into a register.
4036 //===----------------------------------------------------------------------===//
4038 def : Pat<(SPUaform tglobaladdr:$in, 0), (ILAlsa tglobaladdr:$in)>;
4039 def : Pat<(SPUaform texternalsym:$in, 0), (ILAlsa texternalsym:$in)>;
4040 def : Pat<(SPUaform tjumptable:$in, 0), (ILAlsa tjumptable:$in)>;
4041 def : Pat<(SPUaform tconstpool:$in, 0), (ILAlsa tconstpool:$in)>;
4043 def : Pat<(SPUindirect (SPUhi tglobaladdr:$in, 0),
4044 (SPUlo tglobaladdr:$in, 0)),
4045 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4047 def : Pat<(SPUindirect (SPUhi texternalsym:$in, 0),
4048 (SPUlo texternalsym:$in, 0)),
4049 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4051 def : Pat<(SPUindirect (SPUhi tjumptable:$in, 0),
4052 (SPUlo tjumptable:$in, 0)),
4053 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4055 def : Pat<(SPUindirect (SPUhi tconstpool:$in, 0),
4056 (SPUlo tconstpool:$in, 0)),
4057 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4059 def : Pat<(add (SPUhi tglobaladdr:$in, 0), (SPUlo tglobaladdr:$in, 0)),
4060 (IOHLlo (ILHUhi tglobaladdr:$in), tglobaladdr:$in)>;
4062 def : Pat<(add (SPUhi texternalsym:$in, 0), (SPUlo texternalsym:$in, 0)),
4063 (IOHLlo (ILHUhi texternalsym:$in), texternalsym:$in)>;
4065 def : Pat<(add (SPUhi tjumptable:$in, 0), (SPUlo tjumptable:$in, 0)),
4066 (IOHLlo (ILHUhi tjumptable:$in), tjumptable:$in)>;
4068 def : Pat<(add (SPUhi tconstpool:$in, 0), (SPUlo tconstpool:$in, 0)),
4069 (IOHLlo (ILHUhi tconstpool:$in), tconstpool:$in)>;
4072 include "CellSDKIntrinsics.td"