1 //===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Type profiles and SelectionDAG nodes used by CellSPU
12 //===----------------------------------------------------------------------===//
14 // Type profile for a call sequence
15 def SDT_SPUCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
17 // SPU_GenControl: Type profile for generating control words for insertions
18 def SPU_GenControl : SDTypeProfile<1, 1, []>;
19 def SPUvecinsmask : SDNode<"SPUISD::INSERT_MASK", SPU_GenControl, []>;
21 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPUCallSeq,
22 [SDNPHasChain, SDNPOutFlag]>;
23 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq,
24 [SDNPHasChain, SDNPOutFlag]>;
25 //===----------------------------------------------------------------------===//
26 // Operand constraints:
27 //===----------------------------------------------------------------------===//
29 def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
30 def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall,
31 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
33 // Operand type constraints for vector shuffle/permute operations
34 def SDT_SPUshuffle : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
38 // Unary, binary v16i8 operator type constraints:
39 def SPUv16i8_unop: SDTypeProfile<1, 1, [
40 SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>]>;
42 def SPUv16i8_binop: SDTypeProfile<1, 2, [
43 SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
45 // Binary v8i16 operator type constraints:
46 def SPUv8i16_unop: SDTypeProfile<1, 1, [
47 SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>]>;
49 def SPUv8i16_binop: SDTypeProfile<1, 2, [
50 SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
52 // Binary v4i32 operator type constraints:
53 def SPUv4i32_unop: SDTypeProfile<1, 1, [
54 SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>]>;
56 def SPUv4i32_binop: SDTypeProfile<1, 2, [
57 SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
59 // FSMBI type constraints: There are several variations for the various
60 // vector types (this avoids having to bit_convert all over the place.)
61 def SPUfsmbi_type: SDTypeProfile<1, 1, [
65 // SELB type constraints:
66 def SPUselb_type: SDTypeProfile<1, 3, [
67 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<0, 3> ]>;
69 // SPU Vector shift pseudo-instruction type constraints
70 def SPUvecshift_type: SDTypeProfile<1, 2, [
71 SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
73 //===----------------------------------------------------------------------===//
74 // Synthetic/pseudo-instructions
75 //===----------------------------------------------------------------------===//
78 def SPUcntb_v16i8: SDNode<"SPUISD::CNTB", SPUv16i8_unop, []>;
79 def SPUcntb_v8i16: SDNode<"SPUISD::CNTB", SPUv8i16_unop, []>;
80 def SPUcntb_v4i32: SDNode<"SPUISD::CNTB", SPUv4i32_unop, []>;
82 // SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see
83 // SPUISelLowering.h):
84 def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>;
86 // SPU 16-bit multiply
87 def SPUmpy_v16i8: SDNode<"SPUISD::MPY", SPUv16i8_binop, []>;
88 def SPUmpy_v8i16: SDNode<"SPUISD::MPY", SPUv8i16_binop, []>;
89 def SPUmpy_v4i32: SDNode<"SPUISD::MPY", SPUv4i32_binop, []>;
91 // SPU multiply unsigned, used in instruction lowering for v4i32
93 def SPUmpyu_v4i32: SDNode<"SPUISD::MPYU", SPUv4i32_binop, []>;
94 def SPUmpyu_i32: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>;
96 // SPU 16-bit multiply high x low, shift result 16-bits
97 // Used to compute intermediate products for 32-bit multiplies
98 def SPUmpyh_v4i32: SDNode<"SPUISD::MPYH", SPUv4i32_binop, []>;
99 def SPUmpyh_i32: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>;
101 // SPU 16-bit multiply high x high, 32-bit product
102 // Used to compute intermediate products for 16-bit multiplies
103 def SPUmpyhh_v8i16: SDNode<"SPUISD::MPYHH", SPUv8i16_binop, []>;
105 // Shift left quadword by bits and bytes
106 def SPUshlquad_l_bits: SDNode<"SPUISD::SHLQUAD_L_BITS", SPUvecshift_type, []>;
107 def SPUshlquad_l_bytes: SDNode<"SPUISD::SHLQUAD_L_BYTES", SPUvecshift_type, []>;
109 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
110 def SPUvec_shl: SDNode<"SPUISD::VEC_SHL", SPUvecshift_type, []>;
111 def SPUvec_srl: SDNode<"SPUISD::VEC_SRL", SPUvecshift_type, []>;
112 def SPUvec_sra: SDNode<"SPUISD::VEC_SRA", SPUvecshift_type, []>;
114 def SPUvec_rotl: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type, []>;
115 def SPUvec_rotr: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type, []>;
117 def SPUrotquad_rz_bytes: SDNode<"SPUISD::ROTQUAD_RZ_BYTES",
118 SPUvecshift_type, []>;
119 def SPUrotquad_rz_bits: SDNode<"SPUISD::ROTQUAD_RZ_BITS",
120 SPUvecshift_type, []>;
122 def SPUrotbytes_right_sfill: SDNode<"SPUISD::ROTBYTES_RIGHT_S",
123 SPUvecshift_type, []>;
125 def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT",
126 SPUvecshift_type, []>;
128 def SPUrotbytes_left_chained : SDNode<"SPUISD::ROTBYTES_LEFT_CHAINED",
129 SPUvecshift_type, [SDNPHasChain]>;
131 // SPU form select mask for bytes, immediate
132 def SPUfsmbi: SDNode<"SPUISD::FSMBI", SPUfsmbi_type, []>;
134 // SPU select bits instruction
135 def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>;
137 // SPU floating point interpolate
138 def SPUinterpolate : SDNode<"SPUISD::FPInterp", SDTFPBinOp, []>;
140 // SPU floating point reciprocal estimate (used for fdiv)
141 def SPUreciprocalEst: SDNode<"SPUISD::FPRecipEst", SDTFPUnaryOp, []>;
143 def SDTpromote_scalar: SDTypeProfile<1, 1, []>;
144 def SPUpromote_scalar: SDNode<"SPUISD::PROMOTE_SCALAR", SDTpromote_scalar, []>;
146 def SPU_vec_demote : SDTypeProfile<1, 1, []>;
147 def SPUextract_elt0: SDNode<"SPUISD::EXTRACT_ELT0", SPU_vec_demote, []>;
148 def SPU_vec_demote_chained : SDTypeProfile<1, 2, []>;
149 def SPUextract_elt0_chained: SDNode<"SPUISD::EXTRACT_ELT0_CHAINED",
150 SPU_vec_demote_chained, [SDNPHasChain]>;
151 def SPUextract_i1_sext: SDNode<"SPUISD::EXTRACT_I1_SEXT", SPU_vec_demote, []>;
152 def SPUextract_i1_zext: SDNode<"SPUISD::EXTRACT_I1_ZEXT", SPU_vec_demote, []>;
153 def SPUextract_i8_sext: SDNode<"SPUISD::EXTRACT_I8_SEXT", SPU_vec_demote, []>;
154 def SPUextract_i8_zext: SDNode<"SPUISD::EXTRACT_I8_ZEXT", SPU_vec_demote, []>;
156 // Address high and low components, used for [r+r] type addressing
157 def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
158 def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
160 // PC-relative address
161 def SPUpcrel : SDNode<"SPUISD::PCRelAddr", SDTIntBinOp, []>;
163 // A-Form local store addresses
164 def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>;
166 // Indirect [D-Form "imm($reg)" and X-Form "$reg($reg)"] addresses
167 def SPUindirect : SDNode<"SPUISD::IndirectAddr", SDTIntBinOp, []>;
169 // SPU 32-bit sign-extension to 64-bits
170 def SPUsext32_to_64: SDNode<"SPUISD::SEXT32TO64", SDTIntExtendOp, []>;
174 def SPUbrnz : SDNode<"SPUISD::BR_NOTZERO", SDTBrcond, [SDNPHasChain]>;
175 def SPUbrz : SDNode<"SPUISD::BR_ZERO", SDTBrcond, [SDNPHasChain]>;
176 /* def SPUbinz : SDNode<"SPUISD::BR_NOTZERO", SDTBrind, [SDNPHasChain]>;
177 def SPUbiz : SDNode<"SPUISD::BR_ZERO", SPUBrind, [SDNPHasChain]>; */
179 //===----------------------------------------------------------------------===//
180 // Constraints: (taken from PPCInstrInfo.td)
181 //===----------------------------------------------------------------------===//
183 class RegConstraint<string C> {
184 string Constraints = C;
187 class NoEncode<string E> {
188 string DisableEncoding = E;
191 //===----------------------------------------------------------------------===//
192 // Return (flag isn't quite what it means: the operations are flagged so that
193 // instruction scheduling doesn't disassociate them.)
194 //===----------------------------------------------------------------------===//
196 def retflag : SDNode<"SPUISD::RET_FLAG", SDTNone,
197 [SDNPHasChain, SDNPOptInFlag]>;