1 //===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Type profiles and SelectionDAG nodes used by CellSPU
12 //===----------------------------------------------------------------------===//
14 // Type profile for a call sequence
15 def SDT_SPUCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
17 // SPU_GenControl: Type profile for generating control words for insertions
18 def SPU_GenControl : SDTypeProfile<1, 1, []>;
19 def SPUvecinsmask : SDNode<"SPUISD::INSERT_MASK", SPU_GenControl, []>;
21 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPUCallSeq,
22 [SDNPHasChain, SDNPOutFlag]>;
23 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq,
24 [SDNPHasChain, SDNPOutFlag]>;
25 //===----------------------------------------------------------------------===//
26 // Operand constraints:
27 //===----------------------------------------------------------------------===//
29 def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
30 def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall,
31 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
33 // Operand type constraints for vector shuffle/permute operations
34 def SDT_SPUshuffle : SDTypeProfile<1, 3, [
35 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
38 // Unary, binary v16i8 operator type constraints:
39 def SPUv16i8_binop: SDTypeProfile<1, 2, [
40 SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
42 // Binary v8i16 operator type constraints:
43 def SPUv8i16_binop: SDTypeProfile<1, 2, [
44 SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
46 // Binary v4i32 operator type constraints:
47 def SPUv4i32_binop: SDTypeProfile<1, 2, [
48 SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
50 // Trinary operators, e.g., addx, carry generate
51 def SPUIntTrinaryOp : SDTypeProfile<1, 3, [
52 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<0>
55 // SELECT_MASK type constraints: There are several variations for the various
56 // vector types (this avoids having to bit_convert all over the place.)
57 def SPUselmask_type: SDTypeProfile<1, 1, [
61 // SELB type constraints:
62 def SPUselb_type: SDTypeProfile<1, 3, [
63 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<0, 3> ]>;
65 // SPU Vector shift pseudo-instruction type constraints
66 def SPUvecshift_type: SDTypeProfile<1, 2, [
67 SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
69 //===----------------------------------------------------------------------===//
70 // Synthetic/pseudo-instructions
71 //===----------------------------------------------------------------------===//
73 /// Add extended, carry generate:
74 def SPUaddx : SDNode<"SPUISD::ADD_EXTENDED", SPUIntTrinaryOp, []>;
75 def SPUcarry_gen : SDNode<"SPUISD::CARRY_GENERATE", SDTIntBinOp, []>;
77 // Subtract extended, borrow generate
78 def SPUsubx : SDNode<"SPUISD::SUB_EXTENDED", SPUIntTrinaryOp, []>;
79 def SPUborrow_gen : SDNode<"SPUISD::BORROW_GENERATE", SDTIntBinOp, []>;
82 def SPUcntb : SDNode<"SPUISD::CNTB", SDTIntUnaryOp>;
84 // SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see
85 // SPUISelLowering.h):
86 def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>;
88 // SPU 16-bit multiply
89 def SPUmpy_v16i8: SDNode<"SPUISD::MPY", SPUv16i8_binop, []>;
90 def SPUmpy_v8i16: SDNode<"SPUISD::MPY", SPUv8i16_binop, []>;
91 def SPUmpy_v4i32: SDNode<"SPUISD::MPY", SPUv4i32_binop, []>;
93 // SPU multiply unsigned, used in instruction lowering for v4i32
95 def SPUmpyu_v4i32: SDNode<"SPUISD::MPYU", SPUv4i32_binop, []>;
96 def SPUmpyu_i32: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>;
98 // SPU 16-bit multiply high x low, shift result 16-bits
99 // Used to compute intermediate products for 32-bit multiplies
100 def SPUmpyh_v4i32: SDNode<"SPUISD::MPYH", SPUv4i32_binop, []>;
101 def SPUmpyh_i32: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>;
103 // SPU 16-bit multiply high x high, 32-bit product
104 // Used to compute intermediate products for 16-bit multiplies
105 def SPUmpyhh_v8i16: SDNode<"SPUISD::MPYHH", SPUv8i16_binop, []>;
107 // Shift left quadword by bits and bytes
108 def SPUshlquad_l_bits: SDNode<"SPUISD::SHLQUAD_L_BITS", SPUvecshift_type, []>;
109 def SPUshlquad_l_bytes: SDNode<"SPUISD::SHLQUAD_L_BYTES", SPUvecshift_type, []>;
111 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
112 def SPUvec_shl: SDNode<"SPUISD::VEC_SHL", SPUvecshift_type, []>;
113 def SPUvec_srl: SDNode<"SPUISD::VEC_SRL", SPUvecshift_type, []>;
114 def SPUvec_sra: SDNode<"SPUISD::VEC_SRA", SPUvecshift_type, []>;
116 def SPUvec_rotl: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type, []>;
117 def SPUvec_rotr: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type, []>;
119 def SPUrotquad_rz_bytes: SDNode<"SPUISD::ROTQUAD_RZ_BYTES",
120 SPUvecshift_type, []>;
121 def SPUrotquad_rz_bits: SDNode<"SPUISD::ROTQUAD_RZ_BITS",
122 SPUvecshift_type, []>;
124 def SPUrotbytes_right_sfill: SDNode<"SPUISD::ROTBYTES_RIGHT_S",
125 SPUvecshift_type, []>;
127 // Vector rotate left, bits shifted out of the left are rotated in on the right
128 def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT",
129 SPUvecshift_type, []>;
131 // Same as above, but the node also has a chain associated (used in loads and
133 def SPUrotbytes_left_chained : SDNode<"SPUISD::ROTBYTES_LEFT_CHAINED",
134 SPUvecshift_type, [SDNPHasChain]>;
136 // Vector rotate left by bytes, but the count is given in bits and the SPU
137 // internally converts it to bytes (saves an instruction to mask off lower
139 def SPUrotbytes_left_bits : SDNode<"SPUISD::ROTBYTES_LEFT_BITS",
142 // SPU form select mask for bytes, immediate
143 def SPUselmask: SDNode<"SPUISD::SELECT_MASK", SPUselmask_type, []>;
145 // SPU select bits instruction
146 def SPUselb: SDNode<"SPUISD::SELB", SPUselb_type, []>;
148 // SPU floating point interpolate
149 def SPUinterpolate : SDNode<"SPUISD::FPInterp", SDTFPBinOp, []>;
151 // SPU floating point reciprocal estimate (used for fdiv)
152 def SPUreciprocalEst: SDNode<"SPUISD::FPRecipEst", SDTFPUnaryOp, []>;
154 def SDTpromote_scalar: SDTypeProfile<1, 1, []>;
155 def SPUpromote_scalar: SDNode<"SPUISD::PROMOTE_SCALAR", SDTpromote_scalar, []>;
157 def SPU_vec_demote : SDTypeProfile<1, 1, []>;
158 def SPUextract_elt0: SDNode<"SPUISD::EXTRACT_ELT0", SPU_vec_demote, []>;
159 def SPU_vec_demote_chained : SDTypeProfile<1, 2, []>;
160 def SPUextract_elt0_chained: SDNode<"SPUISD::EXTRACT_ELT0_CHAINED",
161 SPU_vec_demote_chained, [SDNPHasChain]>;
162 def SPUextract_i1_sext: SDNode<"SPUISD::EXTRACT_I1_SEXT", SPU_vec_demote, []>;
163 def SPUextract_i1_zext: SDNode<"SPUISD::EXTRACT_I1_ZEXT", SPU_vec_demote, []>;
164 def SPUextract_i8_sext: SDNode<"SPUISD::EXTRACT_I8_SEXT", SPU_vec_demote, []>;
165 def SPUextract_i8_zext: SDNode<"SPUISD::EXTRACT_I8_ZEXT", SPU_vec_demote, []>;
167 // Address high and low components, used for [r+r] type addressing
168 def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
169 def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
171 // PC-relative address
172 def SPUpcrel : SDNode<"SPUISD::PCRelAddr", SDTIntBinOp, []>;
174 // A-Form local store addresses
175 def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>;
177 // Indirect [D-Form "imm($reg)" and X-Form "$reg($reg)"] addresses
178 def SPUindirect : SDNode<"SPUISD::IndirectAddr", SDTIntBinOp, []>;
180 // SPU 32-bit sign-extension to 64-bits
181 def SPUsext32_to_64: SDNode<"SPUISD::SEXT32TO64", SDTIntExtendOp, []>;
185 def SPUbrnz : SDNode<"SPUISD::BR_NOTZERO", SDTBrcond, [SDNPHasChain]>;
186 def SPUbrz : SDNode<"SPUISD::BR_ZERO", SDTBrcond, [SDNPHasChain]>;
187 /* def SPUbinz : SDNode<"SPUISD::BR_NOTZERO", SDTBrind, [SDNPHasChain]>;
188 def SPUbiz : SDNode<"SPUISD::BR_ZERO", SPUBrind, [SDNPHasChain]>; */
190 //===----------------------------------------------------------------------===//
191 // Constraints: (taken from PPCInstrInfo.td)
192 //===----------------------------------------------------------------------===//
194 class RegConstraint<string C> {
195 string Constraints = C;
198 class NoEncode<string E> {
199 string DisableEncoding = E;
202 //===----------------------------------------------------------------------===//
203 // Return (flag isn't quite what it means: the operations are flagged so that
204 // instruction scheduling doesn't disassociate them.)
205 //===----------------------------------------------------------------------===//
207 def retflag : SDNode<"SPUISD::RET_FLAG", SDTNone,
208 [SDNPHasChain, SDNPOptInFlag]>;