1 //===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Type profiles and SelectionDAG nodes used by CellSPU
12 //===----------------------------------------------------------------------===//
14 // Type profile for a call sequence
15 def SDT_SPUCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
17 // SPU_GenControl: Type profile for generating control words for insertions
18 def SPU_GenControl : SDTypeProfile<1, 1, []>;
19 def SPUvecinsmask : SDNode<"SPUISD::INSERT_MASK", SPU_GenControl, []>;
21 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPUCallSeq,
22 [SDNPHasChain, SDNPOutFlag]>;
23 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq,
24 [SDNPHasChain, SDNPOutFlag]>;
25 //===----------------------------------------------------------------------===//
26 // Operand constraints:
27 //===----------------------------------------------------------------------===//
29 def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
30 def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall,
31 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
33 // Operand type constraints for vector shuffle/permute operations
34 def SDT_SPUshuffle : SDTypeProfile<1, 3, [
35 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
38 // Unary, binary v16i8 operator type constraints:
39 def SPUv16i8_unop: SDTypeProfile<1, 1, [
40 SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>]>;
42 def SPUv16i8_binop: SDTypeProfile<1, 2, [
43 SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
45 // Binary v8i16 operator type constraints:
46 def SPUv8i16_unop: SDTypeProfile<1, 1, [
47 SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>]>;
49 def SPUv8i16_binop: SDTypeProfile<1, 2, [
50 SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
52 // Binary v4i32 operator type constraints:
53 def SPUv4i32_unop: SDTypeProfile<1, 1, [
54 SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>]>;
56 def SPUv4i32_binop: SDTypeProfile<1, 2, [
57 SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
59 // FSMBI type constraints: There are several variations for the various
60 // vector types (this avoids having to bit_convert all over the place.)
61 def SPUfsmbi_type_v16i8: SDTypeProfile<1, 1, [
62 SDTCisVT<0, v16i8>, SDTCisVT<1, i32>]>;
64 def SPUfsmbi_type_v8i16: SDTypeProfile<1, 1, [
65 SDTCisVT<0, v8i16>, SDTCisVT<1, i32>]>;
67 def SPUfsmbi_type_v4i32: SDTypeProfile<1, 1, [
68 SDTCisVT<0, v4i32>, SDTCisVT<1, i32>]>;
70 // SELB type constraints:
71 def SPUselb_type_v16i8: SDTypeProfile<1, 3, [
72 SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
73 SDTCisSameAs<0, 3> ]>;
75 def SPUselb_type_v8i16: SDTypeProfile<1, 3, [
76 SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
77 SDTCisSameAs<0, 3> ]>;
79 def SPUselb_type_v4i32: SDTypeProfile<1, 3, [
80 SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
81 SDTCisSameAs<0, 3> ]>;
83 // SPU Vector shift pseudo-instruction type constraints
84 def SPUvecshift_type_v16i8: SDTypeProfile<1, 2, [
85 SDTCisVT<0, v16i8>, SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
87 def SPUvecshift_type_v8i16: SDTypeProfile<1, 2, [
88 SDTCisVT<0, v8i16>, SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
90 def SPUvecshift_type_v4i32: SDTypeProfile<1, 2, [
91 SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1>, SDTCisInt<2>]>;
93 //===----------------------------------------------------------------------===//
94 // Synthetic/pseudo-instructions
95 //===----------------------------------------------------------------------===//
98 def SPUcntb_v16i8: SDNode<"SPUISD::CNTB", SPUv16i8_unop, []>;
99 def SPUcntb_v8i16: SDNode<"SPUISD::CNTB", SPUv8i16_unop, []>;
100 def SPUcntb_v4i32: SDNode<"SPUISD::CNTB", SPUv4i32_unop, []>;
102 // SPU vector shuffle node, matched by the SPUISD::SHUFB enum (see
103 // SPUISelLowering.h):
104 def SPUshuffle: SDNode<"SPUISD::SHUFB", SDT_SPUshuffle, []>;
106 // SPU 16-bit multiply
107 def SPUmpy_v16i8: SDNode<"SPUISD::MPY", SPUv16i8_binop, []>;
108 def SPUmpy_v8i16: SDNode<"SPUISD::MPY", SPUv8i16_binop, []>;
109 def SPUmpy_v4i32: SDNode<"SPUISD::MPY", SPUv4i32_binop, []>;
111 // SPU multiply unsigned, used in instruction lowering for v4i32
113 def SPUmpyu_v4i32: SDNode<"SPUISD::MPYU", SPUv4i32_binop, []>;
114 def SPUmpyu_i32: SDNode<"SPUISD::MPYU", SDTIntBinOp, []>;
116 // SPU 16-bit multiply high x low, shift result 16-bits
117 // Used to compute intermediate products for 32-bit multiplies
118 def SPUmpyh_v4i32: SDNode<"SPUISD::MPYH", SPUv4i32_binop, []>;
119 def SPUmpyh_i32: SDNode<"SPUISD::MPYH", SDTIntBinOp, []>;
121 // SPU 16-bit multiply high x high, 32-bit product
122 // Used to compute intermediate products for 16-bit multiplies
123 def SPUmpyhh_v8i16: SDNode<"SPUISD::MPYHH", SPUv8i16_binop, []>;
125 // Vector shifts (ISD::SHL,SRL,SRA are for _integers_ only):
126 def SPUvec_shl_v8i16: SDNode<"SPUISD::VEC_SHL", SPUvecshift_type_v8i16, []>;
127 def SPUvec_srl_v8i16: SDNode<"SPUISD::VEC_SRL", SPUvecshift_type_v8i16, []>;
128 def SPUvec_sra_v8i16: SDNode<"SPUISD::VEC_SRA", SPUvecshift_type_v8i16, []>;
130 def SPUvec_shl_v4i32: SDNode<"SPUISD::VEC_SHL", SPUvecshift_type_v4i32, []>;
131 def SPUvec_srl_v4i32: SDNode<"SPUISD::VEC_SRL", SPUvecshift_type_v4i32, []>;
132 def SPUvec_sra_v4i32: SDNode<"SPUISD::VEC_SRA", SPUvecshift_type_v4i32, []>;
134 def SPUvec_rotl_v8i16: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type_v8i16, []>;
135 def SPUvec_rotl_v4i32: SDNode<"SPUISD::VEC_ROTL", SPUvecshift_type_v4i32, []>;
137 def SPUvec_rotr_v8i16: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type_v8i16, []>;
138 def SPUvec_rotr_v4i32: SDNode<"SPUISD::VEC_ROTR", SPUvecshift_type_v4i32, []>;
140 def SPUrotbytes_right_zfill: SDNode<"SPUISD::ROTBYTES_RIGHT_Z",
141 SPUvecshift_type_v16i8, []>;
142 def SPUrotbytes_right_sfill: SDNode<"SPUISD::ROTBYTES_RIGHT_S",
143 SPUvecshift_type_v16i8, []>;
144 def SPUrotbytes_left: SDNode<"SPUISD::ROTBYTES_LEFT",
145 SPUvecshift_type_v16i8, []>;
147 def SPUrotbytes_left_chained : SDNode<"SPUISD::ROTBYTES_LEFT_CHAINED",
148 SPUvecshift_type_v16i8, [SDNPHasChain]>;
150 // SPU form select mask for bytes, immediate
151 def SPUfsmbi_v16i8: SDNode<"SPUISD::FSMBI", SPUfsmbi_type_v16i8, []>;
152 def SPUfsmbi_v8i16: SDNode<"SPUISD::FSMBI", SPUfsmbi_type_v8i16, []>;
153 def SPUfsmbi_v4i32: SDNode<"SPUISD::FSMBI", SPUfsmbi_type_v4i32, []>;
155 // SPU select bits instruction
156 def SPUselb_v16i8: SDNode<"SPUISD::SELB", SPUselb_type_v16i8, []>;
157 def SPUselb_v8i16: SDNode<"SPUISD::SELB", SPUselb_type_v8i16, []>;
158 def SPUselb_v4i32: SDNode<"SPUISD::SELB", SPUselb_type_v4i32, []>;
160 // SPU single precision floating point constant load
161 def SPUFPconstant: SDNode<"SPUISD::SFPConstant", SDTFPUnaryOp, []>;
163 // SPU floating point interpolate
164 def SPUinterpolate : SDNode<"SPUISD::FPInterp", SDTFPBinOp, []>;
166 // SPU floating point reciprocal estimate (used for fdiv)
167 def SPUreciprocalEst: SDNode<"SPUISD::FPRecipEst", SDTFPUnaryOp, []>;
169 def SDT_vec_promote : SDTypeProfile<1, 1, []>;
170 def SPUpromote_scalar: SDNode<"SPUISD::PROMOTE_SCALAR", SDT_vec_promote, []>;
172 def SPU_vec_demote : SDTypeProfile<1, 1, []>;
173 def SPUextract_elt0: SDNode<"SPUISD::EXTRACT_ELT0", SPU_vec_demote, []>;
174 def SPU_vec_demote_chained : SDTypeProfile<1, 2, []>;
175 def SPUextract_elt0_chained: SDNode<"SPUISD::EXTRACT_ELT0_CHAINED",
176 SPU_vec_demote_chained, [SDNPHasChain]>;
177 def SPUextract_i1_sext: SDNode<"SPUISD::EXTRACT_I1_SEXT", SPU_vec_demote, []>;
178 def SPUextract_i1_zext: SDNode<"SPUISD::EXTRACT_I1_ZEXT", SPU_vec_demote, []>;
179 def SPUextract_i8_sext: SDNode<"SPUISD::EXTRACT_I8_SEXT", SPU_vec_demote, []>;
180 def SPUextract_i8_zext: SDNode<"SPUISD::EXTRACT_I8_ZEXT", SPU_vec_demote, []>;
182 // Address high and low components, used for [r+r] type addressing
183 def SPUhi : SDNode<"SPUISD::Hi", SDTIntBinOp, []>;
184 def SPUlo : SDNode<"SPUISD::Lo", SDTIntBinOp, []>;
186 // PC-relative address
187 def SPUpcrel : SDNode<"SPUISD::PCRelAddr", SDTIntBinOp, []>;
189 // A-Form local store addresses
190 def SPUaform : SDNode<"SPUISD::AFormAddr", SDTIntBinOp, []>;
192 // D-Form "imm($reg)" addresses
193 def SPUdform : SDNode<"SPUISD::DFormAddr", SDTIntBinOp, []>;
195 // X-Form "$reg($reg)" addresses
196 def SPUxform : SDNode<"SPUISD::XFormAddr", SDTIntBinOp, []>;
198 // SPU 32-bit sign-extension to 64-bits
199 def SPUsext32_to_64: SDNode<"SPUISD::SEXT32TO64", SDTIntExtendOp, []>;
203 def SPUbrnz : SDNode<"SPUISD::BR_NOTZERO", SDTBrcond, [SDNPHasChain]>;
204 def SPUbrz : SDNode<"SPUISD::BR_ZERO", SDTBrcond, [SDNPHasChain]>;
205 /* def SPUbinz : SDNode<"SPUISD::BR_NOTZERO", SDTBrind, [SDNPHasChain]>;
206 def SPUbiz : SDNode<"SPUISD::BR_ZERO", SPUBrind, [SDNPHasChain]>; */
208 //===----------------------------------------------------------------------===//
209 // Constraints: (taken from PPCInstrInfo.td)
210 //===----------------------------------------------------------------------===//
212 class RegConstraint<string C> {
213 string Constraints = C;
216 class NoEncode<string E> {
217 string DisableEncoding = E;
220 //===----------------------------------------------------------------------===//
221 // Return (flag isn't quite what it means: the operations are flagged so that
222 // instruction scheduling doesn't disassociate them.)
223 //===----------------------------------------------------------------------===//
225 def retflag : SDNode<"SPUISD::RET_FLAG", SDTRet,
226 [SDNPHasChain, SDNPOptInFlag]>;