1 //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instruction Operands:
10 //===----------------------------------------------------------------------===//
12 def LO16 : SDNodeXForm<imm, [{
13 unsigned val = N->getValue();
14 // Transformation function: get the low 16 bits.
15 return getI32Imm(val & 0xffff);
18 def LO16_vec : SDNodeXForm<scalar_to_vector, [{
19 SDOperand OpVal(0, 0);
21 // Transformation function: get the low 16 bit immediate from a build_vector
23 assert(N->getOpcode() == ISD::BUILD_VECTOR
24 && "LO16_vec got something other than a BUILD_VECTOR");
26 // Get first constant operand...
27 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
28 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
30 OpVal = N->getOperand(i);
33 assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
34 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
35 return getI32Imm((unsigned)CN->getValue() & 0xffff);
38 // Transform an immediate, returning the high 16 bits shifted down:
39 def HI16 : SDNodeXForm<imm, [{
40 return getI32Imm((unsigned)N->getValue() >> 16);
43 // Transformation function: shift the high 16 bit immediate from a build_vector
44 // node into the low 16 bits, and return a 16-bit constant.
45 def HI16_vec : SDNodeXForm<scalar_to_vector, [{
46 SDOperand OpVal(0, 0);
48 assert(N->getOpcode() == ISD::BUILD_VECTOR
49 && "HI16_vec got something other than a BUILD_VECTOR");
51 // Get first constant operand...
52 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
53 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
55 OpVal = N->getOperand(i);
58 assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
59 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
60 return getI32Imm((unsigned)CN->getValue() >> 16);
63 // simm7 predicate - True if the immediate fits in an 7-bit signed
65 def simm7: PatLeaf<(imm), [{
66 int sextVal = int(N->getSignExtended());
67 return (sextVal >= -64 && sextVal <= 63);
70 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
72 def uimm7: PatLeaf<(imm), [{
73 return (N->getValue() <= 0x7f);
76 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
78 def immSExt8 : PatLeaf<(imm), [{
79 int Value = int(N->getSignExtended());
80 return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
83 // immU8: immediate, unsigned 8-bit quantity
84 def immU8 : PatLeaf<(imm), [{
85 return (N->getValue() <= 0xff);
88 // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
89 // extended field. Used by RI10Form instructions like 'ldq'.
90 def i64ImmSExt10 : PatLeaf<(imm), [{
91 return isI64IntS10Immediate(N);
94 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
95 // extended field. Used by RI10Form instructions like 'ldq'.
96 def i32ImmSExt10 : PatLeaf<(imm), [{
97 return isI32IntS10Immediate(N);
100 // i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
101 // field. Used by RI10Form instructions like 'ldq'.
102 def i32ImmUns10 : PatLeaf<(imm), [{
103 return isI32IntU10Immediate(N);
106 // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
107 // extended field. Used by RI10Form instructions like 'ldq'.
108 def i16ImmSExt10 : PatLeaf<(imm), [{
109 return isI16IntS10Immediate(N);
112 // i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
113 // value. Used by RI10Form instructions.
114 def i16ImmUns10 : PatLeaf<(imm), [{
115 return isI16IntU10Immediate(N);
118 def immSExt16 : PatLeaf<(imm), [{
119 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
122 return isIntS16Immediate(N, Ignored);
125 def immZExt16 : PatLeaf<(imm), [{
126 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
128 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
131 def immU16 : PatLeaf<(imm), [{
132 // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
133 return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
136 def imm18 : PatLeaf<(imm), [{
137 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
138 int Value = (int) N->getValue();
139 return ((Value & ((1 << 19) - 1)) == Value);
142 def lo16 : PatLeaf<(imm), [{
143 // lo16 predicate - returns true if the immediate has all zeros in the
144 // low order bits and is a 32-bit constant:
145 if (N->getValueType(0) == MVT::i32) {
146 uint32_t val = N->getValue();
147 return ((val & 0x0000ffff) == val);
153 def hi16 : PatLeaf<(imm), [{
154 // hi16 predicate - returns true if the immediate has all zeros in the
155 // low order bits and is a 32-bit constant:
156 if (N->getValueType(0) == MVT::i32) {
157 uint32_t val = uint32_t(N->getValue());
158 return ((val & 0xffff0000) == val);
159 } else if (N->getValueType(0) == MVT::i64) {
160 uint64_t val = N->getValue();
161 return ((val & 0xffff0000ULL) == val);
167 def bitshift : PatLeaf<(imm), [{
168 // bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
169 // (shift left quadword by bits immediate)
170 int64_t Val = N->getValue();
171 return (Val > 0 && Val <= 7);
174 //===----------------------------------------------------------------------===//
175 // Floating point operands:
176 //===----------------------------------------------------------------------===//
178 // Transform a float, returning the high 16 bits shifted down, as if
179 // the float was really an unsigned integer:
180 def HI16_f32 : SDNodeXForm<fpimm, [{
181 float fval = N->getValueAPF().convertToFloat();
182 return getI32Imm(FloatToBits(fval) >> 16);
185 // Transformation function on floats: get the low 16 bits as if the float was
186 // an unsigned integer.
187 def LO16_f32 : SDNodeXForm<fpimm, [{
188 float fval = N->getValueAPF().convertToFloat();
189 return getI32Imm(FloatToBits(fval) & 0xffff);
192 def FPimm_sext16 : SDNodeXForm<fpimm, [{
193 float fval = N->getValueAPF().convertToFloat();
194 return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
197 def FPimm_u18 : SDNodeXForm<fpimm, [{
198 float fval = N->getValueAPF().convertToFloat();
199 return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
202 def fpimmSExt16 : PatLeaf<(fpimm), [{
204 return isFPS16Immediate(N, Ignored);
207 // Does the SFP constant only have upp 16 bits set?
208 def hi16_f32 : PatLeaf<(fpimm), [{
209 if (N->getValueType(0) == MVT::f32) {
210 uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
211 return ((val & 0xffff0000) == val);
217 // Does the SFP constant fit into 18 bits?
218 def fpimm18 : PatLeaf<(fpimm), [{
219 if (N->getValueType(0) == MVT::f32) {
220 uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
221 return ((Value & ((1 << 19) - 1)) == Value);
227 //===----------------------------------------------------------------------===//
228 // 64-bit operands (TODO):
229 //===----------------------------------------------------------------------===//
231 //===----------------------------------------------------------------------===//
232 // build_vector operands:
233 //===----------------------------------------------------------------------===//
235 // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
236 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
237 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
238 def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
239 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
242 // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
243 // load, works in conjunction with its transform function. N.B.: This relies the
244 // incoming constant being a 16-bit quantity, where the upper and lower bytes
245 // are EXACTLY the same (e.g., 0x2a2a)
246 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
247 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
248 }], v16i8SExt8Imm_xform>;
250 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
251 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
252 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
253 def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
254 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
257 // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
258 // load, works in conjunction with its transform function. N.B.: This relies the
259 // incoming constant being a 16-bit quantity, where the upper and lower bytes
260 // are EXACTLY the same (e.g., 0x2a2a)
261 def v16i8U8Imm: PatLeaf<(build_vector), [{
262 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
263 }], v16i8U8Imm_xform>;
265 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
266 // immediate constant load for v8i16 vectors.
267 def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
268 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
271 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
272 // load, works in conjunction with its transform function.
273 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
274 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
275 }], v8i16SExt8Imm_xform>;
277 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
278 // immediate constant load for v8i16 vectors.
279 def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
280 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
283 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
284 // load, works in conjunction with its transform function.
285 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
286 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
287 }], v8i16SExt10Imm_xform>;
289 // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
290 // immediate constant load for v8i16 vectors.
291 def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
292 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
295 // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
296 // load, works in conjunction with its transform function.
297 def v8i16Uns10Imm: PatLeaf<(build_vector), [{
298 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
299 }], v8i16Uns10Imm_xform>;
301 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
302 // immediate constant load for v8i16 vectors.
303 def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
304 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
307 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
308 // load, works in conjunction with its transform function.
309 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
310 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
311 }], v8i16Uns16Imm_xform>;
313 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
314 // immediate constant load for v4i32 vectors.
315 def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
316 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
319 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
320 // load, works in conjunction with its transform function.
321 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
322 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
323 }], v4i32SExt10Imm_xform>;
325 // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
326 // immediate constant load for v4i32 vectors.
327 def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
328 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
331 // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
332 // load, works in conjunction with its transform function.
333 def v4i32Uns10Imm: PatLeaf<(build_vector), [{
334 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
335 }], v4i32Uns10Imm_xform>;
337 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
338 // immediate constant load for v4i32 vectors.
339 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
340 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
343 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
344 // load, works in conjunction with its transform function.
345 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
346 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
347 }], v4i32SExt16Imm_xform>;
349 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
350 // immediate constant load for v4i32 vectors.
351 def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
352 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
355 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
356 // works in conjunction with its transform function.
357 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
358 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
359 }], v4i32Uns18Imm_xform>;
361 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
363 def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
364 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
367 /// immILHUvec: Predicate test for a ILHU constant vector.
368 def immILHUvec: PatLeaf<(build_vector), [{
369 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
370 }], ILHUvec_get_imm>;
372 // Catch-all for any other i32 vector constants
373 def v4i32_get_imm: SDNodeXForm<build_vector, [{
374 return SPU::get_v4i32_imm(N, *CurDAG);
377 def v4i32Imm: PatLeaf<(build_vector), [{
378 return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
381 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
382 // immediate constant load for v2i64 vectors.
383 def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
384 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
387 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
388 // load, works in conjunction with its transform function.
389 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
390 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
391 }], v2i64SExt10Imm_xform>;
393 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
394 // immediate constant load for v2i64 vectors.
395 def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
396 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
399 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
400 // load, works in conjunction with its transform function.
401 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
402 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
403 }], v2i64SExt16Imm_xform>;
405 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
406 // immediate constant load for v2i64 vectors.
407 def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
408 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
411 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
412 // works in conjunction with its transform function.
413 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
414 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
415 }], v2i64Uns18Imm_xform>;
417 /// immILHUvec: Predicate test for a ILHU constant vector.
418 def immILHUvec_i64: PatLeaf<(build_vector), [{
419 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
420 }], ILHUvec_get_imm>;
422 // Catch-all for any other i32 vector constants
423 def v2i64_get_imm: SDNodeXForm<build_vector, [{
424 return SPU::get_v2i64_imm(N, *CurDAG);
427 def v2i64Imm: PatLeaf<(build_vector), [{
428 return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
431 //===----------------------------------------------------------------------===//
432 // Operand Definitions.
434 def s7imm: Operand<i8> {
435 let PrintMethod = "printS7ImmOperand";
438 def s7imm_i8: Operand<i8> {
439 let PrintMethod = "printS7ImmOperand";
442 def u7imm: Operand<i16> {
443 let PrintMethod = "printU7ImmOperand";
446 def u7imm_i8: Operand<i8> {
447 let PrintMethod = "printU7ImmOperand";
450 def u7imm_i32: Operand<i32> {
451 let PrintMethod = "printU7ImmOperand";
454 // Halfword, signed 10-bit constant
455 def s10imm : Operand<i16> {
456 let PrintMethod = "printS10ImmOperand";
459 def s10imm_i8: Operand<i8> {
460 let PrintMethod = "printS10ImmOperand";
463 def s10imm_i32: Operand<i32> {
464 let PrintMethod = "printS10ImmOperand";
467 def s10imm_i64: Operand<i64> {
468 let PrintMethod = "printS10ImmOperand";
471 // Unsigned 10-bit integers:
472 def u10imm: Operand<i16> {
473 let PrintMethod = "printU10ImmOperand";
476 def u10imm_i8: Operand<i8> {
477 let PrintMethod = "printU10ImmOperand";
480 def u10imm_i32: Operand<i32> {
481 let PrintMethod = "printU10ImmOperand";
484 def s16imm : Operand<i16> {
485 let PrintMethod = "printS16ImmOperand";
488 def s16imm_i8: Operand<i8> {
489 let PrintMethod = "printS16ImmOperand";
492 def s16imm_i32: Operand<i32> {
493 let PrintMethod = "printS16ImmOperand";
496 def s16imm_i64: Operand<i64> {
497 let PrintMethod = "printS16ImmOperand";
500 def s16imm_f32: Operand<f32> {
501 let PrintMethod = "printS16ImmOperand";
504 def s16imm_f64: Operand<f64> {
505 let PrintMethod = "printS16ImmOperand";
508 def u16imm_i64 : Operand<i64> {
509 let PrintMethod = "printU16ImmOperand";
512 def u16imm : Operand<i32> {
513 let PrintMethod = "printU16ImmOperand";
516 def f16imm : Operand<f32> {
517 let PrintMethod = "printU16ImmOperand";
520 def s18imm : Operand<i32> {
521 let PrintMethod = "printS18ImmOperand";
524 def u18imm : Operand<i32> {
525 let PrintMethod = "printU18ImmOperand";
528 def u18imm_i64 : Operand<i64> {
529 let PrintMethod = "printU18ImmOperand";
532 def f18imm : Operand<f32> {
533 let PrintMethod = "printU18ImmOperand";
536 def f18imm_f64 : Operand<f64> {
537 let PrintMethod = "printU18ImmOperand";
540 // Negated 7-bit halfword rotate immediate operands
541 def rothNeg7imm : Operand<i32> {
542 let PrintMethod = "printROTHNeg7Imm";
545 def rothNeg7imm_i16 : Operand<i16> {
546 let PrintMethod = "printROTHNeg7Imm";
549 // Negated 7-bit word rotate immediate operands
550 def rotNeg7imm : Operand<i32> {
551 let PrintMethod = "printROTNeg7Imm";
554 def rotNeg7imm_i16 : Operand<i16> {
555 let PrintMethod = "printROTNeg7Imm";
558 def target : Operand<OtherVT> {
559 let PrintMethod = "printBranchOperand";
562 // Absolute address call target
563 def calltarget : Operand<iPTR> {
564 let PrintMethod = "printCallOperand";
565 let MIOperandInfo = (ops u18imm:$calldest);
568 // Relative call target
569 def relcalltarget : Operand<iPTR> {
570 let PrintMethod = "printPCRelativeOperand";
571 let MIOperandInfo = (ops s16imm:$calldest);
575 def brtarget : Operand<OtherVT> {
576 let PrintMethod = "printPCRelativeOperand";
579 // Indirect call target
580 def indcalltarget : Operand<iPTR> {
581 let PrintMethod = "printCallOperand";
582 let MIOperandInfo = (ops ptr_rc:$calldest);
585 def symbolHi: Operand<i32> {
586 let PrintMethod = "printSymbolHi";
589 def symbolLo: Operand<i32> {
590 let PrintMethod = "printSymbolLo";
593 def symbolLSA: Operand<i32> {
594 let PrintMethod = "printSymbolLSA";
597 // memory s7imm(reg) operaand
598 def memri7 : Operand<iPTR> {
599 let PrintMethod = "printMemRegImmS7";
600 let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
603 // memory s10imm(reg) operand
604 def memri10 : Operand<iPTR> {
605 let PrintMethod = "printMemRegImmS10";
606 let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
609 // 256K local store address
610 // N.B.: The tblgen code generator expects to have two operands, an offset
611 // and a pointer. Of these, only the immediate is actually used.
612 def addr256k : Operand<iPTR> {
613 let PrintMethod = "printAddr256K";
614 let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
617 // memory s18imm(reg) operand
618 def memri18 : Operand<iPTR> {
619 let PrintMethod = "printMemRegImmS18";
620 let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
623 // memory register + register operand
624 def memrr : Operand<iPTR> {
625 let PrintMethod = "printMemRegReg";
626 let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
629 // Define SPU-specific addressing modes: These come in three basic
632 // D-form : [r+I10] (10-bit signed offset + reg)
633 // X-form : [r+r] (reg+reg)
634 // A-form : abs (256K LSA offset)
635 // D-form(2): [r+I7] (7-bit signed offset + reg)
637 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>;
638 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>;
639 def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>;
640 def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>;