1 //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instruction Operands:
10 //===----------------------------------------------------------------------===//
12 // TO_IMM32 - Convert an i8/i16 to i32.
13 def TO_IMM32 : SDNodeXForm<imm, [{
14 return getI32Imm(N->getZExtValue());
17 // TO_IMM16 - Convert an i8/i32 to i16.
18 def TO_IMM16 : SDNodeXForm<imm, [{
19 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i16);
23 def LO16 : SDNodeXForm<imm, [{
24 unsigned val = N->getZExtValue();
25 // Transformation function: get the low 16 bits.
26 return getI32Imm(val & 0xffff);
29 def LO16_vec : SDNodeXForm<scalar_to_vector, [{
32 // Transformation function: get the low 16 bit immediate from a build_vector
34 assert(N->getOpcode() == ISD::BUILD_VECTOR
35 && "LO16_vec got something other than a BUILD_VECTOR");
37 // Get first constant operand...
38 for (unsigned i = 0, e = N->getNumOperands();
39 OpVal.getNode() == 0 && i != e; ++i) {
40 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
41 if (OpVal.getNode() == 0)
42 OpVal = N->getOperand(i);
45 assert(OpVal.getNode() != 0 && "LO16_vec did not locate a <defined> node");
46 ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
47 return getI32Imm((unsigned)CN->getZExtValue() & 0xffff);
50 // Transform an immediate, returning the high 16 bits shifted down:
51 def HI16 : SDNodeXForm<imm, [{
52 return getI32Imm((unsigned)N->getZExtValue() >> 16);
55 // Transformation function: shift the high 16 bit immediate from a build_vector
56 // node into the low 16 bits, and return a 16-bit constant.
57 def HI16_vec : SDNodeXForm<scalar_to_vector, [{
60 assert(N->getOpcode() == ISD::BUILD_VECTOR
61 && "HI16_vec got something other than a BUILD_VECTOR");
63 // Get first constant operand...
64 for (unsigned i = 0, e = N->getNumOperands();
65 OpVal.getNode() == 0 && i != e; ++i) {
66 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
67 if (OpVal.getNode() == 0)
68 OpVal = N->getOperand(i);
71 assert(OpVal.getNode() != 0 && "HI16_vec did not locate a <defined> node");
72 ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
73 return getI32Imm((unsigned)CN->getZExtValue() >> 16);
76 // simm7 predicate - True if the immediate fits in an 7-bit signed
78 def simm7: PatLeaf<(imm), [{
79 int sextVal = int(N->getSExtValue());
80 return (sextVal >= -64 && sextVal <= 63);
83 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
85 def uimm7: PatLeaf<(imm), [{
86 return (N->getZExtValue() <= 0x7f);
89 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
91 def immSExt8 : PatLeaf<(imm), [{
92 int Value = int(N->getSExtValue());
93 return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
96 // immU8: immediate, unsigned 8-bit quantity
97 def immU8 : PatLeaf<(imm), [{
98 return (N->getZExtValue() <= 0xff);
101 // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
102 // extended field. Used by RI10Form instructions like 'ldq'.
103 def i64ImmSExt10 : PatLeaf<(imm), [{
104 return isI64IntS10Immediate(N);
107 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
108 // extended field. Used by RI10Form instructions like 'ldq'.
109 def i32ImmSExt10 : PatLeaf<(imm), [{
110 return isI32IntS10Immediate(N);
113 // i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
114 // field. Used by RI10Form instructions like 'ldq'.
115 def i32ImmUns10 : PatLeaf<(imm), [{
116 return isI32IntU10Immediate(N);
119 // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
120 // extended field. Used by RI10Form instructions like 'ldq'.
121 def i16ImmSExt10 : PatLeaf<(imm), [{
122 return isI16IntS10Immediate(N);
125 // i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
126 // value. Used by RI10Form instructions.
127 def i16ImmUns10 : PatLeaf<(imm), [{
128 return isI16IntU10Immediate(N);
131 def immSExt16 : PatLeaf<(imm), [{
132 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
135 return isIntS16Immediate(N, Ignored);
138 def immZExt16 : PatLeaf<(imm), [{
139 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
141 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
144 def immU16 : PatLeaf<(imm), [{
145 // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
146 return (uint64_t)N->getZExtValue() == (N->getZExtValue() & 0xffff);
149 def imm18 : PatLeaf<(imm), [{
150 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
151 int Value = (int) N->getZExtValue();
152 return ((Value & ((1 << 19) - 1)) == Value);
155 def lo16 : PatLeaf<(imm), [{
156 // lo16 predicate - returns true if the immediate has all zeros in the
157 // low order bits and is a 32-bit constant:
158 if (N->getValueType(0) == MVT::i32) {
159 uint32_t val = N->getZExtValue();
160 return ((val & 0x0000ffff) == val);
166 def hi16 : PatLeaf<(imm), [{
167 // hi16 predicate - returns true if the immediate has all zeros in the
168 // low order bits and is a 32-bit constant:
169 if (N->getValueType(0) == MVT::i32) {
170 uint32_t val = uint32_t(N->getZExtValue());
171 return ((val & 0xffff0000) == val);
172 } else if (N->getValueType(0) == MVT::i64) {
173 uint64_t val = N->getZExtValue();
174 return ((val & 0xffff0000ULL) == val);
180 def bitshift : PatLeaf<(imm), [{
181 // bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
182 // (shift left quadword by bits immediate)
183 int64_t Val = N->getZExtValue();
184 return (Val > 0 && Val <= 7);
187 //===----------------------------------------------------------------------===//
188 // Floating point operands:
189 //===----------------------------------------------------------------------===//
191 // Transform a float, returning the high 16 bits shifted down, as if
192 // the float was really an unsigned integer:
193 def HI16_f32 : SDNodeXForm<fpimm, [{
194 float fval = N->getValueAPF().convertToFloat();
195 return getI32Imm(FloatToBits(fval) >> 16);
198 // Transformation function on floats: get the low 16 bits as if the float was
199 // an unsigned integer.
200 def LO16_f32 : SDNodeXForm<fpimm, [{
201 float fval = N->getValueAPF().convertToFloat();
202 return getI32Imm(FloatToBits(fval) & 0xffff);
205 def FPimm_sext16 : SDNodeXForm<fpimm, [{
206 float fval = N->getValueAPF().convertToFloat();
207 return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
210 def FPimm_u18 : SDNodeXForm<fpimm, [{
211 float fval = N->getValueAPF().convertToFloat();
212 return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
215 def fpimmSExt16 : PatLeaf<(fpimm), [{
217 return isFPS16Immediate(N, Ignored);
220 // Does the SFP constant only have upp 16 bits set?
221 def hi16_f32 : PatLeaf<(fpimm), [{
222 if (N->getValueType(0) == MVT::f32) {
223 uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
224 return ((val & 0xffff0000) == val);
230 // Does the SFP constant fit into 18 bits?
231 def fpimm18 : PatLeaf<(fpimm), [{
232 if (N->getValueType(0) == MVT::f32) {
233 uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
234 return ((Value & ((1 << 19) - 1)) == Value);
240 //===----------------------------------------------------------------------===//
241 // 64-bit operands (TODO):
242 //===----------------------------------------------------------------------===//
244 //===----------------------------------------------------------------------===//
245 // build_vector operands:
246 //===----------------------------------------------------------------------===//
248 // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
249 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
250 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
251 def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
252 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
255 // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
256 // load, works in conjunction with its transform function. N.B.: This relies the
257 // incoming constant being a 16-bit quantity, where the upper and lower bytes
258 // are EXACTLY the same (e.g., 0x2a2a)
259 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
260 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
261 }], v16i8SExt8Imm_xform>;
263 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
264 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
265 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
266 def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
267 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
270 // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
271 // load, works in conjunction with its transform function. N.B.: This relies the
272 // incoming constant being a 16-bit quantity, where the upper and lower bytes
273 // are EXACTLY the same (e.g., 0x2a2a)
274 def v16i8U8Imm: PatLeaf<(build_vector), [{
275 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
276 }], v16i8U8Imm_xform>;
278 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
279 // immediate constant load for v8i16 vectors.
280 def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
281 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
284 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
285 // load, works in conjunction with its transform function.
286 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
287 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
288 }], v8i16SExt8Imm_xform>;
290 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
291 // immediate constant load for v8i16 vectors.
292 def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
293 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
296 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
297 // load, works in conjunction with its transform function.
298 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
299 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
300 }], v8i16SExt10Imm_xform>;
302 // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
303 // immediate constant load for v8i16 vectors.
304 def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
305 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
308 // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
309 // load, works in conjunction with its transform function.
310 def v8i16Uns10Imm: PatLeaf<(build_vector), [{
311 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
312 }], v8i16Uns10Imm_xform>;
314 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
315 // immediate constant load for v8i16 vectors.
316 def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
317 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
320 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
321 // load, works in conjunction with its transform function.
322 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
323 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
324 }], v8i16Uns16Imm_xform>;
326 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
327 // immediate constant load for v4i32 vectors.
328 def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
329 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
332 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
333 // load, works in conjunction with its transform function.
334 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
335 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
336 }], v4i32SExt10Imm_xform>;
338 // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
339 // immediate constant load for v4i32 vectors.
340 def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
341 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
344 // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
345 // load, works in conjunction with its transform function.
346 def v4i32Uns10Imm: PatLeaf<(build_vector), [{
347 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
348 }], v4i32Uns10Imm_xform>;
350 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
351 // immediate constant load for v4i32 vectors.
352 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
353 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
356 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
357 // load, works in conjunction with its transform function.
358 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
359 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
360 }], v4i32SExt16Imm_xform>;
362 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
363 // immediate constant load for v4i32 vectors.
364 def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
365 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
368 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
369 // works in conjunction with its transform function.
370 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
371 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0;
372 }], v4i32Uns18Imm_xform>;
374 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
376 def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
377 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
380 /// immILHUvec: Predicate test for a ILHU constant vector.
381 def immILHUvec: PatLeaf<(build_vector), [{
382 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0;
383 }], ILHUvec_get_imm>;
385 // Catch-all for any other i32 vector constants
386 def v4i32_get_imm: SDNodeXForm<build_vector, [{
387 return SPU::get_v4i32_imm(N, *CurDAG);
390 def v4i32Imm: PatLeaf<(build_vector), [{
391 return SPU::get_v4i32_imm(N, *CurDAG).getNode() != 0;
394 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
395 // immediate constant load for v2i64 vectors.
396 def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
397 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
400 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
401 // load, works in conjunction with its transform function.
402 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
403 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0;
404 }], v2i64SExt10Imm_xform>;
406 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
407 // immediate constant load for v2i64 vectors.
408 def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
409 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
412 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
413 // load, works in conjunction with its transform function.
414 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
415 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0;
416 }], v2i64SExt16Imm_xform>;
418 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
419 // immediate constant load for v2i64 vectors.
420 def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
421 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
424 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
425 // works in conjunction with its transform function.
426 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
427 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0;
428 }], v2i64Uns18Imm_xform>;
430 /// immILHUvec: Predicate test for a ILHU constant vector.
431 def immILHUvec_i64: PatLeaf<(build_vector), [{
432 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0;
433 }], ILHUvec_get_imm>;
435 // Catch-all for any other i32 vector constants
436 def v2i64_get_imm: SDNodeXForm<build_vector, [{
437 return SPU::get_v2i64_imm(N, *CurDAG);
440 def v2i64Imm: PatLeaf<(build_vector), [{
441 return SPU::get_v2i64_imm(N, *CurDAG).getNode() != 0;
444 //===----------------------------------------------------------------------===//
445 // Operand Definitions.
447 def s7imm: Operand<i8> {
448 let PrintMethod = "printS7ImmOperand";
451 def s7imm_i8: Operand<i8> {
452 let PrintMethod = "printS7ImmOperand";
455 def u7imm: Operand<i16> {
456 let PrintMethod = "printU7ImmOperand";
459 def u7imm_i8: Operand<i8> {
460 let PrintMethod = "printU7ImmOperand";
463 def u7imm_i32: Operand<i32> {
464 let PrintMethod = "printU7ImmOperand";
467 // Halfword, signed 10-bit constant
468 def s10imm : Operand<i16> {
469 let PrintMethod = "printS10ImmOperand";
472 def s10imm_i8: Operand<i8> {
473 let PrintMethod = "printS10ImmOperand";
476 def s10imm_i32: Operand<i32> {
477 let PrintMethod = "printS10ImmOperand";
480 def s10imm_i64: Operand<i64> {
481 let PrintMethod = "printS10ImmOperand";
484 // Unsigned 10-bit integers:
485 def u10imm: Operand<i16> {
486 let PrintMethod = "printU10ImmOperand";
489 def u10imm_i8: Operand<i8> {
490 let PrintMethod = "printU10ImmOperand";
493 def u10imm_i32: Operand<i32> {
494 let PrintMethod = "printU10ImmOperand";
497 def s16imm : Operand<i16> {
498 let PrintMethod = "printS16ImmOperand";
501 def s16imm_i8: Operand<i8> {
502 let PrintMethod = "printS16ImmOperand";
505 def s16imm_i32: Operand<i32> {
506 let PrintMethod = "printS16ImmOperand";
509 def s16imm_i64: Operand<i64> {
510 let PrintMethod = "printS16ImmOperand";
513 def s16imm_f32: Operand<f32> {
514 let PrintMethod = "printS16ImmOperand";
517 def s16imm_f64: Operand<f64> {
518 let PrintMethod = "printS16ImmOperand";
521 def u16imm_i64 : Operand<i64> {
522 let PrintMethod = "printU16ImmOperand";
525 def u16imm_i32 : Operand<i32> {
526 let PrintMethod = "printU16ImmOperand";
529 def u16imm : Operand<i16> {
530 let PrintMethod = "printU16ImmOperand";
533 def f16imm : Operand<f32> {
534 let PrintMethod = "printU16ImmOperand";
537 def s18imm : Operand<i32> {
538 let PrintMethod = "printS18ImmOperand";
541 def u18imm : Operand<i32> {
542 let PrintMethod = "printU18ImmOperand";
545 def u18imm_i64 : Operand<i64> {
546 let PrintMethod = "printU18ImmOperand";
549 def f18imm : Operand<f32> {
550 let PrintMethod = "printU18ImmOperand";
553 def f18imm_f64 : Operand<f64> {
554 let PrintMethod = "printU18ImmOperand";
557 // Negated 7-bit halfword rotate immediate operands
558 def rothNeg7imm : Operand<i32> {
559 let PrintMethod = "printROTHNeg7Imm";
562 def rothNeg7imm_i16 : Operand<i16> {
563 let PrintMethod = "printROTHNeg7Imm";
566 // Negated 7-bit word rotate immediate operands
567 def rotNeg7imm : Operand<i32> {
568 let PrintMethod = "printROTNeg7Imm";
571 def rotNeg7imm_i16 : Operand<i16> {
572 let PrintMethod = "printROTNeg7Imm";
575 def rotNeg7imm_i8 : Operand<i8> {
576 let PrintMethod = "printROTNeg7Imm";
579 def target : Operand<OtherVT> {
580 let PrintMethod = "printBranchOperand";
583 // Absolute address call target
584 def calltarget : Operand<iPTR> {
585 let PrintMethod = "printCallOperand";
586 let MIOperandInfo = (ops u18imm:$calldest);
589 // PC relative call target
590 def relcalltarget : Operand<iPTR> {
591 let PrintMethod = "printPCRelativeOperand";
592 let MIOperandInfo = (ops s16imm:$calldest);
596 def brtarget : Operand<OtherVT> {
597 let PrintMethod = "printPCRelativeOperand";
600 // Hint for branch target
601 def hbrtarget : Operand<OtherVT> {
602 let PrintMethod = "printHBROperand";
605 // Indirect call target
606 def indcalltarget : Operand<iPTR> {
607 let PrintMethod = "printCallOperand";
608 let MIOperandInfo = (ops ptr_rc:$calldest);
611 def symbolHi: Operand<i32> {
612 let PrintMethod = "printSymbolHi";
615 def symbolLo: Operand<i32> {
616 let PrintMethod = "printSymbolLo";
619 def symbolLSA: Operand<i32> {
620 let PrintMethod = "printSymbolLSA";
623 // Shuffle address memory operaand [s7imm(reg) d-format]
624 def shufaddr : Operand<iPTR> {
625 let PrintMethod = "printShufAddr";
626 let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
629 // memory s10imm(reg) operand
630 def dformaddr : Operand<iPTR> {
631 let PrintMethod = "printDFormAddr";
632 let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
635 // 256K local store address
636 // N.B.: The tblgen code generator expects to have two operands, an offset
637 // and a pointer. Of these, only the immediate is actually used.
638 def addr256k : Operand<iPTR> {
639 let PrintMethod = "printAddr256K";
640 let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
643 // memory s18imm(reg) operand
644 def memri18 : Operand<iPTR> {
645 let PrintMethod = "printMemRegImmS18";
646 let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
649 // memory register + register operand
650 def memrr : Operand<iPTR> {
651 let PrintMethod = "printMemRegReg";
652 let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
655 // Define SPU-specific addressing modes: These come in three basic
658 // D-form : [r+I10] (10-bit signed offset + reg)
659 // X-form : [r+r] (reg+reg)
660 // A-form : abs (256K LSA offset)
661 // D-form(2): [r+I7] (7-bit signed offset + reg)
663 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>;
664 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>;
665 def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>;
666 def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>;