1 //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instruction Operands:
10 //===----------------------------------------------------------------------===//
12 def LO16 : SDNodeXForm<imm, [{
13 unsigned val = N->getValue();
14 // Transformation function: get the low 16 bits.
15 return getI32Imm(val & 0xffff);
18 def LO16_vec : SDNodeXForm<scalar_to_vector, [{
19 SDOperand OpVal(0, 0);
21 // Transformation function: get the low 16 bit immediate from a build_vector
23 assert(N->getOpcode() == ISD::BUILD_VECTOR
24 && "LO16_vec got something other than a BUILD_VECTOR");
26 // Get first constant operand...
27 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
28 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
30 OpVal = N->getOperand(i);
33 assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
34 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
35 return getI32Imm((unsigned)CN->getValue() & 0xffff);
38 // Transform an immediate, returning the high 16 bits shifted down:
39 def HI16 : SDNodeXForm<imm, [{
40 return getI32Imm((unsigned)N->getValue() >> 16);
43 // Transformation function: shift the high 16 bit immediate from a build_vector
44 // node into the low 16 bits, and return a 16-bit constant.
45 def HI16_vec : SDNodeXForm<scalar_to_vector, [{
46 SDOperand OpVal(0, 0);
48 assert(N->getOpcode() == ISD::BUILD_VECTOR
49 && "HI16_vec got something other than a BUILD_VECTOR");
51 // Get first constant operand...
52 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
53 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
55 OpVal = N->getOperand(i);
58 assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
59 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
60 return getI32Imm((unsigned)CN->getValue() >> 16);
63 // simm7 predicate - True if the immediate fits in an 7-bit signed
65 def simm7: PatLeaf<(imm), [{
66 int sextVal = ((((int) N->getValue()) << 25) >> 25);
67 return (sextVal >= -64 && sextVal <= 63);
70 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
72 def uimm7: PatLeaf<(imm), [{
73 return (N->getValue() <= 0x7f);
76 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
78 def immSExt8 : PatLeaf<(imm), [{
79 int Value = (int) N->getValue();
80 int Value8 = (Value << 24) >> 24;
81 return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
84 // immU8: immediate, unsigned 8-bit quantity
85 def immU8 : PatLeaf<(imm), [{
86 return (N->getValue() <= 0xff);
89 // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
90 // extended field. Used by RI10Form instructions like 'ldq'.
91 def i64ImmSExt10 : PatLeaf<(imm), [{
92 return isI64IntS10Immediate(N);
95 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
96 // extended field. Used by RI10Form instructions like 'ldq'.
97 def i32ImmSExt10 : PatLeaf<(imm), [{
98 return isI32IntS10Immediate(N);
101 // i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
102 // field. Used by RI10Form instructions like 'ldq'.
103 def i32ImmUns10 : PatLeaf<(imm), [{
104 return isI32IntU10Immediate(N);
107 // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
108 // extended field. Used by RI10Form instructions like 'ldq'.
109 def i16ImmSExt10 : PatLeaf<(imm), [{
110 return isI16IntS10Immediate(N);
113 // i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
114 // value. Used by RI10Form instructions.
115 def i16ImmUns10 : PatLeaf<(imm), [{
116 return isI16IntU10Immediate(N);
119 def immSExt16 : PatLeaf<(imm), [{
120 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
123 return isIntS16Immediate(N, Ignored);
126 def immZExt16 : PatLeaf<(imm), [{
127 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
129 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
132 def immU16 : PatLeaf<(imm), [{
133 // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
134 return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
137 def imm18 : PatLeaf<(imm), [{
138 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
139 int Value = (int) N->getValue();
140 return ((Value & ((1 << 19) - 1)) == Value);
143 def hi16 : PatLeaf<(imm), [{
144 // hi16 predicate - returns true if the immediate has all zeros in the
145 // low order bits and is a 32-bit constant:
146 if (N->getValueType(0) == MVT::i32) {
147 uint32_t val = N->getValue();
148 return ((val & 0xffff0000) == val);
154 //===----------------------------------------------------------------------===//
155 // Floating point operands:
156 //===----------------------------------------------------------------------===//
158 // Transform a float, returning the high 16 bits shifted down, as if
159 // the float was really an unsigned integer:
160 def HI16_f32 : SDNodeXForm<fpimm, [{
161 float fval = N->getValueAPF().convertToFloat();
162 return getI32Imm(FloatToBits(fval) >> 16);
165 // Transformation function on floats: get the low 16 bits as if the float was
166 // an unsigned integer.
167 def LO16_f32 : SDNodeXForm<fpimm, [{
168 float fval = N->getValueAPF().convertToFloat();
169 return getI32Imm(FloatToBits(fval) & 0xffff);
172 def FPimm_sext16 : SDNodeXForm<fpimm, [{
173 float fval = N->getValueAPF().convertToFloat();
174 return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
177 def FPimm_u18 : SDNodeXForm<fpimm, [{
178 float fval = N->getValueAPF().convertToFloat();
179 return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
182 def fpimmSExt16 : PatLeaf<(fpimm), [{
184 return isFPS16Immediate(N, Ignored);
187 // Does the SFP constant only have upp 16 bits set?
188 def hi16_f32 : PatLeaf<(fpimm), [{
189 if (N->getValueType(0) == MVT::f32) {
190 uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
191 return ((val & 0xffff0000) == val);
197 // Does the SFP constant fit into 18 bits?
198 def fpimm18 : PatLeaf<(fpimm), [{
199 if (N->getValueType(0) == MVT::f32) {
200 uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
201 return ((Value & ((1 << 19) - 1)) == Value);
207 //===----------------------------------------------------------------------===//
208 // 64-bit operands (TODO):
209 //===----------------------------------------------------------------------===//
211 //===----------------------------------------------------------------------===//
212 // build_vector operands:
213 //===----------------------------------------------------------------------===//
215 // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
216 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
217 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
218 def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
219 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
222 // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
223 // load, works in conjunction with its transform function. N.B.: This relies the
224 // incoming constant being a 16-bit quantity, where the upper and lower bytes
225 // are EXACTLY the same (e.g., 0x2a2a)
226 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
227 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
228 }], v16i8SExt8Imm_xform>;
230 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
231 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
232 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
233 def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
234 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
237 // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
238 // load, works in conjunction with its transform function. N.B.: This relies the
239 // incoming constant being a 16-bit quantity, where the upper and lower bytes
240 // are EXACTLY the same (e.g., 0x2a2a)
241 def v16i8U8Imm: PatLeaf<(build_vector), [{
242 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
243 }], v16i8U8Imm_xform>;
245 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
246 // immediate constant load for v8i16 vectors.
247 def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
248 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
251 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
252 // load, works in conjunction with its transform function.
253 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
254 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
255 }], v8i16SExt8Imm_xform>;
257 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
258 // immediate constant load for v8i16 vectors.
259 def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
260 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
263 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
264 // load, works in conjunction with its transform function.
265 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
266 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
267 }], v8i16SExt10Imm_xform>;
269 // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
270 // immediate constant load for v8i16 vectors.
271 def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
272 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
275 // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
276 // load, works in conjunction with its transform function.
277 def v8i16Uns10Imm: PatLeaf<(build_vector), [{
278 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
279 }], v8i16Uns10Imm_xform>;
281 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
282 // immediate constant load for v8i16 vectors.
283 def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
284 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
287 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
288 // load, works in conjunction with its transform function.
289 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
290 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
291 }], v8i16Uns16Imm_xform>;
293 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
294 // immediate constant load for v4i32 vectors.
295 def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
296 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
299 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
300 // load, works in conjunction with its transform function.
301 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
302 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
303 }], v4i32SExt10Imm_xform>;
305 // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
306 // immediate constant load for v4i32 vectors.
307 def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
308 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
311 // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
312 // load, works in conjunction with its transform function.
313 def v4i32Uns10Imm: PatLeaf<(build_vector), [{
314 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
315 }], v4i32Uns10Imm_xform>;
317 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
318 // immediate constant load for v4i32 vectors.
319 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
320 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
323 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
324 // load, works in conjunction with its transform function.
325 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
326 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
327 }], v4i32SExt16Imm_xform>;
329 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
330 // immediate constant load for v4i32 vectors.
331 def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
332 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
335 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
336 // works in conjunction with its transform function.
337 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
338 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
339 }], v4i32Uns18Imm_xform>;
341 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
343 def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
344 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
347 /// immILHUvec: Predicate test for a ILHU constant vector.
348 def immILHUvec: PatLeaf<(build_vector), [{
349 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
350 }], ILHUvec_get_imm>;
352 // Catch-all for any other i32 vector constants
353 def v4i32_get_imm: SDNodeXForm<build_vector, [{
354 return SPU::get_v4i32_imm(N, *CurDAG);
357 def v4i32Imm: PatLeaf<(build_vector), [{
358 return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
361 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
362 // immediate constant load for v2i64 vectors.
363 def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
364 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
367 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
368 // load, works in conjunction with its transform function.
369 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
370 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
371 }], v2i64SExt10Imm_xform>;
373 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
374 // immediate constant load for v2i64 vectors.
375 def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
376 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
379 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
380 // load, works in conjunction with its transform function.
381 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
382 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
383 }], v2i64SExt16Imm_xform>;
385 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
386 // immediate constant load for v2i64 vectors.
387 def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
388 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
391 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
392 // works in conjunction with its transform function.
393 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
394 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
395 }], v2i64Uns18Imm_xform>;
397 /// immILHUvec: Predicate test for a ILHU constant vector.
398 def immILHUvec_i64: PatLeaf<(build_vector), [{
399 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
400 }], ILHUvec_get_imm>;
402 // Catch-all for any other i32 vector constants
403 def v2i64_get_imm: SDNodeXForm<build_vector, [{
404 return SPU::get_v2i64_imm(N, *CurDAG);
407 def v2i64Imm: PatLeaf<(build_vector), [{
408 return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
411 //===----------------------------------------------------------------------===//
412 // Operand Definitions.
414 def s7imm: Operand<i16> {
415 let PrintMethod = "printS7ImmOperand";
418 def u7imm: Operand<i16> {
419 let PrintMethod = "printU7ImmOperand";
422 def u7imm_i8: Operand<i8> {
423 let PrintMethod = "printU7ImmOperand";
426 def u7imm_i32: Operand<i32> {
427 let PrintMethod = "printU7ImmOperand";
430 // Halfword, signed 10-bit constant
431 def s10imm : Operand<i16> {
432 let PrintMethod = "printS10ImmOperand";
435 def s10imm_i32: Operand<i32> {
436 let PrintMethod = "printS10ImmOperand";
439 def s10imm_i64: Operand<i64> {
440 let PrintMethod = "printS10ImmOperand";
443 // Unsigned 10-bit integers:
444 def u10imm: Operand<i16> {
445 let PrintMethod = "printU10ImmOperand";
448 def u10imm_i8: Operand<i8> {
449 let PrintMethod = "printU10ImmOperand";
452 def u10imm_i32: Operand<i32> {
453 let PrintMethod = "printU10ImmOperand";
456 def s16imm : Operand<i16> {
457 let PrintMethod = "printS16ImmOperand";
460 def s16imm_i8: Operand<i8> {
461 let PrintMethod = "printS16ImmOperand";
464 def s16imm_i32: Operand<i32> {
465 let PrintMethod = "printS16ImmOperand";
468 def s16imm_i64: Operand<i64> {
469 let PrintMethod = "printS16ImmOperand";
472 def s16imm_f32: Operand<f32> {
473 let PrintMethod = "printS16ImmOperand";
476 def s16imm_f64: Operand<f64> {
477 let PrintMethod = "printS16ImmOperand";
480 def u16imm : Operand<i32> {
481 let PrintMethod = "printU16ImmOperand";
484 def f16imm : Operand<f32> {
485 let PrintMethod = "printU16ImmOperand";
488 def s18imm : Operand<i32> {
489 let PrintMethod = "printS18ImmOperand";
492 def u18imm : Operand<i32> {
493 let PrintMethod = "printU18ImmOperand";
496 def u18imm_i64 : Operand<i64> {
497 let PrintMethod = "printU18ImmOperand";
500 def f18imm : Operand<f32> {
501 let PrintMethod = "printU18ImmOperand";
504 def f18imm_f64 : Operand<f64> {
505 let PrintMethod = "printU18ImmOperand";
508 // Negated 7-bit halfword rotate immediate operands
509 def rothNeg7imm : Operand<i32> {
510 let PrintMethod = "printROTHNeg7Imm";
513 def rothNeg7imm_i16 : Operand<i16> {
514 let PrintMethod = "printROTHNeg7Imm";
517 // Negated 7-bit word rotate immediate operands
518 def rotNeg7imm : Operand<i32> {
519 let PrintMethod = "printROTNeg7Imm";
522 def rotNeg7imm_i16 : Operand<i16> {
523 let PrintMethod = "printROTNeg7Imm";
526 // Floating point immediate operands
527 def f32imm : Operand<f32>;
529 def target : Operand<OtherVT> {
530 let PrintMethod = "printBranchOperand";
533 // Absolute address call target
534 def calltarget : Operand<iPTR> {
535 let PrintMethod = "printCallOperand";
536 let MIOperandInfo = (ops u18imm:$calldest);
539 // Relative call target
540 def relcalltarget : Operand<iPTR> {
541 let PrintMethod = "printPCRelativeOperand";
542 let MIOperandInfo = (ops s16imm:$calldest);
546 def brtarget : Operand<OtherVT> {
547 let PrintMethod = "printPCRelativeOperand";
550 // Indirect call target
551 def indcalltarget : Operand<iPTR> {
552 let PrintMethod = "printCallOperand";
553 let MIOperandInfo = (ops ptr_rc:$calldest);
556 def symbolHi: Operand<i32> {
557 let PrintMethod = "printSymbolHi";
560 def symbolLo: Operand<i32> {
561 let PrintMethod = "printSymbolLo";
564 def symbolLSA: Operand<i32> {
565 let PrintMethod = "printSymbolLSA";
568 // memory s7imm(reg) operaand
569 def memri7 : Operand<iPTR> {
570 let PrintMethod = "printMemRegImmS7";
571 let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
574 // memory s10imm(reg) operand
575 def memri10 : Operand<iPTR> {
576 let PrintMethod = "printMemRegImmS10";
577 let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
580 // 256K local store address
581 // N.B.: The tblgen code generator expects to have two operands, an offset
582 // and a pointer. Of these, only the immediate is actually used.
583 def addr256k : Operand<iPTR> {
584 let PrintMethod = "printAddr256K";
585 let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
588 // memory s18imm(reg) operand
589 def memri18 : Operand<iPTR> {
590 let PrintMethod = "printMemRegImmS18";
591 let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
594 // memory register + register operand
595 def memrr : Operand<iPTR> {
596 let PrintMethod = "printMemRegReg";
597 let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
600 // Define SPU-specific addressing modes: These come in three basic
603 // D-form : [r+I10] (10-bit signed offset + reg)
604 // X-form : [r+r] (reg+reg)
605 // A-form : abs (256K LSA offset)
606 // D-form(2): [r+I7] (7-bit signed offset + reg)
608 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>;
609 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>;
610 def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>;
611 def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>;