1 //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
10 // Cell SPU Instruction Operands:
11 //===----------------------------------------------------------------------===//
13 def LO16 : SDNodeXForm<imm, [{
14 unsigned val = N->getValue();
15 // Transformation function: get the low 16 bits.
16 return getI32Imm(val & 0xffff);
19 def LO16_vec : SDNodeXForm<scalar_to_vector, [{
20 SDOperand OpVal(0, 0);
22 // Transformation function: get the low 16 bit immediate from a build_vector
24 assert(N->getOpcode() == ISD::BUILD_VECTOR
25 && "LO16_vec got something other than a BUILD_VECTOR");
27 // Get first constant operand...
28 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
29 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
31 OpVal = N->getOperand(i);
34 assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
35 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
36 return getI32Imm((unsigned)CN->getValue() & 0xffff);
39 // Transform an immediate, returning the high 16 bits shifted down:
40 def HI16 : SDNodeXForm<imm, [{
41 return getI32Imm((unsigned)N->getValue() >> 16);
44 // Transformation function: shift the high 16 bit immediate from a build_vector
45 // node into the low 16 bits, and return a 16-bit constant.
46 def HI16_vec : SDNodeXForm<scalar_to_vector, [{
47 SDOperand OpVal(0, 0);
49 assert(N->getOpcode() == ISD::BUILD_VECTOR
50 && "HI16_vec got something other than a BUILD_VECTOR");
52 // Get first constant operand...
53 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
54 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
56 OpVal = N->getOperand(i);
59 assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
60 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
61 return getI32Imm((unsigned)CN->getValue() >> 16);
64 // simm7 predicate - True if the immediate fits in an 7-bit signed
66 def simm7: PatLeaf<(imm), [{
67 int sextVal = ((((int) N->getValue()) << 25) >> 25);
68 return (sextVal >= -64 && sextVal <= 63);
71 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
73 def uimm7: PatLeaf<(imm), [{
74 return (N->getValue() <= 0x7f);
77 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
79 def immSExt8 : PatLeaf<(imm), [{
80 int Value = (int) N->getValue();
81 int Value8 = (Value << 24) >> 24;
82 return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
85 // immU8: immediate, unsigned 8-bit quantity
86 def immU8 : PatLeaf<(imm), [{
87 return (N->getValue() <= 0xff);
90 // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
91 // extended field. Used by RI10Form instructions like 'ldq'.
92 def i64ImmSExt10 : PatLeaf<(imm), [{
93 return isI64IntS10Immediate(N);
96 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
97 // extended field. Used by RI10Form instructions like 'ldq'.
98 def i32ImmSExt10 : PatLeaf<(imm), [{
99 return isI32IntS10Immediate(N);
102 // i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
103 // field. Used by RI10Form instructions like 'ldq'.
104 def i32ImmUns10 : PatLeaf<(imm), [{
105 return isI32IntU10Immediate(N);
108 // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
109 // extended field. Used by RI10Form instructions like 'ldq'.
110 def i16ImmSExt10 : PatLeaf<(imm), [{
111 return isI16IntS10Immediate(N);
114 // i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
115 // value. Used by RI10Form instructions.
116 def i16ImmUns10 : PatLeaf<(imm), [{
117 return isI16IntU10Immediate(N);
120 def immSExt16 : PatLeaf<(imm), [{
121 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
124 return isIntS16Immediate(N, Ignored);
127 def immZExt16 : PatLeaf<(imm), [{
128 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
130 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
133 def immU16 : PatLeaf<(imm), [{
134 // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
135 return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
138 def imm18 : PatLeaf<(imm), [{
139 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
140 int Value = (int) N->getValue();
141 return ((Value & ((1 << 19) - 1)) == Value);
144 def hi16 : PatLeaf<(imm), [{
145 // hi16 predicate - returns true if the immediate has all zeros in the
146 // low order bits and is a 32-bit constant:
147 if (N->getValueType(0) == MVT::i32) {
148 uint32_t val = N->getValue();
149 return ((val & 0xffff0000) == val);
155 //===----------------------------------------------------------------------===//
156 // Floating point operands:
157 //===----------------------------------------------------------------------===//
159 // Transform a float, returning the high 16 bits shifted down, as if
160 // the float was really an unsigned integer:
161 def HI16_f32 : SDNodeXForm<fpimm, [{
162 float fval = N->getValueAPF().convertToFloat();
163 return getI32Imm(FloatToBits(fval) >> 16);
166 // Transformation function on floats: get the low 16 bits as if the float was
167 // an unsigned integer.
168 def LO16_f32 : SDNodeXForm<fpimm, [{
169 float fval = N->getValueAPF().convertToFloat();
170 return getI32Imm(FloatToBits(fval) & 0xffff);
173 def FPimm_sext16 : SDNodeXForm<fpimm, [{
174 float fval = N->getValueAPF().convertToFloat();
175 return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
178 def FPimm_u18 : SDNodeXForm<fpimm, [{
179 float fval = N->getValueAPF().convertToFloat();
180 return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
183 def fpimmSExt16 : PatLeaf<(fpimm), [{
185 return isFPS16Immediate(N, Ignored);
188 // Does the SFP constant only have upp 16 bits set?
189 def hi16_f32 : PatLeaf<(fpimm), [{
190 if (N->getValueType(0) == MVT::f32) {
191 uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
192 return ((val & 0xffff0000) == val);
198 // Does the SFP constant fit into 18 bits?
199 def fpimm18 : PatLeaf<(fpimm), [{
200 if (N->getValueType(0) == MVT::f32) {
201 uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
202 return ((Value & ((1 << 19) - 1)) == Value);
208 //===----------------------------------------------------------------------===//
209 // 64-bit operands (TODO):
210 //===----------------------------------------------------------------------===//
212 //===----------------------------------------------------------------------===//
213 // build_vector operands:
214 //===----------------------------------------------------------------------===//
216 // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
217 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
218 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
219 def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
220 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
223 // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
224 // load, works in conjunction with its transform function. N.B.: This relies the
225 // incoming constant being a 16-bit quantity, where the upper and lower bytes
226 // are EXACTLY the same (e.g., 0x2a2a)
227 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
228 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
229 }], v16i8SExt8Imm_xform>;
231 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
232 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
233 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
234 def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
235 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
238 // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
239 // load, works in conjunction with its transform function. N.B.: This relies the
240 // incoming constant being a 16-bit quantity, where the upper and lower bytes
241 // are EXACTLY the same (e.g., 0x2a2a)
242 def v16i8U8Imm: PatLeaf<(build_vector), [{
243 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
244 }], v16i8U8Imm_xform>;
246 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
247 // immediate constant load for v8i16 vectors.
248 def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
249 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
252 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
253 // load, works in conjunction with its transform function.
254 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
255 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
256 }], v8i16SExt8Imm_xform>;
258 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
259 // immediate constant load for v8i16 vectors.
260 def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
261 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
264 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
265 // load, works in conjunction with its transform function.
266 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
267 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
268 }], v8i16SExt10Imm_xform>;
270 // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
271 // immediate constant load for v8i16 vectors.
272 def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
273 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
276 // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
277 // load, works in conjunction with its transform function.
278 def v8i16Uns10Imm: PatLeaf<(build_vector), [{
279 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
280 }], v8i16Uns10Imm_xform>;
282 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
283 // immediate constant load for v8i16 vectors.
284 def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
285 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
288 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
289 // load, works in conjunction with its transform function.
290 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
291 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
292 }], v8i16Uns16Imm_xform>;
294 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
295 // immediate constant load for v4i32 vectors.
296 def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
297 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
300 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
301 // load, works in conjunction with its transform function.
302 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
303 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
304 }], v4i32SExt10Imm_xform>;
306 // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
307 // immediate constant load for v4i32 vectors.
308 def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
309 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
312 // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
313 // load, works in conjunction with its transform function.
314 def v4i32Uns10Imm: PatLeaf<(build_vector), [{
315 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
316 }], v4i32Uns10Imm_xform>;
318 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
319 // immediate constant load for v4i32 vectors.
320 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
321 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
324 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
325 // load, works in conjunction with its transform function.
326 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
327 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
328 }], v4i32SExt16Imm_xform>;
330 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
331 // immediate constant load for v4i32 vectors.
332 def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
333 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
336 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
337 // works in conjunction with its transform function.
338 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
339 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
340 }], v4i32Uns18Imm_xform>;
342 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
344 def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
345 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
348 /// immILHUvec: Predicate test for a ILHU constant vector.
349 def immILHUvec: PatLeaf<(build_vector), [{
350 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
351 }], ILHUvec_get_imm>;
353 // Catch-all for any other i32 vector constants
354 def v4i32_get_imm: SDNodeXForm<build_vector, [{
355 return SPU::get_v4i32_imm(N, *CurDAG);
358 def v4i32Imm: PatLeaf<(build_vector), [{
359 return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
362 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
363 // immediate constant load for v2i64 vectors.
364 def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
365 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
368 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
369 // load, works in conjunction with its transform function.
370 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
371 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
372 }], v2i64SExt10Imm_xform>;
374 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
375 // immediate constant load for v2i64 vectors.
376 def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
377 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
380 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
381 // load, works in conjunction with its transform function.
382 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
383 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
384 }], v2i64SExt16Imm_xform>;
386 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
387 // immediate constant load for v2i64 vectors.
388 def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
389 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
392 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
393 // works in conjunction with its transform function.
394 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
395 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
396 }], v2i64Uns18Imm_xform>;
398 /// immILHUvec: Predicate test for a ILHU constant vector.
399 def immILHUvec_i64: PatLeaf<(build_vector), [{
400 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
401 }], ILHUvec_get_imm>;
403 // Catch-all for any other i32 vector constants
404 def v2i64_get_imm: SDNodeXForm<build_vector, [{
405 return SPU::get_v2i64_imm(N, *CurDAG);
408 def v2i64Imm: PatLeaf<(build_vector), [{
409 return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
412 //===----------------------------------------------------------------------===//
413 // Operand Definitions.
415 def s7imm: Operand<i16> {
416 let PrintMethod = "printS7ImmOperand";
419 def u7imm: Operand<i16> {
420 let PrintMethod = "printU7ImmOperand";
423 def u7imm_i8: Operand<i8> {
424 let PrintMethod = "printU7ImmOperand";
427 def u7imm_i32: Operand<i32> {
428 let PrintMethod = "printU7ImmOperand";
431 // Halfword, signed 10-bit constant
432 def s10imm : Operand<i16> {
433 let PrintMethod = "printS10ImmOperand";
436 def s10imm_i32: Operand<i32> {
437 let PrintMethod = "printS10ImmOperand";
440 def s10imm_i64: Operand<i64> {
441 let PrintMethod = "printS10ImmOperand";
444 // Unsigned 10-bit integers:
445 def u10imm: Operand<i16> {
446 let PrintMethod = "printU10ImmOperand";
449 def u10imm_i8: Operand<i8> {
450 let PrintMethod = "printU10ImmOperand";
453 def u10imm_i32: Operand<i32> {
454 let PrintMethod = "printU10ImmOperand";
457 def s16imm : Operand<i16> {
458 let PrintMethod = "printS16ImmOperand";
461 def s16imm_i8: Operand<i8> {
462 let PrintMethod = "printS16ImmOperand";
465 def s16imm_i32: Operand<i32> {
466 let PrintMethod = "printS16ImmOperand";
469 def s16imm_i64: Operand<i64> {
470 let PrintMethod = "printS16ImmOperand";
473 def s16imm_f32: Operand<f32> {
474 let PrintMethod = "printS16ImmOperand";
477 def s16imm_f64: Operand<f64> {
478 let PrintMethod = "printS16ImmOperand";
481 def u16imm : Operand<i32> {
482 let PrintMethod = "printU16ImmOperand";
485 def f16imm : Operand<f32> {
486 let PrintMethod = "printU16ImmOperand";
489 def s18imm : Operand<i32> {
490 let PrintMethod = "printS18ImmOperand";
493 def u18imm : Operand<i32> {
494 let PrintMethod = "printU18ImmOperand";
497 def u18imm_i64 : Operand<i64> {
498 let PrintMethod = "printU18ImmOperand";
501 def f18imm : Operand<f32> {
502 let PrintMethod = "printU18ImmOperand";
505 def f18imm_f64 : Operand<f64> {
506 let PrintMethod = "printU18ImmOperand";
509 // Negated 7-bit halfword rotate immediate operands
510 def rothNeg7imm : Operand<i32> {
511 let PrintMethod = "printROTHNeg7Imm";
514 def rothNeg7imm_i16 : Operand<i16> {
515 let PrintMethod = "printROTHNeg7Imm";
518 // Negated 7-bit word rotate immediate operands
519 def rotNeg7imm : Operand<i32> {
520 let PrintMethod = "printROTNeg7Imm";
523 def rotNeg7imm_i16 : Operand<i16> {
524 let PrintMethod = "printROTNeg7Imm";
527 // Floating point immediate operands
528 def f32imm : Operand<f32>;
530 def target : Operand<OtherVT> {
531 let PrintMethod = "printBranchOperand";
534 // Absolute address call target
535 def calltarget : Operand<iPTR> {
536 let PrintMethod = "printCallOperand";
537 let MIOperandInfo = (ops u18imm:$calldest);
540 // Relative call target
541 def relcalltarget : Operand<iPTR> {
542 let PrintMethod = "printPCRelativeOperand";
543 let MIOperandInfo = (ops s16imm:$calldest);
547 def brtarget : Operand<OtherVT> {
548 let PrintMethod = "printPCRelativeOperand";
551 // Indirect call target
552 def indcalltarget : Operand<iPTR> {
553 let PrintMethod = "printCallOperand";
554 let MIOperandInfo = (ops ptr_rc:$calldest);
557 def symbolHi: Operand<i32> {
558 let PrintMethod = "printSymbolHi";
561 def symbolLo: Operand<i32> {
562 let PrintMethod = "printSymbolLo";
565 def symbolLSA: Operand<i32> {
566 let PrintMethod = "printSymbolLSA";
569 // memory s7imm(reg) operaand
570 def memri7 : Operand<iPTR> {
571 let PrintMethod = "printMemRegImmS7";
572 let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
575 // memory s10imm(reg) operand
576 def memri10 : Operand<iPTR> {
577 let PrintMethod = "printMemRegImmS10";
578 let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
581 // 256K local store address
582 // N.B.: The tblgen code generator expects to have two operands, an offset
583 // and a pointer. Of these, only the immediate is actually used.
584 def addr256k : Operand<iPTR> {
585 let PrintMethod = "printAddr256K";
586 let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
589 // memory s18imm(reg) operand
590 def memri18 : Operand<iPTR> {
591 let PrintMethod = "printMemRegImmS18";
592 let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
595 // memory register + register operand
596 def memrr : Operand<iPTR> {
597 let PrintMethod = "printMemRegReg";
598 let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
601 // Define SPU-specific addressing modes: These come in three basic
604 // D-form : [r+I10] (10-bit signed offset + reg)
605 // X-form : [r+r] (reg+reg)
606 // A-form : abs (256K LSA offset)
607 // D-form(2): [r+I7] (7-bit signed offset + reg)
609 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>;
610 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>;
611 def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>;
612 def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>;