1 //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instruction Operands:
10 //===----------------------------------------------------------------------===//
12 def LO16 : SDNodeXForm<imm, [{
13 unsigned val = N->getValue();
14 // Transformation function: get the low 16 bits.
15 return getI32Imm(val & 0xffff);
18 def LO16_vec : SDNodeXForm<scalar_to_vector, [{
19 SDOperand OpVal(0, 0);
21 // Transformation function: get the low 16 bit immediate from a build_vector
23 assert(N->getOpcode() == ISD::BUILD_VECTOR
24 && "LO16_vec got something other than a BUILD_VECTOR");
26 // Get first constant operand...
27 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
28 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
30 OpVal = N->getOperand(i);
33 assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
34 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
35 return getI32Imm((unsigned)CN->getValue() & 0xffff);
38 // Transform an immediate, returning the high 16 bits shifted down:
39 def HI16 : SDNodeXForm<imm, [{
40 return getI32Imm((unsigned)N->getValue() >> 16);
43 // Transformation function: shift the high 16 bit immediate from a build_vector
44 // node into the low 16 bits, and return a 16-bit constant.
45 def HI16_vec : SDNodeXForm<scalar_to_vector, [{
46 SDOperand OpVal(0, 0);
48 assert(N->getOpcode() == ISD::BUILD_VECTOR
49 && "HI16_vec got something other than a BUILD_VECTOR");
51 // Get first constant operand...
52 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
53 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
55 OpVal = N->getOperand(i);
58 assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
59 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
60 return getI32Imm((unsigned)CN->getValue() >> 16);
63 // simm7 predicate - True if the immediate fits in an 7-bit signed
65 def simm7: PatLeaf<(imm), [{
66 int sextVal = int(N->getSignExtended());
67 return (sextVal >= -64 && sextVal <= 63);
70 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
72 def uimm7: PatLeaf<(imm), [{
73 return (N->getValue() <= 0x7f);
76 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
78 def immSExt8 : PatLeaf<(imm), [{
79 int Value = (int) N->getValue();
80 int Value8 = (Value << 24) >> 24;
81 return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
84 // immU8: immediate, unsigned 8-bit quantity
85 def immU8 : PatLeaf<(imm), [{
86 return (N->getValue() <= 0xff);
89 // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
90 // extended field. Used by RI10Form instructions like 'ldq'.
91 def i64ImmSExt10 : PatLeaf<(imm), [{
92 return isI64IntS10Immediate(N);
95 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
96 // extended field. Used by RI10Form instructions like 'ldq'.
97 def i32ImmSExt10 : PatLeaf<(imm), [{
98 return isI32IntS10Immediate(N);
101 // i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
102 // field. Used by RI10Form instructions like 'ldq'.
103 def i32ImmUns10 : PatLeaf<(imm), [{
104 return isI32IntU10Immediate(N);
107 // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
108 // extended field. Used by RI10Form instructions like 'ldq'.
109 def i16ImmSExt10 : PatLeaf<(imm), [{
110 return isI16IntS10Immediate(N);
113 // i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
114 // value. Used by RI10Form instructions.
115 def i16ImmUns10 : PatLeaf<(imm), [{
116 return isI16IntU10Immediate(N);
119 def immSExt16 : PatLeaf<(imm), [{
120 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
123 return isIntS16Immediate(N, Ignored);
126 def immZExt16 : PatLeaf<(imm), [{
127 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
129 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
132 def immU16 : PatLeaf<(imm), [{
133 // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
134 return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
137 def imm18 : PatLeaf<(imm), [{
138 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
139 int Value = (int) N->getValue();
140 return ((Value & ((1 << 19) - 1)) == Value);
143 def lo16 : PatLeaf<(imm), [{
144 // lo16 predicate - returns true if the immediate has all zeros in the
145 // low order bits and is a 32-bit constant:
146 if (N->getValueType(0) == MVT::i32) {
147 uint32_t val = N->getValue();
148 return ((val & 0x0000ffff) == val);
154 def hi16 : PatLeaf<(imm), [{
155 // hi16 predicate - returns true if the immediate has all zeros in the
156 // low order bits and is a 32-bit constant:
157 if (N->getValueType(0) == MVT::i32) {
158 uint32_t val = uint32_t(N->getValue());
159 return ((val & 0xffff0000) == val);
160 } else if (N->getValueType(0) == MVT::i64) {
161 uint64_t val = N->getValue();
162 return ((val & 0xffff0000ULL) == val);
168 def bitshift : PatLeaf<(imm), [{
169 // bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
170 // (shift left quadword by bits immediate)
171 int64_t Val = N->getValue();
172 return (Val > 0 && Val <= 7);
175 //===----------------------------------------------------------------------===//
176 // Floating point operands:
177 //===----------------------------------------------------------------------===//
179 // Transform a float, returning the high 16 bits shifted down, as if
180 // the float was really an unsigned integer:
181 def HI16_f32 : SDNodeXForm<fpimm, [{
182 float fval = N->getValueAPF().convertToFloat();
183 return getI32Imm(FloatToBits(fval) >> 16);
186 // Transformation function on floats: get the low 16 bits as if the float was
187 // an unsigned integer.
188 def LO16_f32 : SDNodeXForm<fpimm, [{
189 float fval = N->getValueAPF().convertToFloat();
190 return getI32Imm(FloatToBits(fval) & 0xffff);
193 def FPimm_sext16 : SDNodeXForm<fpimm, [{
194 float fval = N->getValueAPF().convertToFloat();
195 return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
198 def FPimm_u18 : SDNodeXForm<fpimm, [{
199 float fval = N->getValueAPF().convertToFloat();
200 return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
203 def fpimmSExt16 : PatLeaf<(fpimm), [{
205 return isFPS16Immediate(N, Ignored);
208 // Does the SFP constant only have upp 16 bits set?
209 def hi16_f32 : PatLeaf<(fpimm), [{
210 if (N->getValueType(0) == MVT::f32) {
211 uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
212 return ((val & 0xffff0000) == val);
218 // Does the SFP constant fit into 18 bits?
219 def fpimm18 : PatLeaf<(fpimm), [{
220 if (N->getValueType(0) == MVT::f32) {
221 uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
222 return ((Value & ((1 << 19) - 1)) == Value);
228 //===----------------------------------------------------------------------===//
229 // 64-bit operands (TODO):
230 //===----------------------------------------------------------------------===//
232 //===----------------------------------------------------------------------===//
233 // build_vector operands:
234 //===----------------------------------------------------------------------===//
236 // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
237 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
238 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
239 def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
240 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
243 // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
244 // load, works in conjunction with its transform function. N.B.: This relies the
245 // incoming constant being a 16-bit quantity, where the upper and lower bytes
246 // are EXACTLY the same (e.g., 0x2a2a)
247 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
248 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
249 }], v16i8SExt8Imm_xform>;
251 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
252 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
253 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
254 def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
255 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
258 // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
259 // load, works in conjunction with its transform function. N.B.: This relies the
260 // incoming constant being a 16-bit quantity, where the upper and lower bytes
261 // are EXACTLY the same (e.g., 0x2a2a)
262 def v16i8U8Imm: PatLeaf<(build_vector), [{
263 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
264 }], v16i8U8Imm_xform>;
266 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
267 // immediate constant load for v8i16 vectors.
268 def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
269 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
272 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
273 // load, works in conjunction with its transform function.
274 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
275 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
276 }], v8i16SExt8Imm_xform>;
278 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
279 // immediate constant load for v8i16 vectors.
280 def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
281 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
284 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
285 // load, works in conjunction with its transform function.
286 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
287 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
288 }], v8i16SExt10Imm_xform>;
290 // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
291 // immediate constant load for v8i16 vectors.
292 def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
293 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
296 // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
297 // load, works in conjunction with its transform function.
298 def v8i16Uns10Imm: PatLeaf<(build_vector), [{
299 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
300 }], v8i16Uns10Imm_xform>;
302 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
303 // immediate constant load for v8i16 vectors.
304 def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
305 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
308 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
309 // load, works in conjunction with its transform function.
310 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
311 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
312 }], v8i16Uns16Imm_xform>;
314 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
315 // immediate constant load for v4i32 vectors.
316 def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
317 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
320 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
321 // load, works in conjunction with its transform function.
322 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
323 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
324 }], v4i32SExt10Imm_xform>;
326 // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
327 // immediate constant load for v4i32 vectors.
328 def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
329 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
332 // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
333 // load, works in conjunction with its transform function.
334 def v4i32Uns10Imm: PatLeaf<(build_vector), [{
335 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
336 }], v4i32Uns10Imm_xform>;
338 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
339 // immediate constant load for v4i32 vectors.
340 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
341 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
344 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
345 // load, works in conjunction with its transform function.
346 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
347 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
348 }], v4i32SExt16Imm_xform>;
350 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
351 // immediate constant load for v4i32 vectors.
352 def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
353 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
356 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
357 // works in conjunction with its transform function.
358 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
359 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
360 }], v4i32Uns18Imm_xform>;
362 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
364 def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
365 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
368 /// immILHUvec: Predicate test for a ILHU constant vector.
369 def immILHUvec: PatLeaf<(build_vector), [{
370 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
371 }], ILHUvec_get_imm>;
373 // Catch-all for any other i32 vector constants
374 def v4i32_get_imm: SDNodeXForm<build_vector, [{
375 return SPU::get_v4i32_imm(N, *CurDAG);
378 def v4i32Imm: PatLeaf<(build_vector), [{
379 return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
382 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
383 // immediate constant load for v2i64 vectors.
384 def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
385 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
388 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
389 // load, works in conjunction with its transform function.
390 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
391 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
392 }], v2i64SExt10Imm_xform>;
394 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
395 // immediate constant load for v2i64 vectors.
396 def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
397 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
400 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
401 // load, works in conjunction with its transform function.
402 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
403 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
404 }], v2i64SExt16Imm_xform>;
406 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
407 // immediate constant load for v2i64 vectors.
408 def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
409 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
412 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
413 // works in conjunction with its transform function.
414 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
415 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
416 }], v2i64Uns18Imm_xform>;
418 /// immILHUvec: Predicate test for a ILHU constant vector.
419 def immILHUvec_i64: PatLeaf<(build_vector), [{
420 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
421 }], ILHUvec_get_imm>;
423 // Catch-all for any other i32 vector constants
424 def v2i64_get_imm: SDNodeXForm<build_vector, [{
425 return SPU::get_v2i64_imm(N, *CurDAG);
428 def v2i64Imm: PatLeaf<(build_vector), [{
429 return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
432 //===----------------------------------------------------------------------===//
433 // Operand Definitions.
435 def s7imm: Operand<i8> {
436 let PrintMethod = "printS7ImmOperand";
439 def s7imm_i8: Operand<i8> {
440 let PrintMethod = "printS7ImmOperand";
443 def u7imm: Operand<i16> {
444 let PrintMethod = "printU7ImmOperand";
447 def u7imm_i8: Operand<i8> {
448 let PrintMethod = "printU7ImmOperand";
451 def u7imm_i32: Operand<i32> {
452 let PrintMethod = "printU7ImmOperand";
455 // Halfword, signed 10-bit constant
456 def s10imm : Operand<i16> {
457 let PrintMethod = "printS10ImmOperand";
460 def s10imm_i8: Operand<i8> {
461 let PrintMethod = "printS10ImmOperand";
464 def s10imm_i32: Operand<i32> {
465 let PrintMethod = "printS10ImmOperand";
468 def s10imm_i64: Operand<i64> {
469 let PrintMethod = "printS10ImmOperand";
472 // Unsigned 10-bit integers:
473 def u10imm: Operand<i16> {
474 let PrintMethod = "printU10ImmOperand";
477 def u10imm_i8: Operand<i8> {
478 let PrintMethod = "printU10ImmOperand";
481 def u10imm_i32: Operand<i32> {
482 let PrintMethod = "printU10ImmOperand";
485 def s16imm : Operand<i16> {
486 let PrintMethod = "printS16ImmOperand";
489 def s16imm_i8: Operand<i8> {
490 let PrintMethod = "printS16ImmOperand";
493 def s16imm_i32: Operand<i32> {
494 let PrintMethod = "printS16ImmOperand";
497 def s16imm_i64: Operand<i64> {
498 let PrintMethod = "printS16ImmOperand";
501 def s16imm_f32: Operand<f32> {
502 let PrintMethod = "printS16ImmOperand";
505 def s16imm_f64: Operand<f64> {
506 let PrintMethod = "printS16ImmOperand";
509 def u16imm_i64 : Operand<i64> {
510 let PrintMethod = "printU16ImmOperand";
513 def u16imm : Operand<i32> {
514 let PrintMethod = "printU16ImmOperand";
517 def f16imm : Operand<f32> {
518 let PrintMethod = "printU16ImmOperand";
521 def s18imm : Operand<i32> {
522 let PrintMethod = "printS18ImmOperand";
525 def u18imm : Operand<i32> {
526 let PrintMethod = "printU18ImmOperand";
529 def u18imm_i64 : Operand<i64> {
530 let PrintMethod = "printU18ImmOperand";
533 def f18imm : Operand<f32> {
534 let PrintMethod = "printU18ImmOperand";
537 def f18imm_f64 : Operand<f64> {
538 let PrintMethod = "printU18ImmOperand";
541 // Negated 7-bit halfword rotate immediate operands
542 def rothNeg7imm : Operand<i32> {
543 let PrintMethod = "printROTHNeg7Imm";
546 def rothNeg7imm_i16 : Operand<i16> {
547 let PrintMethod = "printROTHNeg7Imm";
550 // Negated 7-bit word rotate immediate operands
551 def rotNeg7imm : Operand<i32> {
552 let PrintMethod = "printROTNeg7Imm";
555 def rotNeg7imm_i16 : Operand<i16> {
556 let PrintMethod = "printROTNeg7Imm";
559 def target : Operand<OtherVT> {
560 let PrintMethod = "printBranchOperand";
563 // Absolute address call target
564 def calltarget : Operand<iPTR> {
565 let PrintMethod = "printCallOperand";
566 let MIOperandInfo = (ops u18imm:$calldest);
569 // Relative call target
570 def relcalltarget : Operand<iPTR> {
571 let PrintMethod = "printPCRelativeOperand";
572 let MIOperandInfo = (ops s16imm:$calldest);
576 def brtarget : Operand<OtherVT> {
577 let PrintMethod = "printPCRelativeOperand";
580 // Indirect call target
581 def indcalltarget : Operand<iPTR> {
582 let PrintMethod = "printCallOperand";
583 let MIOperandInfo = (ops ptr_rc:$calldest);
586 def symbolHi: Operand<i32> {
587 let PrintMethod = "printSymbolHi";
590 def symbolLo: Operand<i32> {
591 let PrintMethod = "printSymbolLo";
594 def symbolLSA: Operand<i32> {
595 let PrintMethod = "printSymbolLSA";
598 // memory s7imm(reg) operaand
599 def memri7 : Operand<iPTR> {
600 let PrintMethod = "printMemRegImmS7";
601 let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
604 // memory s10imm(reg) operand
605 def memri10 : Operand<iPTR> {
606 let PrintMethod = "printMemRegImmS10";
607 let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
610 // 256K local store address
611 // N.B.: The tblgen code generator expects to have two operands, an offset
612 // and a pointer. Of these, only the immediate is actually used.
613 def addr256k : Operand<iPTR> {
614 let PrintMethod = "printAddr256K";
615 let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
618 // memory s18imm(reg) operand
619 def memri18 : Operand<iPTR> {
620 let PrintMethod = "printMemRegImmS18";
621 let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
624 // memory register + register operand
625 def memrr : Operand<iPTR> {
626 let PrintMethod = "printMemRegReg";
627 let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
630 // Define SPU-specific addressing modes: These come in three basic
633 // D-form : [r+I10] (10-bit signed offset + reg)
634 // X-form : [r+r] (reg+reg)
635 // A-form : abs (256K LSA offset)
636 // D-form(2): [r+I7] (7-bit signed offset + reg)
638 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>;
639 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>;
640 def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>;
641 def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>;