1 //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instruction Operands:
10 //===----------------------------------------------------------------------===//
12 def LO16 : SDNodeXForm<imm, [{
13 unsigned val = N->getValue();
14 // Transformation function: get the low 16 bits.
15 return getI32Imm(val & 0xffff);
18 def LO16_vec : SDNodeXForm<scalar_to_vector, [{
19 SDOperand OpVal(0, 0);
21 // Transformation function: get the low 16 bit immediate from a build_vector
23 assert(N->getOpcode() == ISD::BUILD_VECTOR
24 && "LO16_vec got something other than a BUILD_VECTOR");
26 // Get first constant operand...
27 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
28 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
30 OpVal = N->getOperand(i);
33 assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
34 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
35 return getI32Imm((unsigned)CN->getValue() & 0xffff);
38 // Transform an immediate, returning the high 16 bits shifted down:
39 def HI16 : SDNodeXForm<imm, [{
40 return getI32Imm((unsigned)N->getValue() >> 16);
43 // Transformation function: shift the high 16 bit immediate from a build_vector
44 // node into the low 16 bits, and return a 16-bit constant.
45 def HI16_vec : SDNodeXForm<scalar_to_vector, [{
46 SDOperand OpVal(0, 0);
48 assert(N->getOpcode() == ISD::BUILD_VECTOR
49 && "HI16_vec got something other than a BUILD_VECTOR");
51 // Get first constant operand...
52 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
53 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
55 OpVal = N->getOperand(i);
58 assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
59 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
60 return getI32Imm((unsigned)CN->getValue() >> 16);
63 // simm7 predicate - True if the immediate fits in an 7-bit signed
65 def simm7: PatLeaf<(imm), [{
66 int sextVal = ((((int) N->getValue()) << 25) >> 25);
67 return (sextVal >= -64 && sextVal <= 63);
70 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
72 def uimm7: PatLeaf<(imm), [{
73 return (N->getValue() <= 0x7f);
76 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
78 def immSExt8 : PatLeaf<(imm), [{
79 int Value = (int) N->getValue();
80 int Value8 = (Value << 24) >> 24;
81 return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
84 // immU8: immediate, unsigned 8-bit quantity
85 def immU8 : PatLeaf<(imm), [{
86 return (N->getValue() <= 0xff);
89 // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
90 // extended field. Used by RI10Form instructions like 'ldq'.
91 def i64ImmSExt10 : PatLeaf<(imm), [{
92 return isI64IntS10Immediate(N);
95 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
96 // extended field. Used by RI10Form instructions like 'ldq'.
97 def i32ImmSExt10 : PatLeaf<(imm), [{
98 return isI32IntS10Immediate(N);
101 // i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
102 // field. Used by RI10Form instructions like 'ldq'.
103 def i32ImmUns10 : PatLeaf<(imm), [{
104 return isI32IntU10Immediate(N);
107 // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
108 // extended field. Used by RI10Form instructions like 'ldq'.
109 def i16ImmSExt10 : PatLeaf<(imm), [{
110 return isI16IntS10Immediate(N);
113 // i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
114 // value. Used by RI10Form instructions.
115 def i16ImmUns10 : PatLeaf<(imm), [{
116 return isI16IntU10Immediate(N);
119 def immSExt16 : PatLeaf<(imm), [{
120 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
123 return isIntS16Immediate(N, Ignored);
126 def immZExt16 : PatLeaf<(imm), [{
127 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
129 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
132 def immU16 : PatLeaf<(imm), [{
133 // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
134 return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
137 def imm18 : PatLeaf<(imm), [{
138 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
139 int Value = (int) N->getValue();
140 return ((Value & ((1 << 19) - 1)) == Value);
143 def lo16 : PatLeaf<(imm), [{
144 // hi16 predicate - returns true if the immediate has all zeros in the
145 // low order bits and is a 32-bit constant:
146 if (N->getValueType(0) == MVT::i32) {
147 uint32_t val = N->getValue();
148 return ((val & 0x0000ffff) == val);
154 def hi16 : PatLeaf<(imm), [{
155 // hi16 predicate - returns true if the immediate has all zeros in the
156 // low order bits and is a 32-bit constant:
157 if (N->getValueType(0) == MVT::i32) {
158 uint32_t val = N->getValue();
159 return ((val & 0xffff0000) == val);
165 //===----------------------------------------------------------------------===//
166 // Floating point operands:
167 //===----------------------------------------------------------------------===//
169 // Transform a float, returning the high 16 bits shifted down, as if
170 // the float was really an unsigned integer:
171 def HI16_f32 : SDNodeXForm<fpimm, [{
172 float fval = N->getValueAPF().convertToFloat();
173 return getI32Imm(FloatToBits(fval) >> 16);
176 // Transformation function on floats: get the low 16 bits as if the float was
177 // an unsigned integer.
178 def LO16_f32 : SDNodeXForm<fpimm, [{
179 float fval = N->getValueAPF().convertToFloat();
180 return getI32Imm(FloatToBits(fval) & 0xffff);
183 def FPimm_sext16 : SDNodeXForm<fpimm, [{
184 float fval = N->getValueAPF().convertToFloat();
185 return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
188 def FPimm_u18 : SDNodeXForm<fpimm, [{
189 float fval = N->getValueAPF().convertToFloat();
190 return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
193 def fpimmSExt16 : PatLeaf<(fpimm), [{
195 return isFPS16Immediate(N, Ignored);
198 // Does the SFP constant only have upp 16 bits set?
199 def hi16_f32 : PatLeaf<(fpimm), [{
200 if (N->getValueType(0) == MVT::f32) {
201 uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
202 return ((val & 0xffff0000) == val);
208 // Does the SFP constant fit into 18 bits?
209 def fpimm18 : PatLeaf<(fpimm), [{
210 if (N->getValueType(0) == MVT::f32) {
211 uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
212 return ((Value & ((1 << 19) - 1)) == Value);
218 //===----------------------------------------------------------------------===//
219 // 64-bit operands (TODO):
220 //===----------------------------------------------------------------------===//
222 //===----------------------------------------------------------------------===//
223 // build_vector operands:
224 //===----------------------------------------------------------------------===//
226 // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
227 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
228 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
229 def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
230 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
233 // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
234 // load, works in conjunction with its transform function. N.B.: This relies the
235 // incoming constant being a 16-bit quantity, where the upper and lower bytes
236 // are EXACTLY the same (e.g., 0x2a2a)
237 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
238 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
239 }], v16i8SExt8Imm_xform>;
241 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
242 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
243 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
244 def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
245 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
248 // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
249 // load, works in conjunction with its transform function. N.B.: This relies the
250 // incoming constant being a 16-bit quantity, where the upper and lower bytes
251 // are EXACTLY the same (e.g., 0x2a2a)
252 def v16i8U8Imm: PatLeaf<(build_vector), [{
253 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
254 }], v16i8U8Imm_xform>;
256 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
257 // immediate constant load for v8i16 vectors.
258 def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
259 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
262 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
263 // load, works in conjunction with its transform function.
264 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
265 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
266 }], v8i16SExt8Imm_xform>;
268 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
269 // immediate constant load for v8i16 vectors.
270 def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
271 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
274 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
275 // load, works in conjunction with its transform function.
276 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
277 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
278 }], v8i16SExt10Imm_xform>;
280 // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
281 // immediate constant load for v8i16 vectors.
282 def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
283 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
286 // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
287 // load, works in conjunction with its transform function.
288 def v8i16Uns10Imm: PatLeaf<(build_vector), [{
289 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
290 }], v8i16Uns10Imm_xform>;
292 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
293 // immediate constant load for v8i16 vectors.
294 def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
295 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
298 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
299 // load, works in conjunction with its transform function.
300 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
301 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
302 }], v8i16Uns16Imm_xform>;
304 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
305 // immediate constant load for v4i32 vectors.
306 def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
307 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
310 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
311 // load, works in conjunction with its transform function.
312 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
313 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
314 }], v4i32SExt10Imm_xform>;
316 // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
317 // immediate constant load for v4i32 vectors.
318 def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
319 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
322 // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
323 // load, works in conjunction with its transform function.
324 def v4i32Uns10Imm: PatLeaf<(build_vector), [{
325 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
326 }], v4i32Uns10Imm_xform>;
328 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
329 // immediate constant load for v4i32 vectors.
330 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
331 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
334 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
335 // load, works in conjunction with its transform function.
336 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
337 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
338 }], v4i32SExt16Imm_xform>;
340 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
341 // immediate constant load for v4i32 vectors.
342 def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
343 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
346 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
347 // works in conjunction with its transform function.
348 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
349 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
350 }], v4i32Uns18Imm_xform>;
352 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
354 def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
355 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
358 /// immILHUvec: Predicate test for a ILHU constant vector.
359 def immILHUvec: PatLeaf<(build_vector), [{
360 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
361 }], ILHUvec_get_imm>;
363 // Catch-all for any other i32 vector constants
364 def v4i32_get_imm: SDNodeXForm<build_vector, [{
365 return SPU::get_v4i32_imm(N, *CurDAG);
368 def v4i32Imm: PatLeaf<(build_vector), [{
369 return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
372 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
373 // immediate constant load for v2i64 vectors.
374 def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
375 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
378 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
379 // load, works in conjunction with its transform function.
380 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
381 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
382 }], v2i64SExt10Imm_xform>;
384 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
385 // immediate constant load for v2i64 vectors.
386 def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
387 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
390 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
391 // load, works in conjunction with its transform function.
392 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
393 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
394 }], v2i64SExt16Imm_xform>;
396 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
397 // immediate constant load for v2i64 vectors.
398 def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
399 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
402 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
403 // works in conjunction with its transform function.
404 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
405 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
406 }], v2i64Uns18Imm_xform>;
408 /// immILHUvec: Predicate test for a ILHU constant vector.
409 def immILHUvec_i64: PatLeaf<(build_vector), [{
410 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
411 }], ILHUvec_get_imm>;
413 // Catch-all for any other i32 vector constants
414 def v2i64_get_imm: SDNodeXForm<build_vector, [{
415 return SPU::get_v2i64_imm(N, *CurDAG);
418 def v2i64Imm: PatLeaf<(build_vector), [{
419 return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
422 //===----------------------------------------------------------------------===//
423 // Operand Definitions.
425 def s7imm: Operand<i8> {
426 let PrintMethod = "printS7ImmOperand";
429 def s7imm_i8: Operand<i8> {
430 let PrintMethod = "printS7ImmOperand";
433 def u7imm: Operand<i16> {
434 let PrintMethod = "printU7ImmOperand";
437 def u7imm_i8: Operand<i8> {
438 let PrintMethod = "printU7ImmOperand";
441 def u7imm_i32: Operand<i32> {
442 let PrintMethod = "printU7ImmOperand";
445 // Halfword, signed 10-bit constant
446 def s10imm : Operand<i16> {
447 let PrintMethod = "printS10ImmOperand";
450 def s10imm_i32: Operand<i32> {
451 let PrintMethod = "printS10ImmOperand";
454 def s10imm_i64: Operand<i64> {
455 let PrintMethod = "printS10ImmOperand";
458 // Unsigned 10-bit integers:
459 def u10imm: Operand<i16> {
460 let PrintMethod = "printU10ImmOperand";
463 def u10imm_i8: Operand<i8> {
464 let PrintMethod = "printU10ImmOperand";
467 def u10imm_i32: Operand<i32> {
468 let PrintMethod = "printU10ImmOperand";
471 def s16imm : Operand<i16> {
472 let PrintMethod = "printS16ImmOperand";
475 def s16imm_i8: Operand<i8> {
476 let PrintMethod = "printS16ImmOperand";
479 def s16imm_i32: Operand<i32> {
480 let PrintMethod = "printS16ImmOperand";
483 def s16imm_i64: Operand<i64> {
484 let PrintMethod = "printS16ImmOperand";
487 def s16imm_f32: Operand<f32> {
488 let PrintMethod = "printS16ImmOperand";
491 def s16imm_f64: Operand<f64> {
492 let PrintMethod = "printS16ImmOperand";
495 def u16imm : Operand<i32> {
496 let PrintMethod = "printU16ImmOperand";
499 def f16imm : Operand<f32> {
500 let PrintMethod = "printU16ImmOperand";
503 def s18imm : Operand<i32> {
504 let PrintMethod = "printS18ImmOperand";
507 def u18imm : Operand<i32> {
508 let PrintMethod = "printU18ImmOperand";
511 def u18imm_i64 : Operand<i64> {
512 let PrintMethod = "printU18ImmOperand";
515 def f18imm : Operand<f32> {
516 let PrintMethod = "printU18ImmOperand";
519 def f18imm_f64 : Operand<f64> {
520 let PrintMethod = "printU18ImmOperand";
523 // Negated 7-bit halfword rotate immediate operands
524 def rothNeg7imm : Operand<i32> {
525 let PrintMethod = "printROTHNeg7Imm";
528 def rothNeg7imm_i16 : Operand<i16> {
529 let PrintMethod = "printROTHNeg7Imm";
532 // Negated 7-bit word rotate immediate operands
533 def rotNeg7imm : Operand<i32> {
534 let PrintMethod = "printROTNeg7Imm";
537 def rotNeg7imm_i16 : Operand<i16> {
538 let PrintMethod = "printROTNeg7Imm";
541 // Floating point immediate operands
542 def f32imm : Operand<f32>;
544 def target : Operand<OtherVT> {
545 let PrintMethod = "printBranchOperand";
548 // Absolute address call target
549 def calltarget : Operand<iPTR> {
550 let PrintMethod = "printCallOperand";
551 let MIOperandInfo = (ops u18imm:$calldest);
554 // Relative call target
555 def relcalltarget : Operand<iPTR> {
556 let PrintMethod = "printPCRelativeOperand";
557 let MIOperandInfo = (ops s16imm:$calldest);
561 def brtarget : Operand<OtherVT> {
562 let PrintMethod = "printPCRelativeOperand";
565 // Indirect call target
566 def indcalltarget : Operand<iPTR> {
567 let PrintMethod = "printCallOperand";
568 let MIOperandInfo = (ops ptr_rc:$calldest);
571 def symbolHi: Operand<i32> {
572 let PrintMethod = "printSymbolHi";
575 def symbolLo: Operand<i32> {
576 let PrintMethod = "printSymbolLo";
579 def symbolLSA: Operand<i32> {
580 let PrintMethod = "printSymbolLSA";
583 // memory s7imm(reg) operaand
584 def memri7 : Operand<iPTR> {
585 let PrintMethod = "printMemRegImmS7";
586 let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
589 // memory s10imm(reg) operand
590 def memri10 : Operand<iPTR> {
591 let PrintMethod = "printMemRegImmS10";
592 let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
595 // 256K local store address
596 // N.B.: The tblgen code generator expects to have two operands, an offset
597 // and a pointer. Of these, only the immediate is actually used.
598 def addr256k : Operand<iPTR> {
599 let PrintMethod = "printAddr256K";
600 let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
603 // memory s18imm(reg) operand
604 def memri18 : Operand<iPTR> {
605 let PrintMethod = "printMemRegImmS18";
606 let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
609 // memory register + register operand
610 def memrr : Operand<iPTR> {
611 let PrintMethod = "printMemRegReg";
612 let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
615 // Define SPU-specific addressing modes: These come in three basic
618 // D-form : [r+I10] (10-bit signed offset + reg)
619 // X-form : [r+r] (reg+reg)
620 // A-form : abs (256K LSA offset)
621 // D-form(2): [r+I7] (7-bit signed offset + reg)
623 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>;
624 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>;
625 def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>;
626 def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>;