1 //===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // Cell SPU Instruction Operands:
10 //===----------------------------------------------------------------------===//
12 def LO16 : SDNodeXForm<imm, [{
13 unsigned val = N->getValue();
14 // Transformation function: get the low 16 bits.
15 return getI32Imm(val & 0xffff);
18 def LO16_vec : SDNodeXForm<scalar_to_vector, [{
19 SDOperand OpVal(0, 0);
21 // Transformation function: get the low 16 bit immediate from a build_vector
23 assert(N->getOpcode() == ISD::BUILD_VECTOR
24 && "LO16_vec got something other than a BUILD_VECTOR");
26 // Get first constant operand...
27 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
28 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
30 OpVal = N->getOperand(i);
33 assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
34 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
35 return getI32Imm((unsigned)CN->getValue() & 0xffff);
38 // Transform an immediate, returning the high 16 bits shifted down:
39 def HI16 : SDNodeXForm<imm, [{
40 return getI32Imm((unsigned)N->getValue() >> 16);
43 // Transformation function: shift the high 16 bit immediate from a build_vector
44 // node into the low 16 bits, and return a 16-bit constant.
45 def HI16_vec : SDNodeXForm<scalar_to_vector, [{
46 SDOperand OpVal(0, 0);
48 assert(N->getOpcode() == ISD::BUILD_VECTOR
49 && "HI16_vec got something other than a BUILD_VECTOR");
51 // Get first constant operand...
52 for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
53 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
55 OpVal = N->getOperand(i);
58 assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
59 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal);
60 return getI32Imm((unsigned)CN->getValue() >> 16);
63 // simm7 predicate - True if the immediate fits in an 7-bit signed
65 def simm7: PatLeaf<(imm), [{
66 int sextVal = int(N->getSignExtended());
67 return (sextVal >= -64 && sextVal <= 63);
70 // uimm7 predicate - True if the immediate fits in an 7-bit unsigned
72 def uimm7: PatLeaf<(imm), [{
73 return (N->getValue() <= 0x7f);
76 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
78 def immSExt8 : PatLeaf<(imm), [{
79 int Value = (int) N->getValue();
80 int Value8 = (Value << 24) >> 24;
81 return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
84 // immU8: immediate, unsigned 8-bit quantity
85 def immU8 : PatLeaf<(imm), [{
86 return (N->getValue() <= 0xff);
89 // i64ImmSExt10 predicate - True if the i64 immediate fits in a 10-bit sign
90 // extended field. Used by RI10Form instructions like 'ldq'.
91 def i64ImmSExt10 : PatLeaf<(imm), [{
92 return isI64IntS10Immediate(N);
95 // i32ImmSExt10 predicate - True if the i32 immediate fits in a 10-bit sign
96 // extended field. Used by RI10Form instructions like 'ldq'.
97 def i32ImmSExt10 : PatLeaf<(imm), [{
98 return isI32IntS10Immediate(N);
101 // i32ImmUns10 predicate - True if the i32 immediate fits in a 10-bit unsigned
102 // field. Used by RI10Form instructions like 'ldq'.
103 def i32ImmUns10 : PatLeaf<(imm), [{
104 return isI32IntU10Immediate(N);
107 // i16ImmSExt10 predicate - True if the i16 immediate fits in a 10-bit sign
108 // extended field. Used by RI10Form instructions like 'ldq'.
109 def i16ImmSExt10 : PatLeaf<(imm), [{
110 return isI16IntS10Immediate(N);
113 // i16ImmUns10 predicate - True if the i16 immediate fits into a 10-bit unsigned
114 // value. Used by RI10Form instructions.
115 def i16ImmUns10 : PatLeaf<(imm), [{
116 return isI16IntU10Immediate(N);
119 def immSExt16 : PatLeaf<(imm), [{
120 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
123 return isIntS16Immediate(N, Ignored);
126 def immZExt16 : PatLeaf<(imm), [{
127 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
129 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
132 def immU16 : PatLeaf<(imm), [{
133 // immU16 predicate- True if the immediate fits into a 16-bit unsigned field.
134 return (uint64_t)N->getValue() == (N->getValue() & 0xffff);
137 def imm18 : PatLeaf<(imm), [{
138 // imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
139 int Value = (int) N->getValue();
140 return ((Value & ((1 << 19) - 1)) == Value);
143 def lo16 : PatLeaf<(imm), [{
144 // hi16 predicate - returns true if the immediate has all zeros in the
145 // low order bits and is a 32-bit constant:
146 if (N->getValueType(0) == MVT::i32) {
147 uint32_t val = N->getValue();
148 return ((val & 0x0000ffff) == val);
154 def hi16 : PatLeaf<(imm), [{
155 // hi16 predicate - returns true if the immediate has all zeros in the
156 // low order bits and is a 32-bit constant:
157 if (N->getValueType(0) == MVT::i32) {
158 uint32_t val = N->getValue();
159 return ((val & 0xffff0000) == val);
165 def bitshift : PatLeaf<(imm), [{
166 // bitshift predicate - returns true if 0 < imm <= 7 for SHLQBII
167 // (shift left quadword by bits immediate)
168 int64_t Val = N->getValue();
169 return (Val > 0 && Val <= 7);
172 //===----------------------------------------------------------------------===//
173 // Floating point operands:
174 //===----------------------------------------------------------------------===//
176 // Transform a float, returning the high 16 bits shifted down, as if
177 // the float was really an unsigned integer:
178 def HI16_f32 : SDNodeXForm<fpimm, [{
179 float fval = N->getValueAPF().convertToFloat();
180 return getI32Imm(FloatToBits(fval) >> 16);
183 // Transformation function on floats: get the low 16 bits as if the float was
184 // an unsigned integer.
185 def LO16_f32 : SDNodeXForm<fpimm, [{
186 float fval = N->getValueAPF().convertToFloat();
187 return getI32Imm(FloatToBits(fval) & 0xffff);
190 def FPimm_sext16 : SDNodeXForm<fpimm, [{
191 float fval = N->getValueAPF().convertToFloat();
192 return getI32Imm((int) ((FloatToBits(fval) << 16) >> 16));
195 def FPimm_u18 : SDNodeXForm<fpimm, [{
196 float fval = N->getValueAPF().convertToFloat();
197 return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
200 def fpimmSExt16 : PatLeaf<(fpimm), [{
202 return isFPS16Immediate(N, Ignored);
205 // Does the SFP constant only have upp 16 bits set?
206 def hi16_f32 : PatLeaf<(fpimm), [{
207 if (N->getValueType(0) == MVT::f32) {
208 uint32_t val = FloatToBits(N->getValueAPF().convertToFloat());
209 return ((val & 0xffff0000) == val);
215 // Does the SFP constant fit into 18 bits?
216 def fpimm18 : PatLeaf<(fpimm), [{
217 if (N->getValueType(0) == MVT::f32) {
218 uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
219 return ((Value & ((1 << 19) - 1)) == Value);
225 //===----------------------------------------------------------------------===//
226 // 64-bit operands (TODO):
227 //===----------------------------------------------------------------------===//
229 //===----------------------------------------------------------------------===//
230 // build_vector operands:
231 //===----------------------------------------------------------------------===//
233 // v16i8SExt8Imm_xform function: convert build_vector to 8-bit sign extended
234 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
235 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
236 def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
237 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
240 // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant
241 // load, works in conjunction with its transform function. N.B.: This relies the
242 // incoming constant being a 16-bit quantity, where the upper and lower bytes
243 // are EXACTLY the same (e.g., 0x2a2a)
244 def v16i8SExt8Imm: PatLeaf<(build_vector), [{
245 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
246 }], v16i8SExt8Imm_xform>;
248 // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
249 // immediate constant load for v16i8 vectors. N.B.: The incoming constant has
250 // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a).
251 def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
252 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8);
255 // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant
256 // load, works in conjunction with its transform function. N.B.: This relies the
257 // incoming constant being a 16-bit quantity, where the upper and lower bytes
258 // are EXACTLY the same (e.g., 0x2a2a)
259 def v16i8U8Imm: PatLeaf<(build_vector), [{
260 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
261 }], v16i8U8Imm_xform>;
263 // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
264 // immediate constant load for v8i16 vectors.
265 def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
266 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16);
269 // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
270 // load, works in conjunction with its transform function.
271 def v8i16SExt8Imm: PatLeaf<(build_vector), [{
272 return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
273 }], v8i16SExt8Imm_xform>;
275 // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
276 // immediate constant load for v8i16 vectors.
277 def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
278 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
281 // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
282 // load, works in conjunction with its transform function.
283 def v8i16SExt10Imm: PatLeaf<(build_vector), [{
284 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
285 }], v8i16SExt10Imm_xform>;
287 // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
288 // immediate constant load for v8i16 vectors.
289 def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
290 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16);
293 // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
294 // load, works in conjunction with its transform function.
295 def v8i16Uns10Imm: PatLeaf<(build_vector), [{
296 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
297 }], v8i16Uns10Imm_xform>;
299 // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
300 // immediate constant load for v8i16 vectors.
301 def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
302 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16);
305 // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
306 // load, works in conjunction with its transform function.
307 def v8i16SExt16Imm: PatLeaf<(build_vector), [{
308 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
309 }], v8i16Uns16Imm_xform>;
311 // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
312 // immediate constant load for v4i32 vectors.
313 def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
314 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
317 // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
318 // load, works in conjunction with its transform function.
319 def v4i32SExt10Imm: PatLeaf<(build_vector), [{
320 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
321 }], v4i32SExt10Imm_xform>;
323 // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
324 // immediate constant load for v4i32 vectors.
325 def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
326 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32);
329 // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
330 // load, works in conjunction with its transform function.
331 def v4i32Uns10Imm: PatLeaf<(build_vector), [{
332 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
333 }], v4i32Uns10Imm_xform>;
335 // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
336 // immediate constant load for v4i32 vectors.
337 def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
338 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32);
341 // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
342 // load, works in conjunction with its transform function.
343 def v4i32SExt16Imm: PatLeaf<(build_vector), [{
344 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
345 }], v4i32SExt16Imm_xform>;
347 // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned
348 // immediate constant load for v4i32 vectors.
349 def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{
350 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32);
353 // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
354 // works in conjunction with its transform function.
355 def v4i32Uns18Imm: PatLeaf<(build_vector), [{
356 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).Val != 0;
357 }], v4i32Uns18Imm_xform>;
359 // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant
361 def ILHUvec_get_imm: SDNodeXForm<build_vector, [{
362 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32);
365 /// immILHUvec: Predicate test for a ILHU constant vector.
366 def immILHUvec: PatLeaf<(build_vector), [{
367 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).Val != 0;
368 }], ILHUvec_get_imm>;
370 // Catch-all for any other i32 vector constants
371 def v4i32_get_imm: SDNodeXForm<build_vector, [{
372 return SPU::get_v4i32_imm(N, *CurDAG);
375 def v4i32Imm: PatLeaf<(build_vector), [{
376 return SPU::get_v4i32_imm(N, *CurDAG).Val != 0;
379 // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended
380 // immediate constant load for v2i64 vectors.
381 def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{
382 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64);
385 // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant
386 // load, works in conjunction with its transform function.
387 def v2i64SExt10Imm: PatLeaf<(build_vector), [{
388 return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).Val != 0;
389 }], v2i64SExt10Imm_xform>;
391 // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended
392 // immediate constant load for v2i64 vectors.
393 def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{
394 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64);
397 // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant
398 // load, works in conjunction with its transform function.
399 def v2i64SExt16Imm: PatLeaf<(build_vector), [{
400 return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).Val != 0;
401 }], v2i64SExt16Imm_xform>;
403 // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned
404 // immediate constant load for v2i64 vectors.
405 def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{
406 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64);
409 // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load,
410 // works in conjunction with its transform function.
411 def v2i64Uns18Imm: PatLeaf<(build_vector), [{
412 return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).Val != 0;
413 }], v2i64Uns18Imm_xform>;
415 /// immILHUvec: Predicate test for a ILHU constant vector.
416 def immILHUvec_i64: PatLeaf<(build_vector), [{
417 return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).Val != 0;
418 }], ILHUvec_get_imm>;
420 // Catch-all for any other i32 vector constants
421 def v2i64_get_imm: SDNodeXForm<build_vector, [{
422 return SPU::get_v2i64_imm(N, *CurDAG);
425 def v2i64Imm: PatLeaf<(build_vector), [{
426 return SPU::get_v2i64_imm(N, *CurDAG).Val != 0;
429 //===----------------------------------------------------------------------===//
430 // Operand Definitions.
432 def s7imm: Operand<i8> {
433 let PrintMethod = "printS7ImmOperand";
436 def s7imm_i8: Operand<i8> {
437 let PrintMethod = "printS7ImmOperand";
440 def u7imm: Operand<i16> {
441 let PrintMethod = "printU7ImmOperand";
444 def u7imm_i8: Operand<i8> {
445 let PrintMethod = "printU7ImmOperand";
448 def u7imm_i32: Operand<i32> {
449 let PrintMethod = "printU7ImmOperand";
452 // Halfword, signed 10-bit constant
453 def s10imm : Operand<i16> {
454 let PrintMethod = "printS10ImmOperand";
457 def s10imm_i8: Operand<i8> {
458 let PrintMethod = "printS10ImmOperand";
461 def s10imm_i32: Operand<i32> {
462 let PrintMethod = "printS10ImmOperand";
465 def s10imm_i64: Operand<i64> {
466 let PrintMethod = "printS10ImmOperand";
469 // Unsigned 10-bit integers:
470 def u10imm: Operand<i16> {
471 let PrintMethod = "printU10ImmOperand";
474 def u10imm_i8: Operand<i8> {
475 let PrintMethod = "printU10ImmOperand";
478 def u10imm_i32: Operand<i32> {
479 let PrintMethod = "printU10ImmOperand";
482 def s16imm : Operand<i16> {
483 let PrintMethod = "printS16ImmOperand";
486 def s16imm_i8: Operand<i8> {
487 let PrintMethod = "printS16ImmOperand";
490 def s16imm_i32: Operand<i32> {
491 let PrintMethod = "printS16ImmOperand";
494 def s16imm_i64: Operand<i64> {
495 let PrintMethod = "printS16ImmOperand";
498 def s16imm_f32: Operand<f32> {
499 let PrintMethod = "printS16ImmOperand";
502 def s16imm_f64: Operand<f64> {
503 let PrintMethod = "printS16ImmOperand";
506 def u16imm : Operand<i32> {
507 let PrintMethod = "printU16ImmOperand";
510 def f16imm : Operand<f32> {
511 let PrintMethod = "printU16ImmOperand";
514 def s18imm : Operand<i32> {
515 let PrintMethod = "printS18ImmOperand";
518 def u18imm : Operand<i32> {
519 let PrintMethod = "printU18ImmOperand";
522 def u18imm_i64 : Operand<i64> {
523 let PrintMethod = "printU18ImmOperand";
526 def f18imm : Operand<f32> {
527 let PrintMethod = "printU18ImmOperand";
530 def f18imm_f64 : Operand<f64> {
531 let PrintMethod = "printU18ImmOperand";
534 // Negated 7-bit halfword rotate immediate operands
535 def rothNeg7imm : Operand<i32> {
536 let PrintMethod = "printROTHNeg7Imm";
539 def rothNeg7imm_i16 : Operand<i16> {
540 let PrintMethod = "printROTHNeg7Imm";
543 // Negated 7-bit word rotate immediate operands
544 def rotNeg7imm : Operand<i32> {
545 let PrintMethod = "printROTNeg7Imm";
548 def rotNeg7imm_i16 : Operand<i16> {
549 let PrintMethod = "printROTNeg7Imm";
552 def target : Operand<OtherVT> {
553 let PrintMethod = "printBranchOperand";
556 // Absolute address call target
557 def calltarget : Operand<iPTR> {
558 let PrintMethod = "printCallOperand";
559 let MIOperandInfo = (ops u18imm:$calldest);
562 // Relative call target
563 def relcalltarget : Operand<iPTR> {
564 let PrintMethod = "printPCRelativeOperand";
565 let MIOperandInfo = (ops s16imm:$calldest);
569 def brtarget : Operand<OtherVT> {
570 let PrintMethod = "printPCRelativeOperand";
573 // Indirect call target
574 def indcalltarget : Operand<iPTR> {
575 let PrintMethod = "printCallOperand";
576 let MIOperandInfo = (ops ptr_rc:$calldest);
579 def symbolHi: Operand<i32> {
580 let PrintMethod = "printSymbolHi";
583 def symbolLo: Operand<i32> {
584 let PrintMethod = "printSymbolLo";
587 def symbolLSA: Operand<i32> {
588 let PrintMethod = "printSymbolLSA";
591 // memory s7imm(reg) operaand
592 def memri7 : Operand<iPTR> {
593 let PrintMethod = "printMemRegImmS7";
594 let MIOperandInfo = (ops s7imm:$imm, ptr_rc:$reg);
597 // memory s10imm(reg) operand
598 def memri10 : Operand<iPTR> {
599 let PrintMethod = "printMemRegImmS10";
600 let MIOperandInfo = (ops s10imm:$imm, ptr_rc:$reg);
603 // 256K local store address
604 // N.B.: The tblgen code generator expects to have two operands, an offset
605 // and a pointer. Of these, only the immediate is actually used.
606 def addr256k : Operand<iPTR> {
607 let PrintMethod = "printAddr256K";
608 let MIOperandInfo = (ops s16imm:$imm, ptr_rc:$reg);
611 // memory s18imm(reg) operand
612 def memri18 : Operand<iPTR> {
613 let PrintMethod = "printMemRegImmS18";
614 let MIOperandInfo = (ops s18imm:$imm, ptr_rc:$reg);
617 // memory register + register operand
618 def memrr : Operand<iPTR> {
619 let PrintMethod = "printMemRegReg";
620 let MIOperandInfo = (ops ptr_rc:$reg_a, ptr_rc:$reg_b);
623 // Define SPU-specific addressing modes: These come in three basic
626 // D-form : [r+I10] (10-bit signed offset + reg)
627 // X-form : [r+r] (reg+reg)
628 // A-form : abs (256K LSA offset)
629 // D-form(2): [r+I7] (7-bit signed offset + reg)
631 def dform_addr : ComplexPattern<iPTR, 2, "SelectDFormAddr", [], []>;
632 def xform_addr : ComplexPattern<iPTR, 2, "SelectXFormAddr", [], []>;
633 def aform_addr : ComplexPattern<iPTR, 2, "SelectAFormAddr", [], []>;
634 def dform2_addr : ComplexPattern<iPTR, 2, "SelectDForm2Addr", [], []>;