1 //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "SPURegisterInfo.h"
17 #include "SPURegisterNames.h"
18 #include "SPUInstrBuilder.h"
19 #include "SPUSubtarget.h"
20 #include "SPUMachineFunction.h"
21 #include "SPUFrameInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/ValueTypes.h"
32 #include "llvm/Target/TargetFrameInfo.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/ADT/BitVector.h"
40 #include "llvm/ADT/STLExtras.h"
45 /// getRegisterNumbering - Given the enum value for some register, e.g.
46 /// PPC::F14, return the number that it corresponds to (e.g. 14).
47 unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
50 case SPU::R0: return 0;
51 case SPU::R1: return 1;
52 case SPU::R2: return 2;
53 case SPU::R3: return 3;
54 case SPU::R4: return 4;
55 case SPU::R5: return 5;
56 case SPU::R6: return 6;
57 case SPU::R7: return 7;
58 case SPU::R8: return 8;
59 case SPU::R9: return 9;
60 case SPU::R10: return 10;
61 case SPU::R11: return 11;
62 case SPU::R12: return 12;
63 case SPU::R13: return 13;
64 case SPU::R14: return 14;
65 case SPU::R15: return 15;
66 case SPU::R16: return 16;
67 case SPU::R17: return 17;
68 case SPU::R18: return 18;
69 case SPU::R19: return 19;
70 case SPU::R20: return 20;
71 case SPU::R21: return 21;
72 case SPU::R22: return 22;
73 case SPU::R23: return 23;
74 case SPU::R24: return 24;
75 case SPU::R25: return 25;
76 case SPU::R26: return 26;
77 case SPU::R27: return 27;
78 case SPU::R28: return 28;
79 case SPU::R29: return 29;
80 case SPU::R30: return 30;
81 case SPU::R31: return 31;
82 case SPU::R32: return 32;
83 case SPU::R33: return 33;
84 case SPU::R34: return 34;
85 case SPU::R35: return 35;
86 case SPU::R36: return 36;
87 case SPU::R37: return 37;
88 case SPU::R38: return 38;
89 case SPU::R39: return 39;
90 case SPU::R40: return 40;
91 case SPU::R41: return 41;
92 case SPU::R42: return 42;
93 case SPU::R43: return 43;
94 case SPU::R44: return 44;
95 case SPU::R45: return 45;
96 case SPU::R46: return 46;
97 case SPU::R47: return 47;
98 case SPU::R48: return 48;
99 case SPU::R49: return 49;
100 case SPU::R50: return 50;
101 case SPU::R51: return 51;
102 case SPU::R52: return 52;
103 case SPU::R53: return 53;
104 case SPU::R54: return 54;
105 case SPU::R55: return 55;
106 case SPU::R56: return 56;
107 case SPU::R57: return 57;
108 case SPU::R58: return 58;
109 case SPU::R59: return 59;
110 case SPU::R60: return 60;
111 case SPU::R61: return 61;
112 case SPU::R62: return 62;
113 case SPU::R63: return 63;
114 case SPU::R64: return 64;
115 case SPU::R65: return 65;
116 case SPU::R66: return 66;
117 case SPU::R67: return 67;
118 case SPU::R68: return 68;
119 case SPU::R69: return 69;
120 case SPU::R70: return 70;
121 case SPU::R71: return 71;
122 case SPU::R72: return 72;
123 case SPU::R73: return 73;
124 case SPU::R74: return 74;
125 case SPU::R75: return 75;
126 case SPU::R76: return 76;
127 case SPU::R77: return 77;
128 case SPU::R78: return 78;
129 case SPU::R79: return 79;
130 case SPU::R80: return 80;
131 case SPU::R81: return 81;
132 case SPU::R82: return 82;
133 case SPU::R83: return 83;
134 case SPU::R84: return 84;
135 case SPU::R85: return 85;
136 case SPU::R86: return 86;
137 case SPU::R87: return 87;
138 case SPU::R88: return 88;
139 case SPU::R89: return 89;
140 case SPU::R90: return 90;
141 case SPU::R91: return 91;
142 case SPU::R92: return 92;
143 case SPU::R93: return 93;
144 case SPU::R94: return 94;
145 case SPU::R95: return 95;
146 case SPU::R96: return 96;
147 case SPU::R97: return 97;
148 case SPU::R98: return 98;
149 case SPU::R99: return 99;
150 case SPU::R100: return 100;
151 case SPU::R101: return 101;
152 case SPU::R102: return 102;
153 case SPU::R103: return 103;
154 case SPU::R104: return 104;
155 case SPU::R105: return 105;
156 case SPU::R106: return 106;
157 case SPU::R107: return 107;
158 case SPU::R108: return 108;
159 case SPU::R109: return 109;
160 case SPU::R110: return 110;
161 case SPU::R111: return 111;
162 case SPU::R112: return 112;
163 case SPU::R113: return 113;
164 case SPU::R114: return 114;
165 case SPU::R115: return 115;
166 case SPU::R116: return 116;
167 case SPU::R117: return 117;
168 case SPU::R118: return 118;
169 case SPU::R119: return 119;
170 case SPU::R120: return 120;
171 case SPU::R121: return 121;
172 case SPU::R122: return 122;
173 case SPU::R123: return 123;
174 case SPU::R124: return 124;
175 case SPU::R125: return 125;
176 case SPU::R126: return 126;
177 case SPU::R127: return 127;
179 cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
184 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
185 const TargetInstrInfo &tii) :
186 SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
187 Subtarget(subtarget),
192 // SPU's 128-bit registers used for argument passing:
193 static const unsigned SPU_ArgRegs[] = {
194 SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
195 SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
196 SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
197 SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
198 SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
199 SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
200 SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
201 SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
202 SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
203 SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
204 SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
208 SPURegisterInfo::getArgRegs()
214 SPURegisterInfo::getNumArgRegs()
216 return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
220 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
222 // Cell ABI calling convention
223 static const unsigned SPU_CalleeSaveRegs[] = {
224 SPU::R80, SPU::R81, SPU::R82, SPU::R83,
225 SPU::R84, SPU::R85, SPU::R86, SPU::R87,
226 SPU::R88, SPU::R89, SPU::R90, SPU::R91,
227 SPU::R92, SPU::R93, SPU::R94, SPU::R95,
228 SPU::R96, SPU::R97, SPU::R98, SPU::R99,
229 SPU::R100, SPU::R101, SPU::R102, SPU::R103,
230 SPU::R104, SPU::R105, SPU::R106, SPU::R107,
231 SPU::R108, SPU::R109, SPU::R110, SPU::R111,
232 SPU::R112, SPU::R113, SPU::R114, SPU::R115,
233 SPU::R116, SPU::R117, SPU::R118, SPU::R119,
234 SPU::R120, SPU::R121, SPU::R122, SPU::R123,
235 SPU::R124, SPU::R125, SPU::R126, SPU::R127,
236 SPU::R2, /* environment pointer */
237 SPU::R1, /* stack pointer */
238 SPU::R0, /* link register */
242 return SPU_CalleeSaveRegs;
245 const TargetRegisterClass* const*
246 SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
248 // Cell ABI Calling Convention
249 static const TargetRegisterClass * const SPU_CalleeSaveRegClasses[] = {
250 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
251 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
252 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
253 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
254 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
255 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
256 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
257 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
258 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
259 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
260 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
261 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
262 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
263 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
264 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
265 &SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
266 &SPU::GPRCRegClass, /* environment pointer */
267 &SPU::GPRCRegClass, /* stack pointer */
268 &SPU::GPRCRegClass, /* link register */
272 return SPU_CalleeSaveRegClasses;
276 R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
277 generally unused) are the Cell's reserved registers
279 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
280 BitVector Reserved(getNumRegs());
281 Reserved.set(SPU::R0); // LR
282 Reserved.set(SPU::R1); // SP
283 Reserved.set(SPU::R2); // environment pointer
287 //===----------------------------------------------------------------------===//
288 // Stack Frame Processing methods
289 //===----------------------------------------------------------------------===//
291 // needsFP - Return true if the specified function should have a dedicated frame
292 // pointer register. This is true if the function has variable sized allocas or
293 // if frame pointer elimination is disabled.
295 static bool needsFP(const MachineFunction &MF) {
296 const MachineFrameInfo *MFI = MF.getFrameInfo();
297 return NoFramePointerElim || MFI->hasVarSizedObjects();
300 //--------------------------------------------------------------------------
301 // hasFP - Return true if the specified function actually has a dedicated frame
302 // pointer register. This is true if the function needs a frame pointer and has
303 // a non-zero stack size.
305 SPURegisterInfo::hasFP(const MachineFunction &MF) const {
306 const MachineFrameInfo *MFI = MF.getFrameInfo();
307 return MFI->getStackSize() && needsFP(MF);
310 //--------------------------------------------------------------------------
312 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
313 MachineBasicBlock &MBB,
314 MachineBasicBlock::iterator I)
317 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
322 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
323 RegScavenger *RS) const
326 MachineInstr &MI = *II;
327 MachineBasicBlock &MBB = *MI.getParent();
328 MachineFunction &MF = *MBB.getParent();
329 MachineFrameInfo *MFI = MF.getFrameInfo();
331 while (!MI.getOperand(i).isFI()) {
333 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
336 MachineOperand &SPOp = MI.getOperand(i);
337 int FrameIndex = SPOp.getIndex();
339 // Now add the frame object offset to the offset from r1.
340 int Offset = MFI->getObjectOffset(FrameIndex);
342 // Most instructions, except for generated FrameIndex additions using AIr32,
343 // have the immediate in operand 1. AIr32, in this case, has the immediate
345 unsigned OpNo = (MI.getOpcode() != SPU::AIr32 ? 1 : 2);
346 MachineOperand &MO = MI.getOperand(OpNo);
348 // Offset is biased by $lr's slot at the bottom.
349 Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
350 assert((Offset & 0xf) == 0
351 && "16-byte alignment violated in eliminateFrameIndex");
353 // Replace the FrameIndex with base register with $sp (aka $r1)
354 SPOp.ChangeToRegister(SPU::R1, false);
355 if (Offset > SPUFrameInfo::maxFrameOffset()
356 || Offset < SPUFrameInfo::minFrameOffset()) {
357 cerr << "Large stack adjustment ("
359 << ") in SPURegisterInfo::eliminateFrameIndex.";
361 MO.ChangeToImmediate(Offset);
365 /// determineFrameLayout - Determine the size of the frame and maximum call
368 SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
370 MachineFrameInfo *MFI = MF.getFrameInfo();
372 // Get the number of bytes to allocate from the FrameInfo
373 unsigned FrameSize = MFI->getStackSize();
375 // Get the alignments provided by the target, and the maximum alignment
376 // (if any) of the fixed frame objects.
377 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
378 unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
379 assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
380 unsigned AlignMask = Align - 1;
382 // Get the maximum call frame size of all the calls.
383 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
385 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
386 // that allocations will be aligned.
387 if (MFI->hasVarSizedObjects())
388 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
390 // Update maximum call frame size.
391 MFI->setMaxCallFrameSize(maxCallFrameSize);
393 // Include call frame size in total.
394 FrameSize += maxCallFrameSize;
396 // Make sure the frame is aligned.
397 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
399 // Update frame info.
400 MFI->setStackSize(FrameSize);
403 void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
407 // Save and clear the LR state.
408 SPUFunctionInfo *FI = MF.getInfo<SPUFunctionInfo>();
409 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
411 // Mark LR and SP unused, since the prolog spills them to stack and
412 // we don't want anyone else to spill them for us.
414 // Also, unless R2 is really used someday, don't spill it automatically.
415 MF.getRegInfo().setPhysRegUnused(SPU::R0);
416 MF.getRegInfo().setPhysRegUnused(SPU::R1);
417 MF.getRegInfo().setPhysRegUnused(SPU::R2);
420 void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
422 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
423 MachineBasicBlock::iterator MBBI = MBB.begin();
424 MachineFrameInfo *MFI = MF.getFrameInfo();
425 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
427 // Prepare for debug frame info.
428 bool hasDebugInfo = MMI && MMI->hasDebugInfo();
429 unsigned FrameLabelId = 0;
431 // Move MBBI back to the beginning of the function.
434 // Work out frame sizes.
435 determineFrameLayout(MF);
436 int FrameSize = MFI->getStackSize();
438 assert((FrameSize & 0xf) == 0
439 && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
442 FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
444 // Mark effective beginning of when frame pointer becomes valid.
445 FrameLabelId = MMI->NextLabelID();
446 BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId);
449 // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
451 BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
453 if (isS10Constant(FrameSize)) {
454 // Spill $sp to adjusted $sp
455 BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
457 // Adjust $sp by required amout
458 BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
460 } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
461 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
462 // $r2 to adjust $sp:
463 BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
466 BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
468 BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
471 BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
474 BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2)
477 BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
481 cerr << "Unhandled frame size: " << FrameSize << "\n";
486 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
488 // Show update of SP.
489 MachineLocation SPDst(MachineLocation::VirtualFP);
490 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
491 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
493 // Add callee saved registers to move list.
494 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
495 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
496 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
497 unsigned Reg = CSI[I].getReg();
498 if (Reg == SPU::R0) continue;
499 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
500 MachineLocation CSSrc(Reg);
501 Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
504 // Mark effective beginning of when frame pointer is ready.
505 unsigned ReadyLabelId = MMI->NextLabelID();
506 BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId);
508 MachineLocation FPDst(SPU::R1);
509 MachineLocation FPSrc(MachineLocation::VirtualFP);
510 Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
513 // This is a leaf function -- insert a branch hint iff there are
514 // sufficient number instructions in the basic block. Note that
515 // this is just a best guess based on the basic block's size.
516 if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
517 MachineBasicBlock::iterator MBBI = prior(MBB.end());
518 // Insert terminator label
519 unsigned BranchLabelId = MMI->NextLabelID();
520 BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId);
526 SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
528 MachineBasicBlock::iterator MBBI = prior(MBB.end());
529 const MachineFrameInfo *MFI = MF.getFrameInfo();
530 int FrameSize = MFI->getStackSize();
531 int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
533 assert(MBBI->getOpcode() == SPU::RET &&
534 "Can only insert epilog into returning blocks");
535 assert((FrameSize & 0xf) == 0
536 && "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
538 FrameSize = FrameSize + SPUFrameInfo::minStackSize();
539 if (isS10Constant(FrameSize + LinkSlotOffset)) {
540 // Reload $lr, adjust $sp by required amount
541 // Note: We do this to slightly improve dual issue -- not by much, but it
542 // is an opportunity for dual issue.
543 BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
544 .addImm(FrameSize + LinkSlotOffset)
546 BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
549 } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
550 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
551 // $r2 to adjust $sp:
552 BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
555 BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
557 BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
560 BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
563 BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2).
566 BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
570 cerr << "Unhandled frame size: " << FrameSize << "\n";
577 SPURegisterInfo::getRARegister() const
583 SPURegisterInfo::getFrameRegister(MachineFunction &MF) const
589 SPURegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const
591 // Initial state of the frame pointer is R1.
592 MachineLocation Dst(MachineLocation::VirtualFP);
593 MachineLocation Src(SPU::R1, 0);
594 Moves.push_back(MachineMove(0, Dst, Src));
599 SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
600 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
601 return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
604 #include "SPUGenRegisterInfo.inc"