1 //===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "reginfo"
16 #include "SPURegisterInfo.h"
17 #include "SPURegisterNames.h"
18 #include "SPUInstrBuilder.h"
19 #include "SPUSubtarget.h"
20 #include "SPUMachineFunction.h"
21 #include "SPUFrameInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Type.h"
24 #include "llvm/CodeGen/ValueTypes.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineLocation.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/RegisterScavenging.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/Target/TargetFrameInfo.h"
34 #include "llvm/Target/TargetInstrInfo.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/Debug.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/STLExtras.h"
48 /// getRegisterNumbering - Given the enum value for some register, e.g.
49 /// PPC::F14, return the number that it corresponds to (e.g. 14).
50 unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
53 case SPU::R0: return 0;
54 case SPU::R1: return 1;
55 case SPU::R2: return 2;
56 case SPU::R3: return 3;
57 case SPU::R4: return 4;
58 case SPU::R5: return 5;
59 case SPU::R6: return 6;
60 case SPU::R7: return 7;
61 case SPU::R8: return 8;
62 case SPU::R9: return 9;
63 case SPU::R10: return 10;
64 case SPU::R11: return 11;
65 case SPU::R12: return 12;
66 case SPU::R13: return 13;
67 case SPU::R14: return 14;
68 case SPU::R15: return 15;
69 case SPU::R16: return 16;
70 case SPU::R17: return 17;
71 case SPU::R18: return 18;
72 case SPU::R19: return 19;
73 case SPU::R20: return 20;
74 case SPU::R21: return 21;
75 case SPU::R22: return 22;
76 case SPU::R23: return 23;
77 case SPU::R24: return 24;
78 case SPU::R25: return 25;
79 case SPU::R26: return 26;
80 case SPU::R27: return 27;
81 case SPU::R28: return 28;
82 case SPU::R29: return 29;
83 case SPU::R30: return 30;
84 case SPU::R31: return 31;
85 case SPU::R32: return 32;
86 case SPU::R33: return 33;
87 case SPU::R34: return 34;
88 case SPU::R35: return 35;
89 case SPU::R36: return 36;
90 case SPU::R37: return 37;
91 case SPU::R38: return 38;
92 case SPU::R39: return 39;
93 case SPU::R40: return 40;
94 case SPU::R41: return 41;
95 case SPU::R42: return 42;
96 case SPU::R43: return 43;
97 case SPU::R44: return 44;
98 case SPU::R45: return 45;
99 case SPU::R46: return 46;
100 case SPU::R47: return 47;
101 case SPU::R48: return 48;
102 case SPU::R49: return 49;
103 case SPU::R50: return 50;
104 case SPU::R51: return 51;
105 case SPU::R52: return 52;
106 case SPU::R53: return 53;
107 case SPU::R54: return 54;
108 case SPU::R55: return 55;
109 case SPU::R56: return 56;
110 case SPU::R57: return 57;
111 case SPU::R58: return 58;
112 case SPU::R59: return 59;
113 case SPU::R60: return 60;
114 case SPU::R61: return 61;
115 case SPU::R62: return 62;
116 case SPU::R63: return 63;
117 case SPU::R64: return 64;
118 case SPU::R65: return 65;
119 case SPU::R66: return 66;
120 case SPU::R67: return 67;
121 case SPU::R68: return 68;
122 case SPU::R69: return 69;
123 case SPU::R70: return 70;
124 case SPU::R71: return 71;
125 case SPU::R72: return 72;
126 case SPU::R73: return 73;
127 case SPU::R74: return 74;
128 case SPU::R75: return 75;
129 case SPU::R76: return 76;
130 case SPU::R77: return 77;
131 case SPU::R78: return 78;
132 case SPU::R79: return 79;
133 case SPU::R80: return 80;
134 case SPU::R81: return 81;
135 case SPU::R82: return 82;
136 case SPU::R83: return 83;
137 case SPU::R84: return 84;
138 case SPU::R85: return 85;
139 case SPU::R86: return 86;
140 case SPU::R87: return 87;
141 case SPU::R88: return 88;
142 case SPU::R89: return 89;
143 case SPU::R90: return 90;
144 case SPU::R91: return 91;
145 case SPU::R92: return 92;
146 case SPU::R93: return 93;
147 case SPU::R94: return 94;
148 case SPU::R95: return 95;
149 case SPU::R96: return 96;
150 case SPU::R97: return 97;
151 case SPU::R98: return 98;
152 case SPU::R99: return 99;
153 case SPU::R100: return 100;
154 case SPU::R101: return 101;
155 case SPU::R102: return 102;
156 case SPU::R103: return 103;
157 case SPU::R104: return 104;
158 case SPU::R105: return 105;
159 case SPU::R106: return 106;
160 case SPU::R107: return 107;
161 case SPU::R108: return 108;
162 case SPU::R109: return 109;
163 case SPU::R110: return 110;
164 case SPU::R111: return 111;
165 case SPU::R112: return 112;
166 case SPU::R113: return 113;
167 case SPU::R114: return 114;
168 case SPU::R115: return 115;
169 case SPU::R116: return 116;
170 case SPU::R117: return 117;
171 case SPU::R118: return 118;
172 case SPU::R119: return 119;
173 case SPU::R120: return 120;
174 case SPU::R121: return 121;
175 case SPU::R122: return 122;
176 case SPU::R123: return 123;
177 case SPU::R124: return 124;
178 case SPU::R125: return 125;
179 case SPU::R126: return 126;
180 case SPU::R127: return 127;
182 report_fatal_error("Unhandled reg in SPURegisterInfo::getRegisterNumbering");
186 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
187 const TargetInstrInfo &tii) :
188 SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
189 Subtarget(subtarget),
194 /// getPointerRegClass - Return the register class to use to hold pointers.
195 /// This is used for addressing modes.
196 const TargetRegisterClass *
197 SPURegisterInfo::getPointerRegClass(unsigned Kind) const {
198 return &SPU::R32CRegClass;
202 SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
204 // Cell ABI calling convention
205 static const unsigned SPU_CalleeSaveRegs[] = {
206 SPU::R80, SPU::R81, SPU::R82, SPU::R83,
207 SPU::R84, SPU::R85, SPU::R86, SPU::R87,
208 SPU::R88, SPU::R89, SPU::R90, SPU::R91,
209 SPU::R92, SPU::R93, SPU::R94, SPU::R95,
210 SPU::R96, SPU::R97, SPU::R98, SPU::R99,
211 SPU::R100, SPU::R101, SPU::R102, SPU::R103,
212 SPU::R104, SPU::R105, SPU::R106, SPU::R107,
213 SPU::R108, SPU::R109, SPU::R110, SPU::R111,
214 SPU::R112, SPU::R113, SPU::R114, SPU::R115,
215 SPU::R116, SPU::R117, SPU::R118, SPU::R119,
216 SPU::R120, SPU::R121, SPU::R122, SPU::R123,
217 SPU::R124, SPU::R125, SPU::R126, SPU::R127,
218 SPU::R2, /* environment pointer */
219 SPU::R1, /* stack pointer */
220 SPU::R0, /* link register */
224 return SPU_CalleeSaveRegs;
228 R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
229 generally unused) are the Cell's reserved registers
231 BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
232 BitVector Reserved(getNumRegs());
233 Reserved.set(SPU::R0); // LR
234 Reserved.set(SPU::R1); // SP
235 Reserved.set(SPU::R2); // environment pointer
239 //===----------------------------------------------------------------------===//
240 // Stack Frame Processing methods
241 //===----------------------------------------------------------------------===//
243 // needsFP - Return true if the specified function should have a dedicated frame
244 // pointer register. This is true if the function has variable sized allocas or
245 // if frame pointer elimination is disabled.
247 static bool needsFP(const MachineFunction &MF) {
248 const MachineFrameInfo *MFI = MF.getFrameInfo();
249 return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects();
252 //--------------------------------------------------------------------------
253 // hasFP - Return true if the specified function actually has a dedicated frame
254 // pointer register. This is true if the function needs a frame pointer and has
255 // a non-zero stack size.
257 SPURegisterInfo::hasFP(const MachineFunction &MF) const {
258 const MachineFrameInfo *MFI = MF.getFrameInfo();
259 return MFI->getStackSize() && needsFP(MF);
262 //--------------------------------------------------------------------------
264 SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
265 MachineBasicBlock &MBB,
266 MachineBasicBlock::iterator I)
269 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
274 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
275 FrameIndexValue *Value,
276 RegScavenger *RS) const
279 MachineInstr &MI = *II;
280 MachineBasicBlock &MBB = *MI.getParent();
281 MachineFunction &MF = *MBB.getParent();
282 MachineFrameInfo *MFI = MF.getFrameInfo();
283 DebugLoc dl = II->getDebugLoc();
285 while (!MI.getOperand(i).isFI()) {
287 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
290 MachineOperand &SPOp = MI.getOperand(i);
291 int FrameIndex = SPOp.getIndex();
293 // Now add the frame object offset to the offset from r1.
294 int Offset = MFI->getObjectOffset(FrameIndex);
296 // Most instructions, except for generated FrameIndex additions using AIr32
297 // and ILAr32, have the immediate in operand 1. AIr32 and ILAr32 have the
298 // immediate in operand 2.
300 if (MI.getOpcode() == SPU::AIr32 || MI.getOpcode() == SPU::ILAr32)
303 MachineOperand &MO = MI.getOperand(OpNo);
305 // Offset is biased by $lr's slot at the bottom.
306 Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
307 assert((Offset & 0xf) == 0
308 && "16-byte alignment violated in eliminateFrameIndex");
310 // Replace the FrameIndex with base register with $sp (aka $r1)
311 SPOp.ChangeToRegister(SPU::R1, false);
313 // if 'Offset' doesn't fit to the D-form instruction's
314 // immediate, convert the instruction to X-form
315 // if the instruction is not an AI (which takes a s10 immediate), assume
316 // it is a load/store that can take a s14 immediate
317 if ((MI.getOpcode() == SPU::AIr32 && !isInt<10>(Offset))
318 || !isInt<14>(Offset)) {
319 int newOpcode = convertDFormToXForm(MI.getOpcode());
320 unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
321 BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
323 BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
324 .addReg(tmpReg, RegState::Kill)
326 // remove the replaced D-form instruction
329 MO.ChangeToImmediate(Offset);
334 /// determineFrameLayout - Determine the size of the frame and maximum call
337 SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
339 MachineFrameInfo *MFI = MF.getFrameInfo();
341 // Get the number of bytes to allocate from the FrameInfo
342 unsigned FrameSize = MFI->getStackSize();
344 // Get the alignments provided by the target, and the maximum alignment
345 // (if any) of the fixed frame objects.
346 unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
347 unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
348 assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
349 unsigned AlignMask = Align - 1;
351 // Get the maximum call frame size of all the calls.
352 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
354 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
355 // that allocations will be aligned.
356 if (MFI->hasVarSizedObjects())
357 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
359 // Update maximum call frame size.
360 MFI->setMaxCallFrameSize(maxCallFrameSize);
362 // Include call frame size in total.
363 FrameSize += maxCallFrameSize;
365 // Make sure the frame is aligned.
366 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
368 // Update frame info.
369 MFI->setStackSize(FrameSize);
372 void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
375 // Mark LR and SP unused, since the prolog spills them to stack and
376 // we don't want anyone else to spill them for us.
378 // Also, unless R2 is really used someday, don't spill it automatically.
379 MF.getRegInfo().setPhysRegUnused(SPU::R0);
380 MF.getRegInfo().setPhysRegUnused(SPU::R1);
381 MF.getRegInfo().setPhysRegUnused(SPU::R2);
383 MachineFrameInfo *MFI = MF.getFrameInfo();
384 const TargetRegisterClass *RC = &SPU::R32CRegClass;
385 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
392 void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
394 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
395 MachineBasicBlock::iterator MBBI = MBB.begin();
396 MachineFrameInfo *MFI = MF.getFrameInfo();
397 MachineModuleInfo &MMI = MF.getMMI();
398 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
400 // Prepare for debug frame info.
401 bool hasDebugInfo = MMI.hasDebugInfo();
402 MCSymbol *FrameLabel = 0;
404 // Move MBBI back to the beginning of the function.
407 // Work out frame sizes.
408 determineFrameLayout(MF);
409 int FrameSize = MFI->getStackSize();
411 assert((FrameSize & 0xf) == 0
412 && "SPURegisterInfo::emitPrologue: FrameSize not aligned");
414 // the "empty" frame size is 16 - just the register scavenger spill slot
415 if (FrameSize > 16 || MFI->adjustsStack()) {
416 FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
418 // Mark effective beginning of when frame pointer becomes valid.
419 FrameLabel = MMI.getContext().CreateTempSymbol();
420 BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addSym(FrameLabel);
423 // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
425 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
427 if (isInt<10>(FrameSize)) {
428 // Spill $sp to adjusted $sp
429 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
431 // Adjust $sp by required amout
432 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
434 } else if (isInt<16>(FrameSize)) {
435 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
436 // $r2 to adjust $sp:
437 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
440 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
442 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
445 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
448 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2)
451 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
455 report_fatal_error("Unhandled frame size: " + Twine(FrameSize));
459 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
461 // Show update of SP.
462 MachineLocation SPDst(MachineLocation::VirtualFP);
463 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
464 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
466 // Add callee saved registers to move list.
467 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
468 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
469 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
470 unsigned Reg = CSI[I].getReg();
471 if (Reg == SPU::R0) continue;
472 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
473 MachineLocation CSSrc(Reg);
474 Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc));
477 // Mark effective beginning of when frame pointer is ready.
478 MCSymbol *ReadyLabel = MMI.getContext().CreateTempSymbol();
479 BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addSym(ReadyLabel);
481 MachineLocation FPDst(SPU::R1);
482 MachineLocation FPSrc(MachineLocation::VirtualFP);
483 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
486 // This is a leaf function -- insert a branch hint iff there are
487 // sufficient number instructions in the basic block. Note that
488 // this is just a best guess based on the basic block's size.
489 if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
490 MachineBasicBlock::iterator MBBI = prior(MBB.end());
491 dl = MBBI->getDebugLoc();
493 // Insert terminator label
494 BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL))
495 .addSym(MMI.getContext().CreateTempSymbol());
501 SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
503 MachineBasicBlock::iterator MBBI = prior(MBB.end());
504 const MachineFrameInfo *MFI = MF.getFrameInfo();
505 int FrameSize = MFI->getStackSize();
506 int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
507 DebugLoc dl = MBBI->getDebugLoc();
509 assert(MBBI->getOpcode() == SPU::RET &&
510 "Can only insert epilog into returning blocks");
511 assert((FrameSize & 0xf) == 0
512 && "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
514 // the "empty" frame size is 16 - just the register scavenger spill slot
515 if (FrameSize > 16 || MFI->adjustsStack()) {
516 FrameSize = FrameSize + SPUFrameInfo::minStackSize();
517 if (isInt<10>(FrameSize + LinkSlotOffset)) {
518 // Reload $lr, adjust $sp by required amount
519 // Note: We do this to slightly improve dual issue -- not by much, but it
520 // is an opportunity for dual issue.
521 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
522 .addImm(FrameSize + LinkSlotOffset)
524 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1)
527 } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
528 // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
529 // $r2 to adjust $sp:
530 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
533 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
535 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
538 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
541 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
544 BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2)
548 report_fatal_error("Unhandled frame size: " + Twine(FrameSize));
554 SPURegisterInfo::getRARegister() const
560 SPURegisterInfo::getFrameRegister(const MachineFunction &MF) const
566 SPURegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const
568 // Initial state of the frame pointer is R1.
569 MachineLocation Dst(MachineLocation::VirtualFP);
570 MachineLocation Src(SPU::R1, 0);
571 Moves.push_back(MachineMove(0, Dst, Src));
576 SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
577 // FIXME: Most probably dwarf numbers differs for Linux and Darwin
578 return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
582 SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
586 case SPU::AIr32: return SPU::Ar32;
587 case SPU::LQDr32: return SPU::LQXr32;
588 case SPU::LQDr128: return SPU::LQXr128;
589 case SPU::LQDv16i8: return SPU::LQXv16i8;
590 case SPU::LQDv4f32: return SPU::LQXv4f32;
591 case SPU::STQDr32: return SPU::STQXr32;
592 case SPU::STQDr128: return SPU::STQXr128;
593 case SPU::STQDv16i8: return SPU::STQXv16i8;
594 case SPU::STQDv4i32: return SPU::STQXv4i32;
595 case SPU::STQDv4f32: return SPU::STQXv4f32;
597 default: assert( false && "Unhandled D to X-form conversion");
599 // default will assert, but need to return something to keep the
604 // TODO this is already copied from PPC. Could this convenience function
605 // be moved to the RegScavenger class?
607 SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
609 const TargetRegisterClass *RC,
612 assert(RS && "Register scavenging must be on");
613 unsigned Reg = RS->FindUnusedReg(RC);
615 Reg = RS->scavengeRegister(RC, II, SPAdj);
616 assert( Reg && "Register scavenger failed");
620 #include "SPUGenRegisterInfo.inc"