1 //===- SPURegisterInfo.h - Cell SPU Register Information Impl ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef SPU_REGISTERINFO_H
16 #define SPU_REGISTERINFO_H
19 #include "SPUGenRegisterInfo.h.inc"
23 class TargetInstrInfo;
26 class SPURegisterInfo : public SPUGenRegisterInfo {
28 const SPUSubtarget &Subtarget;
29 const TargetInstrInfo &TII;
31 //! Predicate: Does the machine function use the link register?
32 bool usesLR(MachineFunction &MF) const;
35 SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
37 //! Translate a register's enum value to a register number
39 This method translates a register's enum value to it's regiser number,
42 static unsigned getRegisterNumbering(unsigned RegEnum);
44 /// getPointerRegClass - Return the register class to use to hold pointers.
45 /// This is used for addressing modes.
46 virtual const TargetRegisterClass *
47 getPointerRegClass(unsigned Kind = 0) const;
49 //! Return the array of callee-saved registers
50 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
52 //! Return the register class array of the callee-saved registers
53 virtual const TargetRegisterClass* const *
54 getCalleeSavedRegClasses(const MachineFunction *MF) const;
56 //! Allow for scavenging, so we can get scratch registers when needed.
57 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
60 //! Return the reserved registers
61 BitVector getReservedRegs(const MachineFunction &MF) const;
63 //! Prediate: Target has dedicated frame pointer
64 bool hasFP(const MachineFunction &MF) const;
65 //! Eliminate the call frame setup pseudo-instructions
66 void eliminateCallFramePseudoInstr(MachineFunction &MF,
67 MachineBasicBlock &MBB,
68 MachineBasicBlock::iterator I) const;
69 //! Convert frame indicies into machine operands
70 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
71 FrameIndexValue *Value = NULL,
72 RegScavenger *RS = NULL) const;
73 //! Determine the frame's layour
74 void determineFrameLayout(MachineFunction &MF) const;
76 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
77 RegScavenger *RS = NULL) const;
78 //! Emit the function prologue
79 void emitPrologue(MachineFunction &MF) const;
80 //! Emit the function epilogue
81 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
82 //! Get return address register (LR, aka R0)
83 unsigned getRARegister() const;
84 //! Get the stack frame register (SP, aka R1)
85 unsigned getFrameRegister(const MachineFunction &MF) const;
86 //! Perform target-specific stack frame setup.
87 void getInitialFrameState(std::vector<MachineMove> &Moves) const;
89 //------------------------------------------------------------------------
91 //------------------------------------------------------------------------
93 //! Return the array of argument passing registers
95 \note The size of this array is returned by getArgRegsSize().
97 static const unsigned *getArgRegs();
99 //! Return the size of the argument passing register array
100 static unsigned getNumArgRegs();
102 //! Get DWARF debugging register number
103 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
105 //! Convert D-form load/store to X-form load/store
107 Converts a regiser displacement load/store into a register-indexed
108 load/store for large stack frames, when the stack frame exceeds the
109 range of a s10 displacement.
111 int convertDFormToXForm(int dFormOpcode) const;
113 //! Acquire an unused register in an emergency.
114 unsigned findScratchRegister(MachineBasicBlock::iterator II,
116 const TargetRegisterClass *RC,
120 } // end namespace llvm