1 //===- SPURegisterInfo.h - Cell SPU Register Information Impl ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Cell SPU implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef SPU_REGISTERINFO_H
16 #define SPU_REGISTERINFO_H
19 #include "SPUGenRegisterInfo.h.inc"
23 class TargetInstrInfo;
26 class SPURegisterInfo : public SPUGenRegisterInfo {
28 const SPUSubtarget &Subtarget;
29 const TargetInstrInfo &TII;
31 //! Predicate: Does the machine function use the link register?
32 bool usesLR(MachineFunction &MF) const;
35 SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
37 //! Translate a register's enum value to a register number
39 This method translates a register's enum value to it's regiser number,
42 static unsigned getRegisterNumbering(unsigned RegEnum);
44 /// getPointerRegClass - Return the register class to use to hold pointers.
45 /// This is used for addressing modes.
46 virtual const TargetRegisterClass *
47 getPointerRegClass(unsigned Kind = 0) const;
49 /// After allocating this many registers, the allocator should feel
50 /// register pressure. The value is a somewhat random guess, based on the
51 /// number of non callee saved registers in the C calling convention.
52 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
53 MachineFunction &MF) const{
57 //! Return the array of callee-saved registers
58 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
60 //! Allow for scavenging, so we can get scratch registers when needed.
61 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
64 //! Return the reserved registers
65 BitVector getReservedRegs(const MachineFunction &MF) const;
67 //! Eliminate the call frame setup pseudo-instructions
68 void eliminateCallFramePseudoInstr(MachineFunction &MF,
69 MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator I) const;
71 //! Convert frame indicies into machine operands
72 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
73 RegScavenger *RS = NULL) const;
75 //! Get return address register (LR, aka R0)
76 unsigned getRARegister() const;
77 //! Get the stack frame register (SP, aka R1)
78 unsigned getFrameRegister(const MachineFunction &MF) const;
80 //------------------------------------------------------------------------
82 //------------------------------------------------------------------------
84 //! Get DWARF debugging register number
85 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
86 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
88 //! Convert D-form load/store to X-form load/store
90 Converts a regiser displacement load/store into a register-indexed
91 load/store for large stack frames, when the stack frame exceeds the
92 range of a s10 displacement.
94 int convertDFormToXForm(int dFormOpcode) const;
96 //! Acquire an unused register in an emergency.
97 unsigned findScratchRegister(MachineBasicBlock::iterator II,
99 const TargetRegisterClass *RC,
103 } // end namespace llvm