1 //===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by a team from the Computer Systems Research
6 // Department at The Aerospace Corporation and is distributed under the
7 // University of Illinois Open Source License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 def EVEN_UNIT : FuncUnit; // Even execution unit: (PC & 0x7 == 000)
15 def ODD_UNIT : FuncUnit; // Odd execution unit: (PC & 0x7 == 100)
17 //===----------------------------------------------------------------------===//
18 // Instruction Itinerary classes used for Cell SPU
19 //===----------------------------------------------------------------------===//
21 def LoadStore : InstrItinClass; // ODD_UNIT
22 def BranchHints : InstrItinClass; // ODD_UNIT
23 def BranchResolv : InstrItinClass; // ODD_UNIT
24 def ChanOpSPR : InstrItinClass; // ODD_UNIT
25 def ShuffleOp : InstrItinClass; // ODD_UNIT
26 def SelectOp : InstrItinClass; // ODD_UNIT
27 def GatherOp : InstrItinClass; // ODD_UNIT
28 def LoadNOP : InstrItinClass; // ODD_UNIT
29 def ExecNOP : InstrItinClass; // EVEN_UNIT
30 def SPrecFP : InstrItinClass; // EVEN_UNIT
31 def DPrecFP : InstrItinClass; // EVEN_UNIT
32 def FPInt : InstrItinClass; // EVEN_UNIT (FP<->integer)
33 def ByteOp : InstrItinClass; // EVEN_UNIT
34 def IntegerOp : InstrItinClass; // EVEN_UNIT
35 def IntegerMulDiv: InstrItinClass; // EVEN_UNIT
36 def RotateShift : InstrItinClass; // EVEN_UNIT
37 def ImmLoad : InstrItinClass; // EVEN_UNIT
39 /* Note: The itinerary for the Cell SPU is somewhat contrived... */
40 def SPUItineraries : ProcessorItineraries<[
41 InstrItinData<LoadStore , [InstrStage<6, [ODD_UNIT]>]>,
42 InstrItinData<BranchHints , [InstrStage<6, [ODD_UNIT]>]>,
43 InstrItinData<BranchResolv, [InstrStage<4, [ODD_UNIT]>]>,
44 InstrItinData<ChanOpSPR , [InstrStage<6, [ODD_UNIT]>]>,
45 InstrItinData<ShuffleOp , [InstrStage<4, [ODD_UNIT]>]>,
46 InstrItinData<SelectOp , [InstrStage<4, [ODD_UNIT]>]>,
47 InstrItinData<GatherOp , [InstrStage<4, [ODD_UNIT]>]>,
48 InstrItinData<LoadNOP , [InstrStage<1, [ODD_UNIT]>]>,
49 InstrItinData<ExecNOP , [InstrStage<1, [EVEN_UNIT]>]>,
50 InstrItinData<SPrecFP , [InstrStage<6, [EVEN_UNIT]>]>,
51 InstrItinData<DPrecFP , [InstrStage<13, [EVEN_UNIT]>]>,
52 InstrItinData<FPInt , [InstrStage<2, [EVEN_UNIT]>]>,
53 InstrItinData<ByteOp , [InstrStage<4, [EVEN_UNIT]>]>,
54 InstrItinData<IntegerOp , [InstrStage<2, [EVEN_UNIT]>]>,
55 InstrItinData<RotateShift , [InstrStage<4, [EVEN_UNIT]>]>,
56 InstrItinData<IntegerMulDiv,[InstrStage<7, [EVEN_UNIT]>]>,
57 InstrItinData<ImmLoad , [InstrStage<2, [EVEN_UNIT]>]>