1 //===--- BitTracker.cpp ---------------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // SSA-based bit propagation.
12 // The purpose of this code is, for a given virtual register, to provide
13 // information about the value of each bit in the register. The values
14 // of bits are represented by the class BitValue, and take one of four
15 // cases: 0, 1, "ref" and "bottom". The 0 and 1 are rather clear, the
16 // "ref" value means that the bit is a copy of another bit (which itself
17 // cannot be a copy of yet another bit---such chains are not allowed).
18 // A "ref" value is associated with a BitRef structure, which indicates
19 // which virtual register, and which bit in that register is the origin
20 // of the value. For example, given an instruction
21 // vreg2 = ASL vreg1, 1
22 // assuming that nothing is known about bits of vreg1, bit 1 of vreg2
23 // will be a "ref" to (vreg1, 0). If there is a subsequent instruction
24 // vreg3 = ASL vreg2, 2
25 // then bit 3 of vreg3 will be a "ref" to (vreg1, 0) as well.
26 // The "bottom" case means that the bit's value cannot be determined,
27 // and that this virtual register actually defines it. The "bottom" case
28 // is discussed in detail in BitTracker.h. In fact, "bottom" is a "ref
29 // to self", so for the vreg1 above, the bit 0 of it will be a "ref" to
30 // (vreg1, 0), bit 1 will be a "ref" to (vreg1, 1), etc.
32 // The tracker implements the Wegman-Zadeck algorithm, originally developed
33 // for SSA-based constant propagation. Each register is represented as
34 // a sequence of bits, with the convention that bit 0 is the least signi-
35 // ficant bit. Each bit is propagated individually. The class RegisterCell
36 // implements the register's representation, and is also the subject of
37 // the lattice operations in the tracker.
39 // The intended usage of the bit tracker is to create a target-specific
40 // machine instruction evaluator, pass the evaluator to the BitTracker
41 // object, and run the tracker. The tracker will then collect the bit
42 // value information for a given machine function. After that, it can be
43 // queried for the cells for each virtual register.
45 // const TargetSpecificEvaluator TSE(TRI, MRI);
46 // BitTracker BT(TSE, MF);
49 // unsigned Reg = interestingRegister();
50 // RegisterCell RC = BT.get(Reg);
54 // The code below is intended to be fully target-independent.
56 #include "llvm/CodeGen/MachineBasicBlock.h"
57 #include "llvm/CodeGen/MachineFunction.h"
58 #include "llvm/CodeGen/MachineInstr.h"
59 #include "llvm/CodeGen/MachineRegisterInfo.h"
60 #include "llvm/IR/Constants.h"
61 #include "llvm/Support/Debug.h"
62 #include "llvm/Support/raw_ostream.h"
63 #include "llvm/Target/TargetRegisterInfo.h"
65 #include "BitTracker.h"
69 typedef BitTracker BT;
72 // Local trickery to pretty print a register (without the whole "%vreg"
75 printv(unsigned r) : R(r) {}
78 raw_ostream &operator<< (raw_ostream &OS, const printv &PV) {
80 OS << 'v' << TargetRegisterInfo::virtReg2Index(PV.R);
88 raw_ostream &operator<< (raw_ostream &OS, const BT::BitValue &BV) {
90 case BT::BitValue::Top:
93 case BT::BitValue::Zero:
96 case BT::BitValue::One:
99 case BT::BitValue::Ref:
100 OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']';
107 raw_ostream &operator<< (raw_ostream &OS, const BT::RegisterCell &RC) {
108 unsigned n = RC.Bits.size();
110 // Instead of printing each bit value individually, try to group them
111 // into logical segments, such as sequences of 0 or 1 bits or references
112 // to consecutive bits (e.g. "bits 3-5 are same as bits 7-9 of reg xyz").
113 // "Start" will be the index of the beginning of the most recent segment.
115 bool SeqRef = false; // A sequence of refs to consecutive bits.
116 bool ConstRef = false; // A sequence of refs to the same bit.
118 for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) {
119 const BT::BitValue &V = RC[i];
120 const BT::BitValue &SV = RC[Start];
121 bool IsRef = (V.Type == BT::BitValue::Ref);
122 // If the current value is the same as Start, skip to the next one.
123 if (!IsRef && V == SV)
125 if (IsRef && SV.Type == BT::BitValue::Ref && V.RefI.Reg == SV.RefI.Reg) {
127 SeqRef = (V.RefI.Pos == SV.RefI.Pos+1);
128 ConstRef = (V.RefI.Pos == SV.RefI.Pos);
130 if (SeqRef && V.RefI.Pos == SV.RefI.Pos+(i-Start))
132 if (ConstRef && V.RefI.Pos == SV.RefI.Pos)
136 // The current value is different. Print the previous one and reset
139 unsigned Count = i - Start;
143 OS << '-' << i-1 << "]:";
144 if (SV.Type == BT::BitValue::Ref && SeqRef)
145 OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-'
146 << SV.RefI.Pos+(Count-1) << ']';
151 SeqRef = ConstRef = false;
155 unsigned Count = n - Start;
157 OS << "]:" << RC[Start];
159 OS << '-' << n-1 << "]:";
160 const BT::BitValue &SV = RC[Start];
161 if (SV.Type == BT::BitValue::Ref && SeqRef)
162 OS << printv(SV.RefI.Reg) << '[' << SV.RefI.Pos << '-'
163 << SV.RefI.Pos+(Count-1) << ']';
173 BitTracker::BitTracker(const MachineEvaluator &E, llvm::MachineFunction &F) :
174 Trace(false), ME(E), MF(F), MRI(F.getRegInfo()), Map(*new CellMapType) {
178 BitTracker::~BitTracker() {
183 // If we were allowed to update a cell for a part of a register, the meet
184 // operation would need to be parametrized by the register number and the
185 // exact part of the register, so that the computer BitRefs correspond to
186 // the actual bits of the "self" register.
187 // While this cannot happen in the current implementation, I'm not sure
188 // if this should be ruled out in the future.
189 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigned SelfR) {
190 // An example when "meet" can be invoked with SelfR == 0 is a phi node
191 // with a physical register as an operand.
192 assert(SelfR == 0 || TargetRegisterInfo::isVirtualRegister(SelfR));
193 bool Changed = false;
194 for (uint16_t i = 0, n = Bits.size(); i < n; ++i) {
195 const BitValue &RCV = RC[i];
196 Changed |= Bits[i].meet(RCV, BitRef(SelfR, i));
202 // Insert the entire cell RC into the current cell at position given by M.
203 BT::RegisterCell &BT::RegisterCell::insert(const BT::RegisterCell &RC,
205 uint16_t B = M.first(), E = M.last(), W = width();
206 // Sanity: M must be a valid mask for *this.
207 assert(B < W && E < W);
208 // Sanity: the masked part of *this must have the same number of bits
210 assert(B > E || E-B+1 == RC.width()); // B <= E => E-B+1 = |RC|.
211 assert(B <= E || E+(W-B)+1 == RC.width()); // E < B => E+(W-B)+1 = |RC|.
213 for (uint16_t i = 0; i <= E-B; ++i)
216 for (uint16_t i = 0; i < W-B; ++i)
218 for (uint16_t i = 0; i <= E; ++i)
219 Bits[i] = RC[i+(W-B)];
225 BT::RegisterCell BT::RegisterCell::extract(const BitMask &M) const {
226 uint16_t B = M.first(), E = M.last(), W = width();
227 assert(B < W && E < W);
229 RegisterCell RC(E-B+1);
230 for (uint16_t i = B; i <= E; ++i)
231 RC.Bits[i-B] = Bits[i];
235 RegisterCell RC(E+(W-B)+1);
236 for (uint16_t i = 0; i < W-B; ++i)
237 RC.Bits[i] = Bits[i+B];
238 for (uint16_t i = 0; i <= E; ++i)
239 RC.Bits[i+(W-B)] = Bits[i];
244 BT::RegisterCell &BT::RegisterCell::rol(uint16_t Sh) {
245 // Rotate left (i.e. towards increasing bit indices).
246 // Swap the two parts: [0..W-Sh-1] [W-Sh..W-1]
247 uint16_t W = width();
252 RegisterCell Tmp(W-Sh);
253 // Tmp = [0..W-Sh-1].
254 for (uint16_t i = 0; i < W-Sh; ++i)
256 // Shift [W-Sh..W-1] to [0..Sh-1].
257 for (uint16_t i = 0; i < Sh; ++i)
258 Bits[i] = Bits[W-Sh+i];
259 // Copy Tmp to [Sh..W-1].
260 for (uint16_t i = 0; i < W-Sh; ++i)
261 Bits[i+Sh] = Tmp.Bits[i];
266 BT::RegisterCell &BT::RegisterCell::fill(uint16_t B, uint16_t E,
275 BT::RegisterCell &BT::RegisterCell::cat(const RegisterCell &RC) {
276 // Append the cell given as the argument to the "this" cell.
277 // Bit 0 of RC becomes bit W of the result, where W is this->width().
278 uint16_t W = width(), WRC = RC.width();
280 for (uint16_t i = 0; i < WRC; ++i)
281 Bits[i+W] = RC.Bits[i];
286 uint16_t BT::RegisterCell::ct(bool B) const {
287 uint16_t W = width();
290 while (C < W && Bits[C] == V)
296 uint16_t BT::RegisterCell::cl(bool B) const {
297 uint16_t W = width();
300 while (C < W && Bits[W-(C+1)] == V)
306 bool BT::RegisterCell::operator== (const RegisterCell &RC) const {
307 uint16_t W = Bits.size();
308 if (RC.Bits.size() != W)
310 for (uint16_t i = 0; i < W; ++i)
311 if (Bits[i] != RC[i])
317 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
318 // The general problem is with finding a register class that corresponds
319 // to a given reference reg:sub. There can be several such classes, and
320 // since we only care about the register size, it does not matter which
321 // such class we would find.
322 // The easiest way to accomplish what we want is to
323 // 1. find a physical register PhysR from the same class as RR.Reg,
324 // 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
325 // 3. find a register class that contains PhysS.
327 if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) {
328 const TargetRegisterClass *VC = MRI.getRegClass(RR.Reg);
329 assert(VC->begin() != VC->end() && "Empty register class");
330 PhysR = *VC->begin();
332 assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));
336 unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub);
337 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PhysS);
338 uint16_t BW = RC->getSize()*8;
343 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,
344 const CellMapType &M) const {
345 uint16_t BW = getRegBitWidth(RR);
347 // Physical registers are assumed to be present in the map with an unknown
348 // value. Don't actually insert anything in the map, just return the cell.
349 if (TargetRegisterInfo::isPhysicalRegister(RR.Reg))
350 return RegisterCell::self(0, BW);
352 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg));
353 // For virtual registers that belong to a class that is not tracked,
354 // generate an "unknown" value as well.
355 const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);
357 return RegisterCell::self(0, BW);
359 CellMapType::const_iterator F = M.find(RR.Reg);
363 BitMask M = mask(RR.Reg, RR.Sub);
364 return F->second.extract(M);
366 // If not found, create a "top" entry, but do not insert it in the map.
367 return RegisterCell::top(BW);
371 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC,
372 CellMapType &M) const {
373 // While updating the cell map can be done in a meaningful way for
374 // a part of a register, it makes little sense to implement it as the
375 // SSA representation would never contain such "partial definitions".
376 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
378 assert(RR.Sub == 0 && "Unexpected sub-register in definition");
379 // Eliminate all ref-to-reg-0 bit values: replace them with "self".
380 for (unsigned i = 0, n = RC.width(); i < n; ++i) {
381 const BitValue &V = RC[i];
382 if (V.Type == BitValue::Ref && V.RefI.Reg == 0)
383 RC[i].RefI = BitRef(RR.Reg, i);
389 // Check if the cell represents a compile-time integer value.
390 bool BT::MachineEvaluator::isInt(const RegisterCell &A) const {
391 uint16_t W = A.width();
392 for (uint16_t i = 0; i < W; ++i)
393 if (!A[i].is(0) && !A[i].is(1))
399 // Convert a cell to the integer value. The result must fit in uint64_t.
400 uint64_t BT::MachineEvaluator::toInt(const RegisterCell &A) const {
403 uint16_t W = A.width();
404 for (uint16_t i = 0; i < W; ++i) {
412 // Evaluator helper functions. These implement some common operation on
413 // register cells that can be used to implement target-specific instructions
414 // in a target-specific evaluator.
416 BT::RegisterCell BT::MachineEvaluator::eIMM(int64_t V, uint16_t W) const {
418 // For bits beyond the 63rd, this will generate the sign bit of V.
419 for (uint16_t i = 0; i < W; ++i) {
420 Res[i] = BitValue(V & 1);
427 BT::RegisterCell BT::MachineEvaluator::eIMM(const ConstantInt *CI) const {
428 APInt A = CI->getValue();
429 uint16_t BW = A.getBitWidth();
430 assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow");
431 RegisterCell Res(BW);
432 for (uint16_t i = 0; i < BW; ++i)
438 BT::RegisterCell BT::MachineEvaluator::eADD(const RegisterCell &A1,
439 const RegisterCell &A2) const {
440 uint16_t W = A1.width();
441 assert(W == A2.width());
445 for (I = 0; I < W; ++I) {
446 const BitValue &V1 = A1[I];
447 const BitValue &V2 = A2[I];
448 if (!V1.num() || !V2.num())
450 unsigned S = bool(V1) + bool(V2) + Carry;
451 Res[I] = BitValue(S & 1);
455 const BitValue &V1 = A1[I];
456 const BitValue &V2 = A2[I];
457 // If the next bit is same as Carry, the result will be 0 plus the
458 // other bit. The Carry bit will remain unchanged.
460 Res[I] = BitValue::ref(V2);
461 else if (V2.is(Carry))
462 Res[I] = BitValue::ref(V1);
467 Res[I] = BitValue::self();
472 BT::RegisterCell BT::MachineEvaluator::eSUB(const RegisterCell &A1,
473 const RegisterCell &A2) const {
474 uint16_t W = A1.width();
475 assert(W == A2.width());
479 for (I = 0; I < W; ++I) {
480 const BitValue &V1 = A1[I];
481 const BitValue &V2 = A2[I];
482 if (!V1.num() || !V2.num())
484 unsigned S = bool(V1) - bool(V2) - Borrow;
485 Res[I] = BitValue(S & 1);
489 const BitValue &V1 = A1[I];
490 const BitValue &V2 = A2[I];
492 Res[I] = BitValue::ref(V2);
496 Res[I] = BitValue::ref(V1);
501 Res[I] = BitValue::self();
506 BT::RegisterCell BT::MachineEvaluator::eMLS(const RegisterCell &A1,
507 const RegisterCell &A2) const {
508 uint16_t W = A1.width() + A2.width();
509 uint16_t Z = A1.ct(0) + A2.ct(0);
511 Res.fill(0, Z, BitValue::Zero);
512 Res.fill(Z, W, BitValue::self());
517 BT::RegisterCell BT::MachineEvaluator::eMLU(const RegisterCell &A1,
518 const RegisterCell &A2) const {
519 uint16_t W = A1.width() + A2.width();
520 uint16_t Z = A1.ct(0) + A2.ct(0);
522 Res.fill(0, Z, BitValue::Zero);
523 Res.fill(Z, W, BitValue::self());
528 BT::RegisterCell BT::MachineEvaluator::eASL(const RegisterCell &A1,
530 assert(Sh <= A1.width());
531 RegisterCell Res = RegisterCell::ref(A1);
533 Res.fill(0, Sh, BitValue::Zero);
538 BT::RegisterCell BT::MachineEvaluator::eLSR(const RegisterCell &A1,
540 uint16_t W = A1.width();
542 RegisterCell Res = RegisterCell::ref(A1);
544 Res.fill(W-Sh, W, BitValue::Zero);
549 BT::RegisterCell BT::MachineEvaluator::eASR(const RegisterCell &A1,
551 uint16_t W = A1.width();
553 RegisterCell Res = RegisterCell::ref(A1);
554 BitValue Sign = Res[W-1];
556 Res.fill(W-Sh, W, Sign);
561 BT::RegisterCell BT::MachineEvaluator::eAND(const RegisterCell &A1,
562 const RegisterCell &A2) const {
563 uint16_t W = A1.width();
564 assert(W == A2.width());
566 for (uint16_t i = 0; i < W; ++i) {
567 const BitValue &V1 = A1[i];
568 const BitValue &V2 = A2[i];
570 Res[i] = BitValue::ref(V2);
572 Res[i] = BitValue::ref(V1);
573 else if (V1.is(0) || V2.is(0))
574 Res[i] = BitValue::Zero;
578 Res[i] = BitValue::self();
584 BT::RegisterCell BT::MachineEvaluator::eORL(const RegisterCell &A1,
585 const RegisterCell &A2) const {
586 uint16_t W = A1.width();
587 assert(W == A2.width());
589 for (uint16_t i = 0; i < W; ++i) {
590 const BitValue &V1 = A1[i];
591 const BitValue &V2 = A2[i];
592 if (V1.is(1) || V2.is(1))
593 Res[i] = BitValue::One;
595 Res[i] = BitValue::ref(V2);
597 Res[i] = BitValue::ref(V1);
601 Res[i] = BitValue::self();
607 BT::RegisterCell BT::MachineEvaluator::eXOR(const RegisterCell &A1,
608 const RegisterCell &A2) const {
609 uint16_t W = A1.width();
610 assert(W == A2.width());
612 for (uint16_t i = 0; i < W; ++i) {
613 const BitValue &V1 = A1[i];
614 const BitValue &V2 = A2[i];
616 Res[i] = BitValue::ref(V2);
618 Res[i] = BitValue::ref(V1);
620 Res[i] = BitValue::Zero;
622 Res[i] = BitValue::self();
628 BT::RegisterCell BT::MachineEvaluator::eNOT(const RegisterCell &A1) const {
629 uint16_t W = A1.width();
631 for (uint16_t i = 0; i < W; ++i) {
632 const BitValue &V = A1[i];
634 Res[i] = BitValue::One;
636 Res[i] = BitValue::Zero;
638 Res[i] = BitValue::self();
644 BT::RegisterCell BT::MachineEvaluator::eSET(const RegisterCell &A1,
645 uint16_t BitN) const {
646 assert(BitN < A1.width());
647 RegisterCell Res = RegisterCell::ref(A1);
648 Res[BitN] = BitValue::One;
653 BT::RegisterCell BT::MachineEvaluator::eCLR(const RegisterCell &A1,
654 uint16_t BitN) const {
655 assert(BitN < A1.width());
656 RegisterCell Res = RegisterCell::ref(A1);
657 Res[BitN] = BitValue::Zero;
662 BT::RegisterCell BT::MachineEvaluator::eCLB(const RegisterCell &A1, bool B,
664 uint16_t C = A1.cl(B), AW = A1.width();
665 // If the last leading non-B bit is not a constant, then we don't know
667 if ((C < AW && A1[AW-1-C].num()) || C == AW)
669 return RegisterCell::self(0, W);
673 BT::RegisterCell BT::MachineEvaluator::eCTB(const RegisterCell &A1, bool B,
675 uint16_t C = A1.ct(B), AW = A1.width();
676 // If the last trailing non-B bit is not a constant, then we don't know
678 if ((C < AW && A1[C].num()) || C == AW)
680 return RegisterCell::self(0, W);
684 BT::RegisterCell BT::MachineEvaluator::eSXT(const RegisterCell &A1,
685 uint16_t FromN) const {
686 uint16_t W = A1.width();
688 RegisterCell Res = RegisterCell::ref(A1);
689 BitValue Sign = Res[FromN-1];
690 // Sign-extend "inreg".
691 Res.fill(FromN, W, Sign);
696 BT::RegisterCell BT::MachineEvaluator::eZXT(const RegisterCell &A1,
697 uint16_t FromN) const {
698 uint16_t W = A1.width();
700 RegisterCell Res = RegisterCell::ref(A1);
701 Res.fill(FromN, W, BitValue::Zero);
706 BT::RegisterCell BT::MachineEvaluator::eXTR(const RegisterCell &A1,
707 uint16_t B, uint16_t E) const {
708 uint16_t W = A1.width();
709 assert(B < W && E <= W);
711 return RegisterCell(0);
712 uint16_t Last = (E > 0) ? E-1 : W-1;
713 RegisterCell Res = RegisterCell::ref(A1).extract(BT::BitMask(B, Last));
714 // Return shorter cell.
719 BT::RegisterCell BT::MachineEvaluator::eINS(const RegisterCell &A1,
720 const RegisterCell &A2, uint16_t AtN) const {
721 uint16_t W1 = A1.width(), W2 = A2.width();
723 assert(AtN < W1 && AtN+W2 <= W1);
724 // Copy bits from A1, insert A2 at position AtN.
725 RegisterCell Res = RegisterCell::ref(A1);
727 Res.insert(RegisterCell::ref(A2), BT::BitMask(AtN, AtN+W2-1));
732 BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const {
733 assert(Sub == 0 && "Generic BitTracker::mask called for Sub != 0");
734 uint16_t W = getRegBitWidth(Reg);
735 assert(W > 0 && "Cannot generate mask for empty register");
736 return BitMask(0, W-1);
740 bool BT::MachineEvaluator::evaluate(const MachineInstr *MI,
741 const CellMapType &Inputs, CellMapType &Outputs) const {
742 unsigned Opc = MI->getOpcode();
744 case TargetOpcode::REG_SEQUENCE: {
745 RegisterRef RD = MI->getOperand(0);
747 RegisterRef RS = MI->getOperand(1);
748 unsigned SS = MI->getOperand(2).getImm();
749 RegisterRef RT = MI->getOperand(3);
750 unsigned ST = MI->getOperand(4).getImm();
753 uint16_t W = getRegBitWidth(RD);
755 Res.insert(RegisterCell::ref(getCell(RS, Inputs)), mask(RD.Reg, SS));
756 Res.insert(RegisterCell::ref(getCell(RT, Inputs)), mask(RD.Reg, ST));
757 putCell(RD, Res, Outputs);
761 case TargetOpcode::COPY: {
762 // COPY can transfer a smaller register into a wider one.
763 // If that is the case, fill the remaining high bits with 0.
764 RegisterRef RD = MI->getOperand(0);
765 RegisterRef RS = MI->getOperand(1);
767 uint16_t WD = getRegBitWidth(RD);
768 uint16_t WS = getRegBitWidth(RS);
770 RegisterCell Src = getCell(RS, Inputs);
771 RegisterCell Res(WD);
772 Res.insert(Src, BitMask(0, WS-1));
773 Res.fill(WS, WD, BitValue::Zero);
774 putCell(RD, Res, Outputs);
786 // Main W-Z implementation.
788 void BT::visitPHI(const MachineInstr *PI) {
789 int ThisN = PI->getParent()->getNumber();
791 dbgs() << "Visit FI(BB#" << ThisN << "): " << *PI;
793 const MachineOperand &MD = PI->getOperand(0);
794 assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition");
795 RegisterRef DefRR(MD);
796 uint16_t DefBW = ME.getRegBitWidth(DefRR);
798 RegisterCell DefC = ME.getCell(DefRR, Map);
799 if (DefC == RegisterCell::self(DefRR.Reg, DefBW)) // XXX slow
802 bool Changed = false;
804 for (unsigned i = 1, n = PI->getNumOperands(); i < n; i += 2) {
805 const MachineBasicBlock *PB = PI->getOperand(i+1).getMBB();
806 int PredN = PB->getNumber();
808 dbgs() << " edge BB#" << PredN << "->BB#" << ThisN;
809 if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
811 dbgs() << " not executable\n";
815 RegisterRef RU = PI->getOperand(i);
816 RegisterCell ResC = ME.getCell(RU, Map);
818 dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
819 << " cell: " << ResC << "\n";
820 Changed |= DefC.meet(ResC, DefRR.Reg);
825 dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
826 << " cell: " << DefC << "\n";
827 ME.putCell(DefRR, DefC, Map);
828 visitUsesOf(DefRR.Reg);
833 void BT::visitNonBranch(const MachineInstr *MI) {
835 int ThisN = MI->getParent()->getNumber();
836 dbgs() << "Visit MI(BB#" << ThisN << "): " << *MI;
838 if (MI->isDebugValue())
840 assert(!MI->isBranch() && "Unexpected branch instruction");
843 bool Eval = ME.evaluate(MI, Map, ResMap);
846 for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
847 const MachineOperand &MO = MI->getOperand(i);
848 if (!MO.isReg() || !MO.isUse())
851 dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
852 << " cell: " << ME.getCell(RU, Map) << "\n";
854 dbgs() << "Outputs:\n";
855 for (CellMapType::iterator I = ResMap.begin(), E = ResMap.end();
857 RegisterRef RD(I->first);
858 dbgs() << " " << PrintReg(I->first, &ME.TRI) << " cell: "
859 << ME.getCell(RD, ResMap) << "\n";
863 // Iterate over all definitions of the instruction, and update the
864 // cells accordingly.
865 for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
866 const MachineOperand &MO = MI->getOperand(i);
867 // Visit register defs only.
868 if (!MO.isReg() || !MO.isDef())
871 assert(RD.Sub == 0 && "Unexpected sub-register in definition");
872 if (!TargetRegisterInfo::isVirtualRegister(RD.Reg))
875 bool Changed = false;
876 if (!Eval || !ResMap.has(RD.Reg)) {
877 // Set to "ref" (aka "bottom").
878 uint16_t DefBW = ME.getRegBitWidth(RD);
879 RegisterCell RefC = RegisterCell::self(RD.Reg, DefBW);
880 if (RefC != ME.getCell(RD, Map)) {
881 ME.putCell(RD, RefC, Map);
885 RegisterCell DefC = ME.getCell(RD, Map);
886 RegisterCell ResC = ME.getCell(RD, ResMap);
887 // This is a non-phi instruction, so the values of the inputs come
888 // from the same registers each time this instruction is evaluated.
889 // During the propagation, the values of the inputs can become lowered
890 // in the sense of the lattice operation, which may cause different
891 // results to be calculated in subsequent evaluations. This should
892 // not cause the bottoming of the result in the map, since the new
893 // result is already reflecting the lowered inputs.
894 for (uint16_t i = 0, w = DefC.width(); i < w; ++i) {
895 BitValue &V = DefC[i];
896 // Bits that are already "bottom" should not be updated.
897 if (V.Type == BitValue::Ref && V.RefI.Reg == RD.Reg)
899 // Same for those that are identical in DefC and ResC.
906 ME.putCell(RD, DefC, Map);
914 void BT::visitBranchesFrom(const MachineInstr *BI) {
915 const MachineBasicBlock &B = *BI->getParent();
916 MachineBasicBlock::const_iterator It = BI, End = B.end();
917 BranchTargetList Targets, BTs;
918 bool FallsThrough = true, DefaultToAll = false;
919 int ThisN = B.getNumber();
923 const MachineInstr *MI = &*It;
925 dbgs() << "Visit BR(BB#" << ThisN << "): " << *MI;
926 assert(MI->isBranch() && "Expecting branch instruction");
927 InstrExec.insert(MI);
928 bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough);
930 // If the evaluation failed, we will add all targets. Keep going in
931 // the loop to mark all executable branches as such.
935 dbgs() << " failed to evaluate: will add all CFG successors\n";
936 } else if (!DefaultToAll) {
937 // If evaluated successfully add the targets to the cumulative list.
939 dbgs() << " adding targets:";
940 for (unsigned i = 0, n = BTs.size(); i < n; ++i)
941 dbgs() << " BB#" << BTs[i]->getNumber();
943 dbgs() << "\n falls through\n";
945 dbgs() << "\n does not fall through\n";
947 Targets.insert(BTs.begin(), BTs.end());
950 } while (FallsThrough && It != End);
952 typedef MachineBasicBlock::const_succ_iterator succ_iterator;
954 // Need to add all CFG successors that lead to EH landing pads.
955 // There won't be explicit branches to these blocks, but they must
957 for (succ_iterator I = B.succ_begin(), E = B.succ_end(); I != E; ++I) {
958 const MachineBasicBlock *SB = *I;
959 if (SB->isLandingPad())
963 MachineFunction::const_iterator BIt = &B;
964 MachineFunction::const_iterator Next = std::next(BIt);
965 if (Next != MF.end())
966 Targets.insert(&*Next);
969 for (succ_iterator I = B.succ_begin(), E = B.succ_end(); I != E; ++I)
973 for (unsigned i = 0, n = Targets.size(); i < n; ++i) {
974 int TargetN = Targets[i]->getNumber();
975 FlowQ.push(CFGEdge(ThisN, TargetN));
980 void BT::visitUsesOf(unsigned Reg) {
982 dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n";
984 typedef MachineRegisterInfo::use_nodbg_iterator use_iterator;
985 use_iterator End = MRI.use_nodbg_end();
986 for (use_iterator I = MRI.use_nodbg_begin(Reg); I != End; ++I) {
987 MachineInstr *UseI = I->getParent();
988 if (!InstrExec.count(UseI))
992 else if (!UseI->isBranch())
993 visitNonBranch(UseI);
995 visitBranchesFrom(UseI);
1000 BT::RegisterCell BT::get(RegisterRef RR) const {
1001 return ME.getCell(RR, Map);
1005 void BT::put(RegisterRef RR, const RegisterCell &RC) {
1006 ME.putCell(RR, RC, Map);
1010 // Replace all references to bits from OldRR with the corresponding bits
1012 void BT::subst(RegisterRef OldRR, RegisterRef NewRR) {
1013 assert(Map.has(OldRR.Reg) && "OldRR not present in map");
1014 BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub);
1015 BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub);
1016 uint16_t OMB = OM.first(), OME = OM.last();
1017 uint16_t NMB = NM.first(), NME = NM.last();
1019 assert((OME-OMB == NME-NMB) &&
1020 "Substituting registers of different lengths");
1021 for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I) {
1022 RegisterCell &RC = I->second;
1023 for (uint16_t i = 0, w = RC.width(); i < w; ++i) {
1024 BitValue &V = RC[i];
1025 if (V.Type != BitValue::Ref || V.RefI.Reg != OldRR.Reg)
1027 if (V.RefI.Pos < OMB || V.RefI.Pos > OME)
1029 V.RefI.Reg = NewRR.Reg;
1030 V.RefI.Pos += NMB-OMB;
1036 // Check if the block has been "executed" during propagation. (If not, the
1037 // block is dead, but it may still appear to be reachable.)
1038 bool BT::reached(const MachineBasicBlock *B) const {
1039 int BN = B->getNumber();
1041 for (EdgeSetType::iterator I = EdgeExec.begin(), E = EdgeExec.end();
1043 if (I->second == BN)
1059 assert(FlowQ.empty());
1061 typedef GraphTraits<const MachineFunction*> MachineFlowGraphTraits;
1062 const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF);
1065 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
1067 assert(I->getNumber() >= 0 && "Disconnected block");
1068 unsigned BN = I->getNumber();
1073 // Keep track of visited blocks.
1074 BitVector BlockScanned(MaxBN+1);
1076 int EntryN = Entry->getNumber();
1077 // Generate a fake edge to get something to start with.
1078 FlowQ.push(CFGEdge(-1, EntryN));
1080 while (!FlowQ.empty()) {
1081 CFGEdge Edge = FlowQ.front();
1084 if (EdgeExec.count(Edge))
1086 EdgeExec.insert(Edge);
1088 const MachineBasicBlock &B = *MF.getBlockNumbered(Edge.second);
1089 MachineBasicBlock::const_iterator It = B.begin(), End = B.end();
1090 // Visit PHI nodes first.
1091 while (It != End && It->isPHI()) {
1092 const MachineInstr *PI = &*It++;
1093 InstrExec.insert(PI);
1097 // If this block has already been visited through a flow graph edge,
1098 // then the instructions have already been processed. Any updates to
1099 // the cells would now only happen through visitUsesOf...
1100 if (BlockScanned[Edge.second])
1102 BlockScanned[Edge.second] = true;
1104 // Visit non-branch instructions.
1105 while (It != End && !It->isBranch()) {
1106 const MachineInstr *MI = &*It++;
1107 InstrExec.insert(MI);
1110 // If block end has been reached, add the fall-through edge to the queue.
1112 MachineFunction::const_iterator BIt = &B;
1113 MachineFunction::const_iterator Next = std::next(BIt);
1114 if (Next != MF.end()) {
1115 int ThisN = B.getNumber();
1116 int NextN = Next->getNumber();
1117 FlowQ.push(CFGEdge(ThisN, NextN));
1120 // Handle the remaining sequence of branches. This function will update
1122 visitBranchesFrom(It);
1124 } // while (!FlowQ->empty())
1127 dbgs() << "Cells after propagation:\n";
1128 for (CellMapType::iterator I = Map.begin(), E = Map.end(); I != E; ++I)
1129 dbgs() << PrintReg(I->first, &ME.TRI) << " -> " << I->second << "\n";