lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

   1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "Hexagon.h"
  11 #include "MCTargetDesc/HexagonBaseInfo.h"
  12 #include "MCTargetDesc/HexagonMCInstrInfo.h"
  13 #include "MCTargetDesc/HexagonMCTargetDesc.h"
  14
  15 #include "llvm/MC/MCContext.h"
  16 #include "llvm/MC/MCDisassembler.h"
  17 #include "llvm/MC/MCExpr.h"
  18 #include "llvm/MC/MCFixedLenDisassembler.h"
  19 #include "llvm/MC/MCInst.h"
  20 #include "llvm/MC/MCInstrDesc.h"
  21 #include "llvm/MC/MCSubtargetInfo.h"
  22 #include "llvm/Support/Debug.h"
  23 #include "llvm/Support/Endian.h"
  24 #include "llvm/Support/ErrorHandling.h"
  25 #include "llvm/Support/LEB128.h"
  26 #include "llvm/Support/TargetRegistry.h"
  27 #include "llvm/Support/raw_ostream.h"
  28 #include <array>
  29 #include <vector>
  30
  31 using namespace llvm;
  32 using namespace Hexagon;
  33
  34 #define DEBUG_TYPE "hexagon-disassembler"
  35
  36 // Pull DecodeStatus and its enum values into the global namespace.
  37 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
  38
  39 namespace {
  40 /// \brief Hexagon disassembler for all Hexagon platforms.
  41 class HexagonDisassembler : public MCDisassembler {
  42 public:
  43   std::unique_ptr<MCInst *> CurrentBundle;
  44   HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
  45       : MCDisassembler(STI, Ctx), CurrentBundle(new MCInst *) {}
  46
  47   DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
  48                                     ArrayRef<uint8_t> Bytes, uint64_t Address,
  49                                     raw_ostream &VStream, raw_ostream &CStream,
  50                                     bool &Complete) const;
  51   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
  52                               ArrayRef<uint8_t> Bytes, uint64_t Address,
  53                               raw_ostream &VStream,
  54                               raw_ostream &CStream) const override;
  55 };
  56 }
  57
  58 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
  59                                                uint64_t Address,
  60                                                const void *Decoder);
  61 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
  62                                                uint64_t Address,
  63                                                const void *Decoder);
  64 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
  65                                                  uint64_t Address,
  66                                                  void const *Decoder);
  67
  68 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
  69                                  raw_ostream &os);
  70 static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst);
  71
  72 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  73                                   const void *Decoder);
  74 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  75                                   const void *Decoder);
  76 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  77                                     const void *Decoder);
  78 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  79                                     const void *Decoder);
  80 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  81                                     const void *Decoder);
  82 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  83                                     const void *Decoder);
  84 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  85                                   const void *Decoder);
  86 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  87                                  const void *Decoder);
  88 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  89                                    const void *Decoder);
  90 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  91                                    const void *Decoder);
  92 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  93                                    const void *Decoder);
  94 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  95                                    const void *Decoder);
  96 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
  97                                    const void *Decoder);
  98
  99 static const uint16_t IntRegDecoderTable[] = {
 100     Hexagon::R0,  Hexagon::R1,  Hexagon::R2,  Hexagon::R3,  Hexagon::R4,
 101     Hexagon::R5,  Hexagon::R6,  Hexagon::R7,  Hexagon::R8,  Hexagon::R9,
 102     Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
 103     Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
 104     Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
 105     Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
 106     Hexagon::R30, Hexagon::R31};
 107
 108 static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
 109                                                Hexagon::P2, Hexagon::P3};
 110
 111 static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
 112                                         const uint16_t Table[], size_t Size) {
 113   if (RegNo < Size) {
 114     Inst.addOperand(MCOperand::createReg(Table[RegNo]));
 115     return MCDisassembler::Success;
 116   } else
 117     return MCDisassembler::Fail;
 118 }
 119
 120 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
 121                                                uint64_t /*Address*/,
 122                                                void const *Decoder) {
 123   if (RegNo > 31)
 124     return MCDisassembler::Fail;
 125
 126   unsigned Register = IntRegDecoderTable[RegNo];
 127   Inst.addOperand(MCOperand::createReg(Register));
 128   return MCDisassembler::Success;
 129 }
 130
 131 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
 132                                                uint64_t /*Address*/,
 133                                                const void *Decoder) {
 134   static const uint16_t CtrlRegDecoderTable[] = {
 135       Hexagon::SA0,  Hexagon::LC0,        Hexagon::SA1,  Hexagon::LC1,
 136       Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6,   Hexagon::C7,
 137       Hexagon::USR,  Hexagon::PC,         Hexagon::UGP,  Hexagon::GP,
 138       Hexagon::CS0,  Hexagon::CS1,        Hexagon::UPCL, Hexagon::UPCH};
 139
 140   if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))
 141     return MCDisassembler::Fail;
 142
 143   if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
 144     return MCDisassembler::Fail;
 145
 146   unsigned Register = CtrlRegDecoderTable[RegNo];
 147   Inst.addOperand(MCOperand::createReg(Register));
 148   return MCDisassembler::Success;
 149 }
 150
 151 static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
 152                                                  uint64_t /*Address*/,
 153                                                  void const *Decoder) {
 154   static const uint16_t CtrlReg64DecoderTable[] = {
 155       Hexagon::C1_0,       Hexagon::NoRegister, Hexagon::C3_2,
 156       Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister,
 157       Hexagon::C7_6,       Hexagon::NoRegister, Hexagon::C9_8,
 158       Hexagon::NoRegister, Hexagon::C11_10,     Hexagon::NoRegister,
 159       Hexagon::CS,         Hexagon::NoRegister, Hexagon::UPC,
 160       Hexagon::NoRegister};
 161
 162   if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))
 163     return MCDisassembler::Fail;
 164
 165   if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister)
 166     return MCDisassembler::Fail;
 167
 168   unsigned Register = CtrlReg64DecoderTable[RegNo];
 169   Inst.addOperand(MCOperand::createReg(Register));
 170   return MCDisassembler::Success;
 171 }
 172
 173 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
 174                                                uint64_t /*Address*/,
 175                                                const void *Decoder) {
 176   unsigned Register = 0;
 177   switch (RegNo) {
 178   case 0:
 179     Register = Hexagon::M0;
 180     break;
 181   case 1:
 182     Register = Hexagon::M1;
 183     break;
 184   default:
 185     return MCDisassembler::Fail;
 186   }
 187   Inst.addOperand(MCOperand::createReg(Register));
 188   return MCDisassembler::Success;
 189 }
 190
 191 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
 192                                                   uint64_t /*Address*/,
 193                                                   const void *Decoder) {
 194   static const uint16_t DoubleRegDecoderTable[] = {
 195       Hexagon::D0,  Hexagon::D1,  Hexagon::D2,  Hexagon::D3,
 196       Hexagon::D4,  Hexagon::D5,  Hexagon::D6,  Hexagon::D7,
 197       Hexagon::D8,  Hexagon::D9,  Hexagon::D10, Hexagon::D11,
 198       Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
 199
 200   return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable,
 201                               sizeof(DoubleRegDecoderTable)));
 202 }
 203
 204 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
 205                                                 uint64_t /*Address*/,
 206                                                 void const *Decoder) {
 207   if (RegNo > 3)
 208     return MCDisassembler::Fail;
 209
 210   unsigned Register = PredRegDecoderTable[RegNo];
 211   Inst.addOperand(MCOperand::createReg(Register));
 212   return MCDisassembler::Success;
 213 }
 214
 215 #include "HexagonGenDisassemblerTables.inc"
 216
 217 static MCDisassembler *createHexagonDisassembler(Target const &T,
 218                                                  MCSubtargetInfo const &STI,
 219                                                  MCContext &Ctx) {
 220   return new HexagonDisassembler(STI, Ctx);
 221 }
 222
 223 extern "C" void LLVMInitializeHexagonDisassembler() {
 224   TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
 225                                          createHexagonDisassembler);
 226 }
 227
 228 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
 229                                                  ArrayRef<uint8_t> Bytes,
 230                                                  uint64_t Address,
 231                                                  raw_ostream &os,
 232                                                  raw_ostream &cs) const {
 233   DecodeStatus Result = DecodeStatus::Success;
 234   bool Complete = false;
 235   Size = 0;
 236
 237   *CurrentBundle = &MI;
 238   MI.clear();
 239   MI.setOpcode(Hexagon::BUNDLE);
 240   MI.addOperand(MCOperand::createImm(0));
 241   while (Result == Success && Complete == false) {
 242     if (Bytes.size() < HEXAGON_INSTR_SIZE)
 243       return MCDisassembler::Fail;
 244     MCInst *Inst = new (getContext()) MCInst;
 245     Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
 246     MI.addOperand(MCOperand::createInst(Inst));
 247     Size += HEXAGON_INSTR_SIZE;
 248     Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
 249   }
 250   return Result;
 251 }
 252
 253 DecodeStatus HexagonDisassembler::getSingleInstruction(
 254     MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
 255     raw_ostream &os, raw_ostream &cs, bool &Complete) const {
 256   assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
 257
 258   uint32_t Instruction =
 259       llvm::support::endian::read<uint32_t, llvm::support::little,
 260                                   llvm::support::unaligned>(Bytes.data());
 261
 262   auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
 263   if ((Instruction & HexagonII::INST_PARSE_MASK) ==
 264       HexagonII::INST_PARSE_LOOP_END) {
 265     if (BundleSize == 0)
 266       HexagonMCInstrInfo::setInnerLoop(MCB);
 267     else if (BundleSize == 1)
 268       HexagonMCInstrInfo::setOuterLoop(MCB);
 269     else
 270       return DecodeStatus::Fail;
 271   }
 272
 273   DecodeStatus Result = DecodeStatus::Success;
 274   if ((Instruction & HexagonII::INST_PARSE_MASK) ==
 275       HexagonII::INST_PARSE_DUPLEX) {
 276     // Determine the instruction class of each instruction in the duplex.
 277     unsigned duplexIClass, IClassLow, IClassHigh;
 278
 279     duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
 280     switch (duplexIClass) {
 281     default:
 282       return MCDisassembler::Fail;
 283     case 0:
 284       IClassLow = HexagonII::HSIG_L1;
 285       IClassHigh = HexagonII::HSIG_L1;
 286       break;
 287     case 1:
 288       IClassLow = HexagonII::HSIG_L2;
 289       IClassHigh = HexagonII::HSIG_L1;
 290       break;
 291     case 2:
 292       IClassLow = HexagonII::HSIG_L2;
 293       IClassHigh = HexagonII::HSIG_L2;
 294       break;
 295     case 3:
 296       IClassLow = HexagonII::HSIG_A;
 297       IClassHigh = HexagonII::HSIG_A;
 298       break;
 299     case 4:
 300       IClassLow = HexagonII::HSIG_L1;
 301       IClassHigh = HexagonII::HSIG_A;
 302       break;
 303     case 5:
 304       IClassLow = HexagonII::HSIG_L2;
 305       IClassHigh = HexagonII::HSIG_A;
 306       break;
 307     case 6:
 308       IClassLow = HexagonII::HSIG_S1;
 309       IClassHigh = HexagonII::HSIG_A;
 310       break;
 311     case 7:
 312       IClassLow = HexagonII::HSIG_S2;
 313       IClassHigh = HexagonII::HSIG_A;
 314       break;
 315     case 8:
 316       IClassLow = HexagonII::HSIG_S1;
 317       IClassHigh = HexagonII::HSIG_L1;
 318       break;
 319     case 9:
 320       IClassLow = HexagonII::HSIG_S1;
 321       IClassHigh = HexagonII::HSIG_L2;
 322       break;
 323     case 10:
 324       IClassLow = HexagonII::HSIG_S1;
 325       IClassHigh = HexagonII::HSIG_S1;
 326       break;
 327     case 11:
 328       IClassLow = HexagonII::HSIG_S2;
 329       IClassHigh = HexagonII::HSIG_S1;
 330       break;
 331     case 12:
 332       IClassLow = HexagonII::HSIG_S2;
 333       IClassHigh = HexagonII::HSIG_L1;
 334       break;
 335     case 13:
 336       IClassLow = HexagonII::HSIG_S2;
 337       IClassHigh = HexagonII::HSIG_L2;
 338       break;
 339     case 14:
 340       IClassLow = HexagonII::HSIG_S2;
 341       IClassHigh = HexagonII::HSIG_S2;
 342       break;
 343     }
 344
 345     // Set the MCInst to be a duplex instruction. Which one doesn't matter.
 346     MI.setOpcode(Hexagon::DuplexIClass0);
 347
 348     // Decode each instruction in the duplex.
 349     // Create an MCInst for each instruction.
 350     unsigned instLow = Instruction & 0x1fff;
 351     unsigned instHigh = (Instruction >> 16) & 0x1fff;
 352     unsigned opLow;
 353     if (GetSubinstOpcode(IClassLow, instLow, opLow, os) !=
 354         MCDisassembler::Success)
 355       return MCDisassembler::Fail;
 356     unsigned opHigh;
 357     if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) !=
 358         MCDisassembler::Success)
 359       return MCDisassembler::Fail;
 360     MCInst *MILow = new (getContext()) MCInst;
 361     MILow->setOpcode(opLow);
 362     MCInst *MIHigh = new (getContext()) MCInst;
 363     MIHigh->setOpcode(opHigh);
 364     AddSubinstOperands(MILow, opLow, instLow);
 365     AddSubinstOperands(MIHigh, opHigh, instHigh);
 366     // see ConvertToSubInst() in
 367     // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
 368
 369     // Add the duplex instruction MCInsts as operands to the passed in MCInst.
 370     MCOperand OPLow = MCOperand::createInst(MILow);
 371     MCOperand OPHigh = MCOperand::createInst(MIHigh);
 372     MI.addOperand(OPLow);
 373     MI.addOperand(OPHigh);
 374     Complete = true;
 375   } else {
 376     if ((Instruction & HexagonII::INST_PARSE_MASK) ==
 377         HexagonII::INST_PARSE_PACKET_END)
 378       Complete = true;
 379     // Calling the auto-generated decoder function.
 380     Result =
 381         decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);
 382   }
 383
 384   return Result;
 385 }
 386
 387 static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp,
 388                                   uint64_t /*Address*/, const void *Decoder) {
 389   uint64_t imm = SignExtend64<16>(tmp);
 390   MI.addOperand(MCOperand::createImm(imm));
 391   return MCDisassembler::Success;
 392 }
 393
 394 static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp,
 395                                   uint64_t /*Address*/, const void *Decoder) {
 396   uint64_t imm = SignExtend64<12>(tmp);
 397   MI.addOperand(MCOperand::createImm(imm));
 398   return MCDisassembler::Success;
 399 }
 400
 401 static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp,
 402                                     uint64_t /*Address*/, const void *Decoder) {
 403   uint64_t imm = SignExtend64<11>(tmp);
 404   MI.addOperand(MCOperand::createImm(imm));
 405   return MCDisassembler::Success;
 406 }
 407
 408 static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp,
 409                                     uint64_t /*Address*/, const void *Decoder) {
 410   uint64_t imm = SignExtend64<12>(tmp);
 411   MI.addOperand(MCOperand::createImm(imm));
 412   return MCDisassembler::Success;
 413 }
 414
 415 static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp,
 416                                     uint64_t /*Address*/, const void *Decoder) {
 417   uint64_t imm = SignExtend64<13>(tmp);
 418   MI.addOperand(MCOperand::createImm(imm));
 419   return MCDisassembler::Success;
 420 }
 421
 422 static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp,
 423                                     uint64_t /*Address*/, const void *Decoder) {
 424   uint64_t imm = SignExtend64<14>(tmp);
 425   MI.addOperand(MCOperand::createImm(imm));
 426   return MCDisassembler::Success;
 427 }
 428
 429 static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp,
 430                                   uint64_t /*Address*/, const void *Decoder) {
 431   uint64_t imm = SignExtend64<10>(tmp);
 432   MI.addOperand(MCOperand::createImm(imm));
 433   return MCDisassembler::Success;
 434 }
 435
 436 static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/,
 437                                  const void *Decoder) {
 438   uint64_t imm = SignExtend64<8>(tmp);
 439   MI.addOperand(MCOperand::createImm(imm));
 440   return MCDisassembler::Success;
 441 }
 442
 443 static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp,
 444                                    uint64_t /*Address*/, const void *Decoder) {
 445   uint64_t imm = SignExtend64<6>(tmp);
 446   MI.addOperand(MCOperand::createImm(imm));
 447   return MCDisassembler::Success;
 448 }
 449
 450 static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp,
 451                                    uint64_t /*Address*/, const void *Decoder) {
 452   uint64_t imm = SignExtend64<4>(tmp);
 453   MI.addOperand(MCOperand::createImm(imm));
 454   return MCDisassembler::Success;
 455 }
 456
 457 static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp,
 458                                    uint64_t /*Address*/, const void *Decoder) {
 459   uint64_t imm = SignExtend64<5>(tmp);
 460   MI.addOperand(MCOperand::createImm(imm));
 461   return MCDisassembler::Success;
 462 }
 463
 464 static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp,
 465                                    uint64_t /*Address*/, const void *Decoder) {
 466   uint64_t imm = SignExtend64<6>(tmp);
 467   MI.addOperand(MCOperand::createImm(imm));
 468   return MCDisassembler::Success;
 469 }
 470
 471 static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp,
 472                                    uint64_t /*Address*/, const void *Decoder) {
 473   uint64_t imm = SignExtend64<7>(tmp);
 474   MI.addOperand(MCOperand::createImm(imm));
 475   return MCDisassembler::Success;
 476 }
 477
 478 // These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
 479 enum subInstBinaryValues {
 480   V4_SA1_addi_BITS = 0x0000,
 481   V4_SA1_addi_MASK = 0x1800,
 482   V4_SA1_addrx_BITS = 0x1800,
 483   V4_SA1_addrx_MASK = 0x1f00,
 484   V4_SA1_addsp_BITS = 0x0c00,
 485   V4_SA1_addsp_MASK = 0x1c00,
 486   V4_SA1_and1_BITS = 0x1200,
 487   V4_SA1_and1_MASK = 0x1f00,
 488   V4_SA1_clrf_BITS = 0x1a70,
 489   V4_SA1_clrf_MASK = 0x1e70,
 490   V4_SA1_clrfnew_BITS = 0x1a50,
 491   V4_SA1_clrfnew_MASK = 0x1e70,
 492   V4_SA1_clrt_BITS = 0x1a60,
 493   V4_SA1_clrt_MASK = 0x1e70,
 494   V4_SA1_clrtnew_BITS = 0x1a40,
 495   V4_SA1_clrtnew_MASK = 0x1e70,
 496   V4_SA1_cmpeqi_BITS = 0x1900,
 497   V4_SA1_cmpeqi_MASK = 0x1f00,
 498   V4_SA1_combine0i_BITS = 0x1c00,
 499   V4_SA1_combine0i_MASK = 0x1d18,
 500   V4_SA1_combine1i_BITS = 0x1c08,
 501   V4_SA1_combine1i_MASK = 0x1d18,
 502   V4_SA1_combine2i_BITS = 0x1c10,
 503   V4_SA1_combine2i_MASK = 0x1d18,
 504   V4_SA1_combine3i_BITS = 0x1c18,
 505   V4_SA1_combine3i_MASK = 0x1d18,
 506   V4_SA1_combinerz_BITS = 0x1d08,
 507   V4_SA1_combinerz_MASK = 0x1d08,
 508   V4_SA1_combinezr_BITS = 0x1d00,
 509   V4_SA1_combinezr_MASK = 0x1d08,
 510   V4_SA1_dec_BITS = 0x1300,
 511   V4_SA1_dec_MASK = 0x1f00,
 512   V4_SA1_inc_BITS = 0x1100,
 513   V4_SA1_inc_MASK = 0x1f00,
 514   V4_SA1_seti_BITS = 0x0800,
 515   V4_SA1_seti_MASK = 0x1c00,
 516   V4_SA1_setin1_BITS = 0x1a00,
 517   V4_SA1_setin1_MASK = 0x1e40,
 518   V4_SA1_sxtb_BITS = 0x1500,
 519   V4_SA1_sxtb_MASK = 0x1f00,
 520   V4_SA1_sxth_BITS = 0x1400,
 521   V4_SA1_sxth_MASK = 0x1f00,
 522   V4_SA1_tfr_BITS = 0x1000,
 523   V4_SA1_tfr_MASK = 0x1f00,
 524   V4_SA1_zxtb_BITS = 0x1700,
 525   V4_SA1_zxtb_MASK = 0x1f00,
 526   V4_SA1_zxth_BITS = 0x1600,
 527   V4_SA1_zxth_MASK = 0x1f00,
 528   V4_SL1_loadri_io_BITS = 0x0000,
 529   V4_SL1_loadri_io_MASK = 0x1000,
 530   V4_SL1_loadrub_io_BITS = 0x1000,
 531   V4_SL1_loadrub_io_MASK = 0x1000,
 532   V4_SL2_deallocframe_BITS = 0x1f00,
 533   V4_SL2_deallocframe_MASK = 0x1fc0,
 534   V4_SL2_jumpr31_BITS = 0x1fc0,
 535   V4_SL2_jumpr31_MASK = 0x1fc4,
 536   V4_SL2_jumpr31_f_BITS = 0x1fc5,
 537   V4_SL2_jumpr31_f_MASK = 0x1fc7,
 538   V4_SL2_jumpr31_fnew_BITS = 0x1fc7,
 539   V4_SL2_jumpr31_fnew_MASK = 0x1fc7,
 540   V4_SL2_jumpr31_t_BITS = 0x1fc4,
 541   V4_SL2_jumpr31_t_MASK = 0x1fc7,
 542   V4_SL2_jumpr31_tnew_BITS = 0x1fc6,
 543   V4_SL2_jumpr31_tnew_MASK = 0x1fc7,
 544   V4_SL2_loadrb_io_BITS = 0x1000,
 545   V4_SL2_loadrb_io_MASK = 0x1800,
 546   V4_SL2_loadrd_sp_BITS = 0x1e00,
 547   V4_SL2_loadrd_sp_MASK = 0x1f00,
 548   V4_SL2_loadrh_io_BITS = 0x0000,
 549   V4_SL2_loadrh_io_MASK = 0x1800,
 550   V4_SL2_loadri_sp_BITS = 0x1c00,
 551   V4_SL2_loadri_sp_MASK = 0x1e00,
 552   V4_SL2_loadruh_io_BITS = 0x0800,
 553   V4_SL2_loadruh_io_MASK = 0x1800,
 554   V4_SL2_return_BITS = 0x1f40,
 555   V4_SL2_return_MASK = 0x1fc4,
 556   V4_SL2_return_f_BITS = 0x1f45,
 557   V4_SL2_return_f_MASK = 0x1fc7,
 558   V4_SL2_return_fnew_BITS = 0x1f47,
 559   V4_SL2_return_fnew_MASK = 0x1fc7,
 560   V4_SL2_return_t_BITS = 0x1f44,
 561   V4_SL2_return_t_MASK = 0x1fc7,
 562   V4_SL2_return_tnew_BITS = 0x1f46,
 563   V4_SL2_return_tnew_MASK = 0x1fc7,
 564   V4_SS1_storeb_io_BITS = 0x1000,
 565   V4_SS1_storeb_io_MASK = 0x1000,
 566   V4_SS1_storew_io_BITS = 0x0000,
 567   V4_SS1_storew_io_MASK = 0x1000,
 568   V4_SS2_allocframe_BITS = 0x1c00,
 569   V4_SS2_allocframe_MASK = 0x1e00,
 570   V4_SS2_storebi0_BITS = 0x1200,
 571   V4_SS2_storebi0_MASK = 0x1f00,
 572   V4_SS2_storebi1_BITS = 0x1300,
 573   V4_SS2_storebi1_MASK = 0x1f00,
 574   V4_SS2_stored_sp_BITS = 0x0a00,
 575   V4_SS2_stored_sp_MASK = 0x1e00,
 576   V4_SS2_storeh_io_BITS = 0x0000,
 577   V4_SS2_storeh_io_MASK = 0x1800,
 578   V4_SS2_storew_sp_BITS = 0x0800,
 579   V4_SS2_storew_sp_MASK = 0x1e00,
 580   V4_SS2_storewi0_BITS = 0x1000,
 581   V4_SS2_storewi0_MASK = 0x1f00,
 582   V4_SS2_storewi1_BITS = 0x1100,
 583   V4_SS2_storewi1_MASK = 0x1f00
 584 };
 585
 586 static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
 587                                  raw_ostream &os) {
 588   switch (IClass) {
 589   case HexagonII::HSIG_L1:
 590     if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS)
 591       op = Hexagon::V4_SL1_loadri_io;
 592     else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS)
 593       op = Hexagon::V4_SL1_loadrub_io;
 594     else {
 595       os << "<unknown subinstruction>";
 596       return MCDisassembler::Fail;
 597     }
 598     break;
 599   case HexagonII::HSIG_L2:
 600     if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS)
 601       op = Hexagon::V4_SL2_deallocframe;
 602     else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS)
 603       op = Hexagon::V4_SL2_jumpr31;
 604     else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS)
 605       op = Hexagon::V4_SL2_jumpr31_f;
 606     else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS)
 607       op = Hexagon::V4_SL2_jumpr31_fnew;
 608     else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS)
 609       op = Hexagon::V4_SL2_jumpr31_t;
 610     else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS)
 611       op = Hexagon::V4_SL2_jumpr31_tnew;
 612     else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS)
 613       op = Hexagon::V4_SL2_loadrb_io;
 614     else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS)
 615       op = Hexagon::V4_SL2_loadrd_sp;
 616     else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS)
 617       op = Hexagon::V4_SL2_loadrh_io;
 618     else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS)
 619       op = Hexagon::V4_SL2_loadri_sp;
 620     else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS)
 621       op = Hexagon::V4_SL2_loadruh_io;
 622     else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS)
 623       op = Hexagon::V4_SL2_return;
 624     else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS)
 625       op = Hexagon::V4_SL2_return_f;
 626     else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS)
 627       op = Hexagon::V4_SL2_return_fnew;
 628     else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS)
 629       op = Hexagon::V4_SL2_return_t;
 630     else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS)
 631       op = Hexagon::V4_SL2_return_tnew;
 632     else {
 633       os << "<unknown subinstruction>";
 634       return MCDisassembler::Fail;
 635     }
 636     break;
 637   case HexagonII::HSIG_A:
 638     if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS)
 639       op = Hexagon::V4_SA1_addi;
 640     else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS)
 641       op = Hexagon::V4_SA1_addrx;
 642     else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS)
 643       op = Hexagon::V4_SA1_addsp;
 644     else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS)
 645       op = Hexagon::V4_SA1_and1;
 646     else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS)
 647       op = Hexagon::V4_SA1_clrf;
 648     else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS)
 649       op = Hexagon::V4_SA1_clrfnew;
 650     else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS)
 651       op = Hexagon::V4_SA1_clrt;
 652     else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS)
 653       op = Hexagon::V4_SA1_clrtnew;
 654     else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS)
 655       op = Hexagon::V4_SA1_cmpeqi;
 656     else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS)
 657       op = Hexagon::V4_SA1_combine0i;
 658     else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS)
 659       op = Hexagon::V4_SA1_combine1i;
 660     else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS)
 661       op = Hexagon::V4_SA1_combine2i;
 662     else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS)
 663       op = Hexagon::V4_SA1_combine3i;
 664     else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS)
 665       op = Hexagon::V4_SA1_combinerz;
 666     else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS)
 667       op = Hexagon::V4_SA1_combinezr;
 668     else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS)
 669       op = Hexagon::V4_SA1_dec;
 670     else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS)
 671       op = Hexagon::V4_SA1_inc;
 672     else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS)
 673       op = Hexagon::V4_SA1_seti;
 674     else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS)
 675       op = Hexagon::V4_SA1_setin1;
 676     else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS)
 677       op = Hexagon::V4_SA1_sxtb;
 678     else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS)
 679       op = Hexagon::V4_SA1_sxth;
 680     else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS)
 681       op = Hexagon::V4_SA1_tfr;
 682     else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS)
 683       op = Hexagon::V4_SA1_zxtb;
 684     else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS)
 685       op = Hexagon::V4_SA1_zxth;
 686     else {
 687       os << "<unknown subinstruction>";
 688       return MCDisassembler::Fail;
 689     }
 690     break;
 691   case HexagonII::HSIG_S1:
 692     if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS)
 693       op = Hexagon::V4_SS1_storeb_io;
 694     else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS)
 695       op = Hexagon::V4_SS1_storew_io;
 696     else {
 697       os << "<unknown subinstruction>";
 698       return MCDisassembler::Fail;
 699     }
 700     break;
 701   case HexagonII::HSIG_S2:
 702     if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS)
 703       op = Hexagon::V4_SS2_allocframe;
 704     else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS)
 705       op = Hexagon::V4_SS2_storebi0;
 706     else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS)
 707       op = Hexagon::V4_SS2_storebi1;
 708     else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS)
 709       op = Hexagon::V4_SS2_stored_sp;
 710     else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS)
 711       op = Hexagon::V4_SS2_storeh_io;
 712     else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS)
 713       op = Hexagon::V4_SS2_storew_sp;
 714     else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS)
 715       op = Hexagon::V4_SS2_storewi0;
 716     else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS)
 717       op = Hexagon::V4_SS2_storewi1;
 718     else {
 719       os << "<unknown subinstruction>";
 720       return MCDisassembler::Fail;
 721     }
 722     break;
 723   default:
 724     os << "<unknown>";
 725     return MCDisassembler::Fail;
 726   }
 727   return MCDisassembler::Success;
 728 }
 729
 730 static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) {
 731   if (encoded_reg < 8)
 732     return Hexagon::R0 + encoded_reg;
 733   else if (encoded_reg < 16)
 734     return Hexagon::R0 + encoded_reg + 8;
 735   return Hexagon::NoRegister;
 736 }
 737
 738 static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) {
 739   if (encoded_dreg < 4)
 740     return Hexagon::D0 + encoded_dreg;
 741   else if (encoded_dreg < 8)
 742     return Hexagon::D0 + encoded_dreg + 4;
 743   return Hexagon::NoRegister;
 744 }
 745
 746 static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) {
 747   int64_t operand;
 748   MCOperand Op;
 749   switch (opcode) {
 750   case Hexagon::V4_SL2_deallocframe:
 751   case Hexagon::V4_SL2_jumpr31:
 752   case Hexagon::V4_SL2_jumpr31_f:
 753   case Hexagon::V4_SL2_jumpr31_fnew:
 754   case Hexagon::V4_SL2_jumpr31_t:
 755   case Hexagon::V4_SL2_jumpr31_tnew:
 756   case Hexagon::V4_SL2_return:
 757   case Hexagon::V4_SL2_return_f:
 758   case Hexagon::V4_SL2_return_fnew:
 759   case Hexagon::V4_SL2_return_t:
 760   case Hexagon::V4_SL2_return_tnew:
 761     // no operands for these instructions
 762     break;
 763   case Hexagon::V4_SS2_allocframe:
 764     // u 8-4{5_3}
 765     operand = ((inst & 0x1f0) >> 4) << 3;
 766     Op = MCOperand::createImm(operand);
 767     MI->addOperand(Op);
 768     break;
 769   case Hexagon::V4_SL1_loadri_io:
 770     // Rd 3-0, Rs 7-4, u 11-8{4_2}
 771     operand = getRegFromSubinstEncoding(inst & 0xf);
 772     Op = MCOperand::createReg(operand);
 773     MI->addOperand(Op);
 774     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 775     Op = MCOperand::createReg(operand);
 776     MI->addOperand(Op);
 777     operand = (inst & 0xf00) >> 6;
 778     Op = MCOperand::createImm(operand);
 779     MI->addOperand(Op);
 780     break;
 781   case Hexagon::V4_SL1_loadrub_io:
 782     // Rd 3-0, Rs 7-4, u 11-8
 783     operand = getRegFromSubinstEncoding(inst & 0xf);
 784     Op = MCOperand::createReg(operand);
 785     MI->addOperand(Op);
 786     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 787     Op = MCOperand::createReg(operand);
 788     MI->addOperand(Op);
 789     operand = (inst & 0xf00) >> 8;
 790     Op = MCOperand::createImm(operand);
 791     MI->addOperand(Op);
 792     break;
 793   case Hexagon::V4_SL2_loadrb_io:
 794     // Rd 3-0, Rs 7-4, u 10-8
 795     operand = getRegFromSubinstEncoding(inst & 0xf);
 796     Op = MCOperand::createReg(operand);
 797     MI->addOperand(Op);
 798     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 799     Op = MCOperand::createReg(operand);
 800     MI->addOperand(Op);
 801     operand = (inst & 0x700) >> 8;
 802     Op = MCOperand::createImm(operand);
 803     MI->addOperand(Op);
 804     break;
 805   case Hexagon::V4_SL2_loadrh_io:
 806   case Hexagon::V4_SL2_loadruh_io:
 807     // Rd 3-0, Rs 7-4, u 10-8{3_1}
 808     operand = getRegFromSubinstEncoding(inst & 0xf);
 809     Op = MCOperand::createReg(operand);
 810     MI->addOperand(Op);
 811     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 812     Op = MCOperand::createReg(operand);
 813     MI->addOperand(Op);
 814     operand = ((inst & 0x700) >> 8) << 1;
 815     Op = MCOperand::createImm(operand);
 816     MI->addOperand(Op);
 817     break;
 818   case Hexagon::V4_SL2_loadrd_sp:
 819     // Rdd 2-0, u 7-3{5_3}
 820     operand = getDRegFromSubinstEncoding(inst & 0x7);
 821     Op = MCOperand::createReg(operand);
 822     MI->addOperand(Op);
 823     operand = ((inst & 0x0f8) >> 3) << 3;
 824     Op = MCOperand::createImm(operand);
 825     MI->addOperand(Op);
 826     break;
 827   case Hexagon::V4_SL2_loadri_sp:
 828     // Rd 3-0, u 8-4{5_2}
 829     operand = getRegFromSubinstEncoding(inst & 0xf);
 830     Op = MCOperand::createReg(operand);
 831     MI->addOperand(Op);
 832     operand = ((inst & 0x1f0) >> 4) << 2;
 833     Op = MCOperand::createImm(operand);
 834     MI->addOperand(Op);
 835     break;
 836   case Hexagon::V4_SA1_addi:
 837     // Rx 3-0 (x2), s7 10-4
 838     operand = getRegFromSubinstEncoding(inst & 0xf);
 839     Op = MCOperand::createReg(operand);
 840     MI->addOperand(Op);
 841     MI->addOperand(Op);
 842     operand = SignExtend64<7>((inst & 0x7f0) >> 4);
 843     Op = MCOperand::createImm(operand);
 844     MI->addOperand(Op);
 845     break;
 846   case Hexagon::V4_SA1_addrx:
 847     // Rx 3-0 (x2), Rs 7-4
 848     operand = getRegFromSubinstEncoding(inst & 0xf);
 849     Op = MCOperand::createReg(operand);
 850     MI->addOperand(Op);
 851     MI->addOperand(Op);
 852     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 853     Op = MCOperand::createReg(operand);
 854     MI->addOperand(Op);
 855   case Hexagon::V4_SA1_and1:
 856   case Hexagon::V4_SA1_dec:
 857   case Hexagon::V4_SA1_inc:
 858   case Hexagon::V4_SA1_sxtb:
 859   case Hexagon::V4_SA1_sxth:
 860   case Hexagon::V4_SA1_tfr:
 861   case Hexagon::V4_SA1_zxtb:
 862   case Hexagon::V4_SA1_zxth:
 863     // Rd 3-0, Rs 7-4
 864     operand = getRegFromSubinstEncoding(inst & 0xf);
 865     Op = MCOperand::createReg(operand);
 866     MI->addOperand(Op);
 867     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 868     Op = MCOperand::createReg(operand);
 869     MI->addOperand(Op);
 870     break;
 871   case Hexagon::V4_SA1_addsp:
 872     // Rd 3-0, u 9-4{6_2}
 873     operand = getRegFromSubinstEncoding(inst & 0xf);
 874     Op = MCOperand::createReg(operand);
 875     MI->addOperand(Op);
 876     operand = ((inst & 0x3f0) >> 4) << 2;
 877     Op = MCOperand::createImm(operand);
 878     MI->addOperand(Op);
 879     break;
 880   case Hexagon::V4_SA1_seti:
 881     // Rd 3-0, u 9-4
 882     operand = getRegFromSubinstEncoding(inst & 0xf);
 883     Op = MCOperand::createReg(operand);
 884     MI->addOperand(Op);
 885     operand = (inst & 0x3f0) >> 4;
 886     Op = MCOperand::createImm(operand);
 887     MI->addOperand(Op);
 888     break;
 889   case Hexagon::V4_SA1_clrf:
 890   case Hexagon::V4_SA1_clrfnew:
 891   case Hexagon::V4_SA1_clrt:
 892   case Hexagon::V4_SA1_clrtnew:
 893   case Hexagon::V4_SA1_setin1:
 894     // Rd 3-0
 895     operand = getRegFromSubinstEncoding(inst & 0xf);
 896     Op = MCOperand::createReg(operand);
 897     MI->addOperand(Op);
 898     break;
 899   case Hexagon::V4_SA1_cmpeqi:
 900     // Rs 7-4, u 1-0
 901     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 902     Op = MCOperand::createReg(operand);
 903     MI->addOperand(Op);
 904     operand = inst & 0x3;
 905     Op = MCOperand::createImm(operand);
 906     MI->addOperand(Op);
 907     break;
 908   case Hexagon::V4_SA1_combine0i:
 909   case Hexagon::V4_SA1_combine1i:
 910   case Hexagon::V4_SA1_combine2i:
 911   case Hexagon::V4_SA1_combine3i:
 912     // Rdd 2-0, u 6-5
 913     operand = getDRegFromSubinstEncoding(inst & 0x7);
 914     Op = MCOperand::createReg(operand);
 915     MI->addOperand(Op);
 916     operand = (inst & 0x060) >> 5;
 917     Op = MCOperand::createImm(operand);
 918     MI->addOperand(Op);
 919     break;
 920   case Hexagon::V4_SA1_combinerz:
 921   case Hexagon::V4_SA1_combinezr:
 922     // Rdd 2-0, Rs 7-4
 923     operand = getDRegFromSubinstEncoding(inst & 0x7);
 924     Op = MCOperand::createReg(operand);
 925     MI->addOperand(Op);
 926     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 927     Op = MCOperand::createReg(operand);
 928     MI->addOperand(Op);
 929     break;
 930   case Hexagon::V4_SS1_storeb_io:
 931     // Rs 7-4, u 11-8, Rt 3-0
 932     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 933     Op = MCOperand::createReg(operand);
 934     MI->addOperand(Op);
 935     operand = (inst & 0xf00) >> 8;
 936     Op = MCOperand::createImm(operand);
 937     MI->addOperand(Op);
 938     operand = getRegFromSubinstEncoding(inst & 0xf);
 939     Op = MCOperand::createReg(operand);
 940     MI->addOperand(Op);
 941     break;
 942   case Hexagon::V4_SS1_storew_io:
 943     // Rs 7-4, u 11-8{4_2}, Rt 3-0
 944     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 945     Op = MCOperand::createReg(operand);
 946     MI->addOperand(Op);
 947     operand = ((inst & 0xf00) >> 8) << 2;
 948     Op = MCOperand::createImm(operand);
 949     MI->addOperand(Op);
 950     operand = getRegFromSubinstEncoding(inst & 0xf);
 951     Op = MCOperand::createReg(operand);
 952     MI->addOperand(Op);
 953     break;
 954   case Hexagon::V4_SS2_storebi0:
 955   case Hexagon::V4_SS2_storebi1:
 956     // Rs 7-4, u 3-0
 957     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 958     Op = MCOperand::createReg(operand);
 959     MI->addOperand(Op);
 960     operand = inst & 0xf;
 961     Op = MCOperand::createImm(operand);
 962     MI->addOperand(Op);
 963     break;
 964   case Hexagon::V4_SS2_storewi0:
 965   case Hexagon::V4_SS2_storewi1:
 966     // Rs 7-4, u 3-0{4_2}
 967     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 968     Op = MCOperand::createReg(operand);
 969     MI->addOperand(Op);
 970     operand = (inst & 0xf) << 2;
 971     Op = MCOperand::createImm(operand);
 972     MI->addOperand(Op);
 973     break;
 974   case Hexagon::V4_SS2_stored_sp:
 975     // s 8-3{6_3}, Rtt 2-0
 976     operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
 977     Op = MCOperand::createImm(operand);
 978     MI->addOperand(Op);
 979     operand = getDRegFromSubinstEncoding(inst & 0x7);
 980     Op = MCOperand::createReg(operand);
 981     MI->addOperand(Op);
 982   case Hexagon::V4_SS2_storeh_io:
 983     // Rs 7-4, u 10-8{3_1}, Rt 3-0
 984     operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
 985     Op = MCOperand::createReg(operand);
 986     MI->addOperand(Op);
 987     operand = ((inst & 0x700) >> 8) << 1;
 988     Op = MCOperand::createImm(operand);
 989     MI->addOperand(Op);
 990     operand = getRegFromSubinstEncoding(inst & 0xf);
 991     Op = MCOperand::createReg(operand);
 992     MI->addOperand(Op);
 993     break;
 994   case Hexagon::V4_SS2_storew_sp:
 995     // u 8-4{5_2}, Rd 3-0
 996     operand = ((inst & 0x1f0) >> 4) << 2;
 997     Op = MCOperand::createImm(operand);
 998     MI->addOperand(Op);
 999     operand = getRegFromSubinstEncoding(inst & 0xf);
1000     Op = MCOperand::createReg(operand);
1001     MI->addOperand(Op);
1002     break;
1003   default:
1004     // don't crash with an invalid subinstruction
1005     // llvm_unreachable("Invalid subinstruction in duplex instruction");
1006     break;
1007   }
1008 }