1 //===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/HexagonBaseInfo.h"
11 #include "MCTargetDesc/HexagonMCTargetDesc.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCDisassembler.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/Endian.h"
32 #define DEBUG_TYPE "hexagon-disassembler"
34 // Pull DecodeStatus and its enum values into the global namespace.
35 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
38 /// \brief Hexagon disassembler for all Hexagon platforms.
39 class HexagonDisassembler : public MCDisassembler {
41 HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
42 : MCDisassembler(STI, Ctx) {}
44 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
45 ArrayRef<uint8_t> Bytes, uint64_t Address,
47 raw_ostream &CStream) const override;
51 static const uint16_t IntRegDecoderTable[] = {
52 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
53 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
54 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
55 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
56 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
57 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
58 Hexagon::R30, Hexagon::R31 };
60 static const uint16_t PredRegDecoderTable[] = { Hexagon::P0, Hexagon::P1,
61 Hexagon::P2, Hexagon::P3 };
63 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
65 void const *Decoder) {
67 return MCDisassembler::Fail;
69 unsigned Register = IntRegDecoderTable[RegNo];
70 Inst.addOperand(MCOperand::CreateReg(Register));
71 return MCDisassembler::Success;
74 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
76 void const *Decoder) {
78 return MCDisassembler::Fail;
80 unsigned Register = PredRegDecoderTable[RegNo];
81 Inst.addOperand(MCOperand::CreateReg(Register));
82 return MCDisassembler::Success;
85 #include "HexagonGenDisassemblerTables.inc"
87 static MCDisassembler *createHexagonDisassembler(Target const &T,
88 MCSubtargetInfo const &STI,
90 return new HexagonDisassembler(STI, Ctx);
93 extern "C" void LLVMInitializeHexagonDisassembler() {
94 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget,
95 createHexagonDisassembler);
98 DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
99 ArrayRef<uint8_t> Bytes,
102 raw_ostream &cs) const {
104 if (Bytes.size() < 4)
105 return MCDisassembler::Fail;
108 llvm::support::endian::read<uint32_t, llvm::support::little,
109 llvm::support::unaligned>(Bytes.data());
111 // Remove parse bits.
112 insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);
113 return decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);