1 //===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This is the top level entry point for the Hexagon target.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Target-independent interfaces which we are implementing
16 //===----------------------------------------------------------------------===//
18 include "llvm/Target/Target.td"
20 //===----------------------------------------------------------------------===//
21 // Hexagon Subtarget features.
22 //===----------------------------------------------------------------------===//
24 // Hexagon Archtectures
25 def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2",
27 def ArchV3 : SubtargetFeature<"v3", "HexagonArchVersion", "V3",
29 def ArchV4 : SubtargetFeature<"v4", "HexagonArchVersion", "V4",
31 def ArchV5 : SubtargetFeature<"v5", "HexagonArchVersion", "V5",
34 //===----------------------------------------------------------------------===//
35 // Register File, Calling Conv, Instruction Descriptions
36 //===----------------------------------------------------------------------===//
37 include "HexagonSchedule.td"
38 include "HexagonRegisterInfo.td"
39 include "HexagonCallingConv.td"
40 include "HexagonInstrInfo.td"
41 include "HexagonIntrinsics.td"
42 include "HexagonIntrinsicsDerived.td"
44 def HexagonInstrInfo : InstrInfo;
46 //===----------------------------------------------------------------------===//
47 // Hexagon processors supported.
48 //===----------------------------------------------------------------------===//
50 class Proc<string Name, SchedMachineModel Model,
51 list<SubtargetFeature> Features>
52 : ProcessorModel<Name, Model, Features>;
54 def : Proc<"hexagonv2", HexagonModel, [ArchV2]>;
55 def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>;
56 def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>;
57 def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
60 // Hexagon Uses the MC printer for assembler output, so make sure the TableGen
61 // AsmWriter bits get associated with the correct class.
62 def HexagonAsmWriter : AsmWriter {
63 string AsmWriterClassName = "InstPrinter";
64 bit isMCAsmWriter = 1;
67 //===----------------------------------------------------------------------===//
68 // Declare the target which we are implementing
69 //===----------------------------------------------------------------------===//
71 def Hexagon : Target {
72 // Pull in Instruction Info:
73 let InstructionSet = HexagonInstrInfo;
75 let AssemblyWriters = [HexagonAsmWriter];