1 //===--- HexagonBitTracker.cpp --------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/CodeGen/MachineRegisterInfo.h"
11 #include "llvm/IR/Module.h"
12 #include "llvm/Support/Debug.h"
13 #include "llvm/Support/raw_ostream.h"
16 #include "HexagonInstrInfo.h"
17 #include "HexagonRegisterInfo.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonBitTracker.h"
23 typedef BitTracker BT;
25 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
26 MachineRegisterInfo &mri,
27 const HexagonInstrInfo &tii,
29 : MachineEvaluator(tri, mri), MF(mf), MFI(*mf.getFrameInfo()), TII(tii) {
30 // Populate the VRX map (VR to extension-type).
31 // Go over all the formal parameters of the function. If a given parameter
32 // P is sign- or zero-extended, locate the virtual register holding that
33 // parameter and create an entry in the VRX map indicating the type of ex-
34 // tension (and the source type).
35 // This is a bit complicated to do accurately, since the memory layout in-
36 // formation is necessary to precisely determine whether an aggregate para-
37 // meter will be passed in a register or in memory. What is given in MRI
38 // is the association between the physical register that is live-in (i.e.
39 // holds an argument), and the virtual register that this value will be
40 // copied into. This, by itself, is not sufficient to map back the virtual
41 // register to a formal parameter from Function (since consecutive live-ins
42 // from MRI may not correspond to consecutive formal parameters from Func-
43 // tion). To avoid the complications with in-memory arguments, only consi-
44 // der the initial sequence of formal parameters that are known to be
45 // passed via registers.
47 unsigned InVirtReg, InPhysReg = 0;
48 const Function &F = *MF.getFunction();
49 typedef Function::const_arg_iterator arg_iterator;
50 for (arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
52 const Argument &Arg = *I;
53 Type *ATy = Arg.getType();
55 if (ATy->isIntegerTy())
56 Width = ATy->getIntegerBitWidth();
57 else if (ATy->isPointerTy())
59 // If pointer size is not set through target data, it will default to
60 // Module::AnyPointerSize.
61 if (Width == 0 || Width > 64)
63 InPhysReg = getNextPhysReg(InPhysReg, Width);
66 InVirtReg = getVirtRegFor(InPhysReg);
69 AttributeSet Attrs = F.getAttributes();
70 if (Attrs.hasAttribute(AttrIdx, Attribute::SExt))
71 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width)));
72 else if (Attrs.hasAttribute(AttrIdx, Attribute::ZExt))
73 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width)));
78 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
80 return MachineEvaluator::mask(Reg, 0);
81 using namespace Hexagon;
82 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
83 unsigned ID = RC->getID();
84 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
86 case DoubleRegsRegClassID:
87 return (Sub == subreg_loreg) ? BT::BitMask(0, RW-1)
88 : BT::BitMask(RW, 2*RW-1);
93 dbgs() << PrintReg(Reg, &TRI, Sub) << '\n';
95 llvm_unreachable("Unexpected register/subregister");
100 std::vector<BT::RegisterRef> Vector;
103 RegisterRefs(const MachineInstr *MI) : Vector(MI->getNumOperands()) {
104 for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
105 const MachineOperand &MO = MI->getOperand(i);
107 Vector[i] = BT::RegisterRef(MO);
108 // For indices that don't correspond to registers, the entry will
109 // remain constructed via the default constructor.
113 size_t size() const { return Vector.size(); }
114 const BT::RegisterRef &operator[](unsigned n) const {
115 // The main purpose of this operator is to assert with bad argument.
116 assert(n < Vector.size());
122 bool HexagonEvaluator::evaluate(const MachineInstr *MI,
123 const CellMapType &Inputs, CellMapType &Outputs) const {
124 unsigned NumDefs = 0;
126 // Sanity verification: there should not be any defs with subregisters.
127 for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
128 const MachineOperand &MO = MI->getOperand(i);
129 if (!MO.isReg() || !MO.isDef())
132 assert(MO.getSubReg() == 0);
139 return evaluateLoad(MI, Inputs, Outputs);
141 // Check COPY instructions that copy formal parameters into virtual
142 // registers. Such parameters can be sign- or zero-extended at the
143 // call site, and we should take advantage of this knowledge. The MRI
144 // keeps a list of pairs of live-in physical and virtual registers,
145 // which provides information about which virtual registers will hold
146 // the argument values. The function will still contain instructions
147 // defining those virtual registers, and in practice those are COPY
148 // instructions from a physical to a virtual register. In such cases,
149 // applying the argument extension to the virtual register can be seen
150 // as simply mirroring the extension that had already been applied to
151 // the physical register at the call site. If the defining instruction
152 // was not a COPY, it would not be clear how to mirror that extension
153 // on the callee's side. For that reason, only check COPY instructions
154 // for potential extensions.
156 if (evaluateFormalCopy(MI, Inputs, Outputs))
160 // Beyond this point, if any operand is a global, skip that instruction.
161 // The reason is that certain instructions that can take an immediate
162 // operand can also have a global symbol in that operand. To avoid
163 // checking what kind of operand a given instruction has individually
164 // for each instruction, do it here. Global symbols as operands gene-
165 // rally do not provide any useful information.
166 for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
167 const MachineOperand &MO = MI->getOperand(i);
168 if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
173 RegisterRefs Reg(MI);
174 unsigned Opc = MI->getOpcode();
175 using namespace Hexagon;
176 #define op(i) MI->getOperand(i)
177 #define rc(i) RegisterCell::ref(getCell(Reg[i],Inputs))
178 #define im(i) MI->getOperand(i).getImm()
180 // If the instruction has no register operands, skip it.
184 // Record result for register in operand 0.
185 auto rr0 = [this,Reg] (const BT::RegisterCell &Val, CellMapType &Outputs)
187 putCell(Reg[0], Val, Outputs);
190 // Get the cell corresponding to the N-th operand.
191 auto cop = [this,&Reg,&MI,&Inputs] (unsigned N, uint16_t W)
192 -> BT::RegisterCell {
193 const MachineOperand &Op = MI->getOperand(N);
195 return eIMM(Op.getImm(), W);
197 return RegisterCell::self(0, W);
198 assert(getRegBitWidth(Reg[N]) == W && "Register width mismatch");
201 // Extract RW low bits of the cell.
202 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
203 -> BT::RegisterCell {
204 assert(RW <= RC.width());
205 return eXTR(RC, 0, RW);
207 // Extract RW high bits of the cell.
208 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
209 -> BT::RegisterCell {
210 uint16_t W = RC.width();
212 return eXTR(RC, W-RW, W);
214 // Extract N-th halfword (counting from the least significant position).
215 auto half = [this] (const BT::RegisterCell &RC, unsigned N)
216 -> BT::RegisterCell {
217 assert(N*16+16 <= RC.width());
218 return eXTR(RC, N*16, N*16+16);
220 // Shuffle bits (pick even/odd from cells and merge into result).
221 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt,
222 uint16_t BW, bool Odd) -> BT::RegisterCell {
223 uint16_t I = Odd, Ws = Rs.width();
224 assert(Ws == Rt.width());
225 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW));
228 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW));
234 // The bitwidth of the 0th operand. In most (if not all) of the
235 // instructions below, the 0th operand is the defined register.
236 // Pre-compute the bitwidth here, because it is needed in many cases
238 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0;
241 // Transfer immediate:
246 case CONST32_Float_Real:
247 case CONST32_Int_Real:
248 case CONST64_Float_Real:
249 case CONST64_Int_Real:
250 return rr0(eIMM(im(1), W0), Outputs);
252 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs);
254 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs);
256 int FI = op(1).getIndex();
257 int Off = op(2).getImm();
258 unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
259 unsigned L = Log2_32(A);
260 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
261 RC.fill(0, L, BT::BitValue::Zero);
262 return rr0(RC, Outputs);
265 // Transfer register:
270 return rr0(rc(1), Outputs);
273 uint16_t PW = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
275 RegisterCell PC = eXTR(rc(1), 0, PW);
276 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1));
277 RC.fill(PW, RW, BT::BitValue::Zero);
278 return rr0(RC, Outputs);
281 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0);
282 W0 = 8; // XXX Pred size
283 return rr0(eINS(RC, eXTR(rc(1), 0, W0), 0), Outputs);
294 uint16_t W1 = getRegBitWidth(Reg[1]);
295 assert(W0 == 64 && W1 == 32);
296 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1));
297 RegisterCell RC = eADD(eSXT(CW, W1), rc(2));
298 return rr0(RC, Outputs);
302 return rr0(eADD(rc(1), rc(2)), Outputs);
304 return rr0(eADD(rc(1), eIMM(im(2), W0)), Outputs);
305 case S4_addi_asl_ri: {
306 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3)));
307 return rr0(RC, Outputs);
309 case S4_addi_lsr_ri: {
310 RegisterCell RC = eADD(eIMM(im(1), W0), eLSR(rc(2), im(3)));
311 return rr0(RC, Outputs);
314 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
315 return rr0(RC, Outputs);
317 case M4_mpyri_addi: {
318 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
319 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
320 return rr0(RC, Outputs);
322 case M4_mpyrr_addi: {
323 RegisterCell M = eMLS(rc(2), rc(3));
324 RegisterCell RC = eADD(eIMM(im(1), W0), lo(M, W0));
325 return rr0(RC, Outputs);
327 case M4_mpyri_addr_u2: {
328 RegisterCell M = eMLS(eIMM(im(2), W0), rc(3));
329 RegisterCell RC = eADD(rc(1), lo(M, W0));
330 return rr0(RC, Outputs);
332 case M4_mpyri_addr: {
333 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
334 RegisterCell RC = eADD(rc(1), lo(M, W0));
335 return rr0(RC, Outputs);
337 case M4_mpyrr_addr: {
338 RegisterCell M = eMLS(rc(2), rc(3));
339 RegisterCell RC = eADD(rc(1), lo(M, W0));
340 return rr0(RC, Outputs);
343 RegisterCell RC = eADD(rc(1), eSUB(eIMM(im(2), W0), rc(3)));
344 return rr0(RC, Outputs);
347 RegisterCell RC = eADD(rc(1), eADD(rc(2), eIMM(im(3), W0)));
348 return rr0(RC, Outputs);
351 RegisterCell RC = eADD(rc(1), eADD(rc(2), rc(3)));
352 return rr0(RC, Outputs);
355 RegisterCell RC = eADD(rc(1), eSUB(rc(2), rc(3)));
356 return rr0(RC, Outputs);
358 case S2_addasl_rrri: {
359 RegisterCell RC = eADD(rc(1), eASL(rc(2), im(3)));
360 return rr0(RC, Outputs);
363 RegisterCell RPC = RegisterCell::self(Reg[0].Reg, W0);
364 RPC.fill(0, 2, BT::BitValue::Zero);
365 return rr0(eADD(RPC, eIMM(im(2), W0)), Outputs);
369 return rr0(eSUB(rc(1), rc(2)), Outputs);
371 return rr0(eSUB(eIMM(im(1), W0), rc(2)), Outputs);
372 case S4_subi_asl_ri: {
373 RegisterCell RC = eSUB(eIMM(im(1), W0), eASL(rc(2), im(3)));
374 return rr0(RC, Outputs);
376 case S4_subi_lsr_ri: {
377 RegisterCell RC = eSUB(eIMM(im(1), W0), eLSR(rc(2), im(3)));
378 return rr0(RC, Outputs);
381 RegisterCell RC = eSUB(rc(1), eADD(rc(2), eIMM(im(3), W0)));
382 return rr0(RC, Outputs);
385 RegisterCell RC = eSUB(rc(1), eADD(rc(2), rc(3)));
386 return rr0(RC, Outputs);
388 // 32-bit negation is done by "Rd = A2_subri 0, Rs"
390 return rr0(eSUB(eIMM(0, W0), rc(1)), Outputs);
393 RegisterCell M = eMLS(rc(1), rc(2));
394 return rr0(hi(M, W0), Outputs);
397 return rr0(eMLS(rc(1), rc(2)), Outputs);
398 case M2_dpmpyss_acc_s0:
399 return rr0(eADD(rc(1), eMLS(rc(2), rc(3))), Outputs);
400 case M2_dpmpyss_nac_s0:
401 return rr0(eSUB(rc(1), eMLS(rc(2), rc(3))), Outputs);
403 RegisterCell M = eMLS(rc(1), rc(2));
404 return rr0(lo(M, W0), Outputs);
407 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
408 RegisterCell RC = eADD(rc(1), lo(M, W0));
409 return rr0(RC, Outputs);
412 RegisterCell M = eMLS(rc(2), eIMM(im(3), W0));
413 RegisterCell RC = eSUB(rc(1), lo(M, W0));
414 return rr0(RC, Outputs);
417 RegisterCell M = eMLS(rc(2), rc(3));
418 RegisterCell RC = eADD(rc(1), lo(M, W0));
419 return rr0(RC, Outputs);
422 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
423 return rr0(lo(M, 32), Outputs);
426 RegisterCell M = eMLS(rc(1), eIMM(-im(2), W0));
427 return rr0(lo(M, 32), Outputs);
430 RegisterCell M = eMLS(rc(1), eIMM(im(2), W0));
431 return rr0(lo(M, 32), Outputs);
434 RegisterCell M = eMLU(rc(1), rc(2));
435 return rr0(hi(M, W0), Outputs);
438 return rr0(eMLU(rc(1), rc(2)), Outputs);
439 case M2_dpmpyuu_acc_s0:
440 return rr0(eADD(rc(1), eMLU(rc(2), rc(3))), Outputs);
441 case M2_dpmpyuu_nac_s0:
442 return rr0(eSUB(rc(1), eMLU(rc(2), rc(3))), Outputs);
448 return rr0(eAND(rc(1), eIMM(im(2), W0)), Outputs);
451 return rr0(eAND(rc(1), rc(2)), Outputs);
454 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
455 case S4_andi_asl_ri: {
456 RegisterCell RC = eAND(eIMM(im(1), W0), eASL(rc(2), im(3)));
457 return rr0(RC, Outputs);
459 case S4_andi_lsr_ri: {
460 RegisterCell RC = eAND(eIMM(im(1), W0), eLSR(rc(2), im(3)));
461 return rr0(RC, Outputs);
464 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
466 return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
468 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
470 return rr0(eAND(rc(1), eXOR(rc(2), rc(3))), Outputs);
472 return rr0(eORL(rc(1), eIMM(im(2), W0)), Outputs);
475 return rr0(eORL(rc(1), rc(2)), Outputs);
478 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
479 case S4_ori_asl_ri: {
480 RegisterCell RC = eORL(eIMM(im(1), W0), eASL(rc(2), im(3)));
481 return rr0(RC, Outputs);
483 case S4_ori_lsr_ri: {
484 RegisterCell RC = eORL(eIMM(im(1), W0), eLSR(rc(2), im(3)));
485 return rr0(RC, Outputs);
488 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
490 return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
493 RegisterCell RC = eORL(rc(1), eAND(rc(2), eIMM(im(3), W0)));
494 return rr0(RC, Outputs);
497 RegisterCell RC = eORL(rc(1), eORL(rc(2), eIMM(im(3), W0)));
498 return rr0(RC, Outputs);
501 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
503 return rr0(eORL(rc(1), eXOR(rc(2), rc(3))), Outputs);
506 return rr0(eXOR(rc(1), rc(2)), Outputs);
508 return rr0(eXOR(rc(1), eAND(rc(2), rc(3))), Outputs);
510 return rr0(eXOR(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
512 return rr0(eXOR(rc(1), eORL(rc(2), rc(3))), Outputs);
514 return rr0(eXOR(rc(1), eXOR(rc(2), rc(3))), Outputs);
517 return rr0(eNOT(rc(1)), Outputs);
521 return rr0(eASL(rc(1), im(2)), Outputs);
523 return rr0(eASL(rc(1), 16), Outputs);
526 return rr0(eADD(rc(1), eASL(rc(2), im(3))), Outputs);
529 return rr0(eSUB(rc(1), eASL(rc(2), im(3))), Outputs);
532 return rr0(eAND(rc(1), eASL(rc(2), im(3))), Outputs);
535 return rr0(eORL(rc(1), eASL(rc(2), im(3))), Outputs);
536 case S2_asl_i_r_xacc:
537 case S2_asl_i_p_xacc:
538 return rr0(eXOR(rc(1), eASL(rc(2), im(3))), Outputs);
546 return rr0(eASR(rc(1), im(2)), Outputs);
548 return rr0(eASR(rc(1), 16), Outputs);
551 return rr0(eADD(rc(1), eASR(rc(2), im(3))), Outputs);
554 return rr0(eSUB(rc(1), eASR(rc(2), im(3))), Outputs);
557 return rr0(eAND(rc(1), eASR(rc(2), im(3))), Outputs);
560 return rr0(eORL(rc(1), eASR(rc(2), im(3))), Outputs);
561 case S2_asr_i_r_rnd: {
562 // The input is first sign-extended to 64 bits, then the output
563 // is truncated back to 32 bits.
565 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
566 RegisterCell RC = eASR(eADD(eASR(XC, im(2)), eIMM(1, 2*W0)), 1);
567 return rr0(eXTR(RC, 0, W0), Outputs);
569 case S2_asr_i_r_rnd_goodsyntax: {
572 return rr0(rc(1), Outputs);
573 // Result: S2_asr_i_r_rnd Rs, u5-1
574 RegisterCell XC = eSXT(rc(1).cat(eIMM(0, W0)), W0);
575 RegisterCell RC = eLSR(eADD(eASR(XC, S-1), eIMM(1, 2*W0)), 1);
576 return rr0(eXTR(RC, 0, W0), Outputs);
580 case S2_asr_i_svw_trun:
586 return rr0(eLSR(rc(1), im(2)), Outputs);
589 return rr0(eADD(rc(1), eLSR(rc(2), im(3))), Outputs);
592 return rr0(eSUB(rc(1), eLSR(rc(2), im(3))), Outputs);
595 return rr0(eAND(rc(1), eLSR(rc(2), im(3))), Outputs);
598 return rr0(eORL(rc(1), eLSR(rc(2), im(3))), Outputs);
599 case S2_lsr_i_r_xacc:
600 case S2_lsr_i_p_xacc:
601 return rr0(eXOR(rc(1), eLSR(rc(2), im(3))), Outputs);
604 RegisterCell RC = rc(1);
605 RC[im(2)] = BT::BitValue::Zero;
606 return rr0(RC, Outputs);
609 RegisterCell RC = rc(1);
610 RC[im(2)] = BT::BitValue::One;
611 return rr0(RC, Outputs);
613 case S2_togglebit_i: {
614 RegisterCell RC = rc(1);
616 RC[BX] = RC[BX].is(0) ? BT::BitValue::One
617 : RC[BX].is(1) ? BT::BitValue::Zero
618 : BT::BitValue::self();
619 return rr0(RC, Outputs);
623 uint16_t W1 = getRegBitWidth(Reg[1]);
625 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
626 const BT::BitValue Zero = BT::BitValue::Zero;
627 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
628 .fill(W1+(W1-BX), W0, Zero);
629 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1);
630 RegisterCell RC = eINS(eINS(RZ, BF1, 0), BF2, W1);
631 return rr0(RC, Outputs);
637 uint16_t Wd = im(2), Of = im(3);
640 return rr0(eIMM(0, W0), Outputs);
641 // If the width extends beyond the register size, pad the register
643 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1);
644 RegisterCell Ext = eXTR(Pad, Of, Wd+Of);
645 // Ext is short, need to extend it with 0s or sign bit.
646 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1));
647 if (Opc == S2_extractu || Opc == S2_extractup)
648 return rr0(eZXT(RC, Wd), Outputs);
649 return rr0(eSXT(RC, Wd), Outputs);
653 uint16_t Wd = im(3), Of = im(4);
654 assert(Wd < W0 && Of < W0);
655 // If Wd+Of exceeds W0, the inserted bits are truncated.
659 return rr0(rc(1), Outputs);
660 return rr0(eINS(rc(1), eXTR(rc(2), 0, Wd), Of), Outputs);
671 return rr0(cop(2, W0/2).cat(cop(1, W0/2)), Outputs);
675 case A2_combine_hh: {
677 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
678 // Low half in the output is 0 for _ll and _hl, 1 otherwise:
679 unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
680 // High half in the output is 0 for _ll and _lh, 1 otherwise:
681 unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
682 RegisterCell R1 = rc(1);
683 RegisterCell R2 = rc(2);
684 RegisterCell RC = half(R2, LoH).cat(half(R1, HiH));
685 return rr0(RC, Outputs);
689 assert(getRegBitWidth(Reg[1]) == 32 && getRegBitWidth(Reg[2]) == 32);
690 RegisterCell R1 = rc(1);
691 RegisterCell R2 = rc(2);
692 RegisterCell RC = half(R2, 0).cat(half(R1, 0)).cat(half(R2, 1))
694 return rr0(RC, Outputs);
697 RegisterCell RC = shuffle(rc(1), rc(2), 8, false);
698 return rr0(RC, Outputs);
701 RegisterCell RC = shuffle(rc(1), rc(2), 16, false);
702 return rr0(RC, Outputs);
705 RegisterCell RC = shuffle(rc(1), rc(2), 8, true);
706 return rr0(RC, Outputs);
709 RegisterCell RC = shuffle(rc(1), rc(2), 16, true);
710 return rr0(RC, Outputs);
714 uint16_t WP = 8; // XXX Pred size: getRegBitWidth(Reg[1]);
715 assert(WR == 64 && WP == 8);
716 RegisterCell R1 = rc(1);
718 for (uint16_t i = 0; i < WP; ++i) {
719 const BT::BitValue &V = R1[i];
720 BT::BitValue F = (V.is(0) || V.is(1)) ? V : BT::BitValue::self();
721 RC.fill(i*8, i*8+8, F);
723 return rr0(RC, Outputs);
732 BT::BitValue PC0 = rc(1)[0];
733 RegisterCell R2 = cop(2, W0);
734 RegisterCell R3 = cop(3, W0);
735 if (PC0.is(0) || PC0.is(1))
736 return rr0(RegisterCell::ref(PC0 ? R2 : R3), Outputs);
737 R2.meet(R3, Reg[0].Reg);
738 return rr0(R2, Outputs);
744 // Sign- and zero-extension:
747 return rr0(eSXT(rc(1), 8), Outputs);
749 return rr0(eSXT(rc(1), 16), Outputs);
751 uint16_t W1 = getRegBitWidth(Reg[1]);
752 assert(W0 == 64 && W1 == 32);
753 RegisterCell RC = eSXT(rc(1).cat(eIMM(0, W1)), W1);
754 return rr0(RC, Outputs);
757 return rr0(eZXT(rc(1), 8), Outputs);
759 return rr0(eZXT(rc(1), 16), Outputs);
765 // Always produce a 32-bit result.
766 return rr0(eCLB(rc(1), 0/*bit*/, 32), Outputs);
769 return rr0(eCLB(rc(1), 1/*bit*/, 32), Outputs);
772 uint16_t W1 = getRegBitWidth(Reg[1]);
773 RegisterCell R1 = rc(1);
774 BT::BitValue TV = R1[W1-1];
775 if (TV.is(0) || TV.is(1))
776 return rr0(eCLB(R1, TV, 32), Outputs);
781 return rr0(eCTB(rc(1), 0/*bit*/, 32), Outputs);
784 return rr0(eCTB(rc(1), 1/*bit*/, 32), Outputs);
790 RegisterCell P1 = rc(1);
791 bool Has0 = false, All1 = true;
792 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
803 RC.fill(0, W0, (All1 ? BT::BitValue::One : BT::BitValue::Zero));
804 return rr0(RC, Outputs);
807 RegisterCell P1 = rc(1);
808 bool Has1 = false, All0 = true;
809 for (uint16_t i = 0; i < 8/*XXX*/; ++i) {
820 RC.fill(0, W0, (Has1 ? BT::BitValue::One : BT::BitValue::Zero));
821 return rr0(RC, Outputs);
824 return rr0(eAND(rc(1), rc(2)), Outputs);
826 return rr0(eAND(rc(1), eNOT(rc(2))), Outputs);
828 return rr0(eNOT(rc(1)), Outputs);
830 return rr0(eORL(rc(1), rc(2)), Outputs);
832 return rr0(eORL(rc(1), eNOT(rc(2))), Outputs);
834 return rr0(eXOR(rc(1), rc(2)), Outputs);
836 return rr0(eAND(rc(1), eAND(rc(2), rc(3))), Outputs);
838 return rr0(eAND(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
840 return rr0(eAND(rc(1), eORL(rc(2), rc(3))), Outputs);
842 return rr0(eAND(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
844 return rr0(eORL(rc(1), eAND(rc(2), rc(3))), Outputs);
846 return rr0(eORL(rc(1), eAND(rc(2), eNOT(rc(3)))), Outputs);
848 return rr0(eORL(rc(1), eORL(rc(2), rc(3))), Outputs);
850 return rr0(eORL(rc(1), eORL(rc(2), eNOT(rc(3)))), Outputs);
861 BT::BitValue V = rc(1)[im(2)];
862 if (V.is(0) || V.is(1)) {
863 // If instruction is S2_tstbit_i, test for 1, otherwise test for 0.
864 bool TV = (Opc == S2_tstbit_i);
865 BT::BitValue F = V.is(TV) ? BT::BitValue::One : BT::BitValue::Zero;
866 return rr0(RegisterCell(W0).fill(0, W0, F), Outputs);
872 return MachineEvaluator::evaluate(MI, Inputs, Outputs);
881 bool HexagonEvaluator::evaluate(const MachineInstr *BI,
882 const CellMapType &Inputs, BranchTargetList &Targets,
883 bool &FallsThru) const {
884 // We need to evaluate one branch at a time. TII::AnalyzeBranch checks
885 // all the branches in a basic block at once, so we cannot use it.
886 unsigned Opc = BI->getOpcode();
887 bool SimpleBranch = false;
888 bool Negated = false;
890 case Hexagon::J2_jumpf:
891 case Hexagon::J2_jumpfnew:
892 case Hexagon::J2_jumpfnewpt:
894 case Hexagon::J2_jumpt:
895 case Hexagon::J2_jumptnew:
896 case Hexagon::J2_jumptnewpt:
897 // Simple branch: if([!]Pn) jump ...
898 // i.e. Op0 = predicate, Op1 = branch target.
901 case Hexagon::J2_jump:
902 Targets.insert(BI->getOperand(0).getMBB());
906 // If the branch is of unknown type, assume that all successors are
914 // BI is a conditional branch if we got here.
915 RegisterRef PR = BI->getOperand(0);
916 RegisterCell PC = getCell(PR, Inputs);
917 const BT::BitValue &Test = PC[0];
919 // If the condition is neither true nor false, then it's unknown.
920 if (!Test.is(0) && !Test.is(1))
923 // "Test.is(!Negated)" means "branch condition is true".
924 if (!Test.is(!Negated)) {
925 // Condition known to be false.
930 Targets.insert(BI->getOperand(1).getMBB());
936 bool HexagonEvaluator::evaluateLoad(const MachineInstr *MI,
937 const CellMapType &Inputs, CellMapType &Outputs) const {
938 if (TII.isPredicated(MI))
940 assert(MI->mayLoad() && "A load that mayn't?");
941 unsigned Opc = MI->getOpcode();
945 using namespace Hexagon;
953 case L2_loadalignb_pbr:
954 case L2_loadalignb_pcr:
955 case L2_loadalignb_pi:
957 case L2_loadalignh_pbr:
958 case L2_loadalignh_pcr:
959 case L2_loadalignh_pi:
961 case L2_loadbsw2_pbr:
962 case L2_loadbsw2_pci:
963 case L2_loadbsw2_pcr:
965 case L2_loadbsw4_pbr:
966 case L2_loadbsw4_pci:
967 case L2_loadbsw4_pcr:
970 case L2_loadbzw2_pbr:
971 case L2_loadbzw2_pci:
972 case L2_loadbzw2_pcr:
974 case L2_loadbzw4_pbr:
975 case L2_loadbzw4_pci:
976 case L2_loadbzw4_pcr:
1000 case L4_loadrub_abs:
1024 case L2_loadruh_pbr:
1025 case L2_loadruh_pci:
1026 case L2_loadruh_pcr:
1029 case L4_loadruh_abs:
1042 case L2_loadw_locked:
1058 case L4_loadd_locked:
1068 const MachineOperand &MD = MI->getOperand(0);
1069 assert(MD.isReg() && MD.isDef());
1070 RegisterRef RD = MD;
1072 uint16_t W = getRegBitWidth(RD);
1073 assert(W >= BitNum && BitNum > 0);
1074 RegisterCell Res(W);
1076 for (uint16_t i = 0; i < BitNum; ++i)
1077 Res[i] = BT::BitValue::self(BT::BitRef(RD.Reg, i));
1080 const BT::BitValue &Sign = Res[BitNum-1];
1081 for (uint16_t i = BitNum; i < W; ++i)
1082 Res[i] = BT::BitValue::ref(Sign);
1084 for (uint16_t i = BitNum; i < W; ++i)
1085 Res[i] = BT::BitValue::Zero;
1088 putCell(RD, Res, Outputs);
1093 bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr *MI,
1094 const CellMapType &Inputs, CellMapType &Outputs) const {
1095 // If MI defines a formal parameter, but is not a copy (loads are handled
1096 // in evaluateLoad), then it's not clear what to do.
1097 assert(MI->isCopy());
1099 RegisterRef RD = MI->getOperand(0);
1100 RegisterRef RS = MI->getOperand(1);
1101 assert(RD.Sub == 0);
1102 if (!TargetRegisterInfo::isPhysicalRegister(RS.Reg))
1104 RegExtMap::const_iterator F = VRX.find(RD.Reg);
1108 uint16_t EW = F->second.Width;
1109 // Store RD's cell into the map. This will associate the cell with a virtual
1110 // register, and make zero-/sign-extends possible (otherwise we would be ex-
1111 // tending "self" bit values, which will have no effect, since "self" values
1112 // cannot be references to anything).
1113 putCell(RD, getCell(RS, Inputs), Outputs);
1116 // Read RD's cell from the outputs instead of RS's cell from the inputs:
1117 if (F->second.Type == ExtType::SExt)
1118 Res = eSXT(getCell(RD, Outputs), EW);
1119 else if (F->second.Type == ExtType::ZExt)
1120 Res = eZXT(getCell(RD, Outputs), EW);
1122 putCell(RD, Res, Outputs);
1127 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
1128 using namespace Hexagon;
1129 bool Is64 = DoubleRegsRegClass.contains(PReg);
1130 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg));
1132 static const unsigned Phys32[] = { R0, R1, R2, R3, R4, R5 };
1133 static const unsigned Phys64[] = { D0, D1, D2 };
1134 const unsigned Num32 = sizeof(Phys32)/sizeof(unsigned);
1135 const unsigned Num64 = sizeof(Phys64)/sizeof(unsigned);
1137 // Return the first parameter register of the required width.
1139 return (Width <= 32) ? Phys32[0] : Phys64[0];
1141 // Set Idx32, Idx64 in such a way that Idx+1 would give the index of the
1143 unsigned Idx32 = 0, Idx64 = 0;
1145 while (Idx32 < Num32) {
1146 if (Phys32[Idx32] == PReg)
1152 while (Idx64 < Num64) {
1153 if (Phys64[Idx64] == PReg)
1161 return (Idx32+1 < Num32) ? Phys32[Idx32+1] : 0;
1162 return (Idx64+1 < Num64) ? Phys64[Idx64+1] : 0;
1166 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
1167 typedef MachineRegisterInfo::livein_iterator iterator;
1168 for (iterator I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) {
1169 if (I->first == PReg)