1 //===-- HexagonCallingConvLower.h - Calling Conventions ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the Hexagon_CCState class, used for lowering
11 // and implementing calling conventions. Adapted from the target independent
12 // version but this handles calls to varargs functions
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_Hexagon_CODEGEN_CALLINGCONVLOWER_H
17 #define LLVM_Hexagon_CODEGEN_CALLINGCONVLOWER_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 // Need to handle varargs.
27 class TargetRegisterInfo;
29 class Hexagon_CCState;
33 /// Hexagon_CCAssignFn - This function assigns a location for Val, updating
34 /// State to reflect the change.
35 typedef bool Hexagon_CCAssignFn(unsigned ValNo, EVT ValVT,
36 EVT LocVT, CCValAssign::LocInfo LocInfo,
37 ISD::ArgFlagsTy ArgFlags, Hexagon_CCState &State,
43 /// CCState - This class holds information needed while lowering arguments and
44 /// return values. It captures which registers are already assigned and which
45 /// stack slots are used. It provides accessors to allocate these values.
46 class Hexagon_CCState {
47 CallingConv::ID CallingConv;
49 const TargetMachine &TM;
50 SmallVectorImpl<CCValAssign> &Locs;
54 SmallVector<uint32_t, 16> UsedRegs;
56 Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &TM,
57 SmallVectorImpl<CCValAssign> &locs, LLVMContext &c);
59 void addLoc(const CCValAssign &V) {
63 LLVMContext &getContext() const { return Context; }
64 const TargetMachine &getTarget() const { return TM; }
65 unsigned getCallingConv() const { return CallingConv; }
66 bool isVarArg() const { return IsVarArg; }
68 unsigned getNextStackOffset() const { return StackOffset; }
70 /// isAllocated - Return true if the specified register (or an alias) is
72 bool isAllocated(unsigned Reg) const {
73 return UsedRegs[Reg/32] & (1 << (Reg&31));
76 /// AnalyzeFormalArguments - Analyze an ISD::FORMAL_ARGUMENTS node,
77 /// incorporating info about the formals into this state.
78 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
79 Hexagon_CCAssignFn Fn, unsigned SretValueInRegs);
81 /// AnalyzeReturn - Analyze the returned values of an ISD::RET node,
82 /// incorporating info about the result values into this state.
83 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
84 Hexagon_CCAssignFn Fn, unsigned SretValueInRegs);
86 /// AnalyzeCallOperands - Analyze an ISD::CALL node, incorporating info
87 /// about the passed values into this state.
88 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
89 Hexagon_CCAssignFn Fn, int NonVarArgsParams,
90 unsigned SretValueSize);
92 /// AnalyzeCallOperands - Same as above except it takes vectors of types
93 /// and argument flags.
94 void AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
95 SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
96 Hexagon_CCAssignFn Fn);
98 /// AnalyzeCallResult - Analyze the return values of an ISD::CALL node,
99 /// incorporating info about the passed values into this state.
100 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
101 Hexagon_CCAssignFn Fn, unsigned SretValueInRegs);
103 /// AnalyzeCallResult - Same as above except it's specialized for calls which
104 /// produce a single value.
105 void AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn);
107 /// getFirstUnallocated - Return the first unallocated register in the set, or
108 /// NumRegs if they are all allocated.
109 unsigned getFirstUnallocated(const unsigned *Regs, unsigned NumRegs) const {
110 for (unsigned i = 0; i != NumRegs; ++i)
111 if (!isAllocated(Regs[i]))
116 /// AllocateReg - Attempt to allocate one register. If it is not available,
117 /// return zero. Otherwise, return the register, marking it and any aliases
119 unsigned AllocateReg(unsigned Reg) {
120 if (isAllocated(Reg)) return 0;
125 /// Version of AllocateReg with extra register to be shadowed.
126 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) {
127 if (isAllocated(Reg)) return 0;
129 MarkAllocated(ShadowReg);
133 /// AllocateReg - Attempt to allocate one of the specified registers. If none
134 /// are available, return zero. Otherwise, return the first one available,
135 /// marking it and any aliases as allocated.
136 unsigned AllocateReg(const unsigned *Regs, unsigned NumRegs) {
137 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
138 if (FirstUnalloc == NumRegs)
139 return 0; // Didn't find the reg.
141 // Mark the register and any aliases as allocated.
142 unsigned Reg = Regs[FirstUnalloc];
147 /// Version of AllocateReg with list of registers to be shadowed.
148 unsigned AllocateReg(const unsigned *Regs, const unsigned *ShadowRegs,
150 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
151 if (FirstUnalloc == NumRegs)
152 return 0; // Didn't find the reg.
154 // Mark the register and any aliases as allocated.
155 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc];
157 MarkAllocated(ShadowReg);
161 /// AllocateStack - Allocate a chunk of stack space with the specified size
163 unsigned AllocateStack(unsigned Size, unsigned Align) {
164 assert(Align && ((Align-1) & Align) == 0); // Align is power of 2.
165 StackOffset = ((StackOffset + Align-1) & ~(Align-1));
166 unsigned Result = StackOffset;
171 // HandleByVal - Allocate a stack slot large enough to pass an argument by
172 // value. The size and alignment information of the argument is encoded in its
173 // parameter attribute.
174 void HandleByVal(unsigned ValNo, EVT ValVT,
175 EVT LocVT, CCValAssign::LocInfo LocInfo,
176 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
179 /// MarkAllocated - Mark a register and all of its aliases as allocated.
180 void MarkAllocated(unsigned Reg);
185 } // end namespace llvm