1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass replaces transfer instructions by combine instructions.
10 // We walk along a basic block and look for two combinable instructions and try
11 // to move them together. If we can move them next to each other we do so and
12 // replace them with a combine instruction.
13 //===----------------------------------------------------------------------===//
14 #include "llvm/PassSupport.h"
16 #include "HexagonInstrInfo.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/DenseSet.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Support/CodeGen.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
37 #define DEBUG_TYPE "hexagon-copy-combine"
40 cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
41 cl::Hidden, cl::ZeroOrMore,
43 cl::desc("Disable merging into combines"));
46 MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
47 cl::Hidden, cl::init(4),
48 cl::desc("Maximum distance between a tfr feeding a store we "
49 "consider the store still to be newifiable"));
52 void initializeHexagonCopyToCombinePass(PassRegistry&);
58 class HexagonCopyToCombine : public MachineFunctionPass {
59 const HexagonInstrInfo *TII;
60 const TargetRegisterInfo *TRI;
61 bool ShouldCombineAggressively;
63 DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
67 HexagonCopyToCombine() : MachineFunctionPass(ID) {
68 initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
71 void getAnalysisUsage(AnalysisUsage &AU) const override {
72 MachineFunctionPass::getAnalysisUsage(AU);
75 const char *getPassName() const override {
76 return "Hexagon Copy-To-Combine Pass";
79 bool runOnMachineFunction(MachineFunction &Fn) override;
82 MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);
84 void findPotentialNewifiableTFRs(MachineBasicBlock &);
86 void combine(MachineInstr *I1, MachineInstr *I2,
87 MachineBasicBlock::iterator &MI, bool DoInsertAtI1);
89 bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2,
90 unsigned I1DestReg, unsigned I2DestReg,
93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
94 MachineOperand &HiOperand, MachineOperand &LoOperand);
96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
97 MachineOperand &HiOperand, MachineOperand &LoOperand);
99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
100 MachineOperand &HiOperand, MachineOperand &LoOperand);
102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
103 MachineOperand &HiOperand, MachineOperand &LoOperand);
106 } // End anonymous namespace.
108 char HexagonCopyToCombine::ID = 0;
110 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
111 "Hexagon Copy-To-Combine Pass", false, false)
113 static bool isCombinableInstType(MachineInstr *MI,
114 const HexagonInstrInfo *TII,
115 bool ShouldCombineAggressively) {
116 switch(MI->getOpcode()) {
117 case Hexagon::A2_tfr: {
118 // A COPY instruction can be combined if its arguments are IntRegs (32bit).
119 const MachineOperand &Op0 = MI->getOperand(0);
120 const MachineOperand &Op1 = MI->getOperand(1);
121 assert(Op0.isReg() && Op1.isReg());
123 unsigned DestReg = Op0.getReg();
124 unsigned SrcReg = Op1.getReg();
125 return Hexagon::IntRegsRegClass.contains(DestReg) &&
126 Hexagon::IntRegsRegClass.contains(SrcReg);
129 case Hexagon::A2_tfrsi: {
130 // A transfer-immediate can be combined if its argument is a signed 8bit
132 const MachineOperand &Op0 = MI->getOperand(0);
133 const MachineOperand &Op1 = MI->getOperand(1);
136 unsigned DestReg = Op0.getReg();
137 // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
138 // workaround for an ABI bug that prevents GOT relocations on combine
140 if (!Op1.isImm() && Op1.getTargetFlags() != HexagonII::MO_NO_FLAG)
143 // Only combine constant extended A2_tfrsi if we are in aggressive mode.
144 bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm());
145 return Hexagon::IntRegsRegClass.contains(DestReg) &&
146 (ShouldCombineAggressively || NotExt);
156 template <unsigned N>
157 static bool isGreaterThanNBitTFRI(const MachineInstr *I) {
158 if (I->getOpcode() == Hexagon::TFRI64_V4 ||
159 I->getOpcode() == Hexagon::A2_tfrsi) {
160 const MachineOperand &Op = I->getOperand(1);
161 return !Op.isImm() || !isInt<N>(Op.getImm());
166 /// areCombinableOperations - Returns true if the two instruction can be merge
167 /// into a combine (ignoring register constraints).
168 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
169 MachineInstr *HighRegInst,
170 MachineInstr *LowRegInst) {
171 unsigned HiOpc = HighRegInst->getOpcode();
172 unsigned LoOpc = LowRegInst->getOpcode();
173 (void)HiOpc; // Fix compiler warning
174 (void)LoOpc; // Fix compiler warning
175 assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) &&
176 (LoOpc == Hexagon::A2_tfr || LoOpc == Hexagon::A2_tfrsi) &&
177 "Assume individual instructions are of a combinable type");
179 // There is no combine of two constant extended values.
180 if (isGreaterThanNBitTFRI<8>(HighRegInst) &&
181 isGreaterThanNBitTFRI<6>(LowRegInst))
187 static bool isEvenReg(unsigned Reg) {
188 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
189 Hexagon::IntRegsRegClass.contains(Reg));
190 return (Reg - Hexagon::R0) % 2 == 0;
193 static void removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) {
194 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
195 MachineOperand &Op = MI->getOperand(I);
196 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
202 /// isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy
203 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
204 static bool isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg,
206 const TargetRegisterInfo *TRI) {
207 return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
208 I->modifiesRegister(DestReg, TRI) ||
209 I->readsRegister(DestReg, TRI) ||
210 I->hasUnmodeledSideEffects() ||
211 I->isInlineAsm() || I->isDebugValue();
214 static unsigned UseReg(const MachineOperand& MO) {
215 return MO.isReg() ? MO.getReg() : 0;
218 /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
219 /// that the two instructions can be paired in a combine.
220 bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
224 bool &DoInsertAtI1) {
225 unsigned I2UseReg = UseReg(I2->getOperand(1));
227 // It is not safe to move I1 and I2 into one combine if I2 has a true
229 if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
234 // First try to move I2 towards I1.
236 // A reverse_iterator instantiated like below starts before I2, and I1
238 // Look at instructions I in between I2 and (excluding) I1.
239 MachineBasicBlock::reverse_iterator I(I2),
240 End = --(MachineBasicBlock::reverse_iterator(I1));
241 // At 03 we got better results (dhrystone!) by being more conservative.
242 if (!ShouldCombineAggressively)
243 End = MachineBasicBlock::reverse_iterator(I1);
244 // If I2 kills its operand and we move I2 over an instruction that also
245 // uses I2's use reg we need to modify that (first) instruction to now kill
247 unsigned KilledOperand = 0;
248 if (I2->killsRegister(I2UseReg))
249 KilledOperand = I2UseReg;
250 MachineInstr *KillingInstr = nullptr;
252 for (; I != End; ++I) {
253 // If the intervening instruction I:
254 // * modifies I2's use reg
255 // * modifies I2's def reg
256 // * reads I2's def reg
257 // * or has unmodelled side effects
258 // we can't move I2 across it.
259 if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
264 // Update first use of the killed operand.
265 if (!KillingInstr && KilledOperand &&
266 I->readsRegister(KilledOperand, TRI))
270 // Update the intermediate instruction to with the kill flag.
272 bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
273 (void)Added; // suppress compiler warning
274 assert(Added && "Must successfully update kill flag");
275 removeKillInfo(I2, KilledOperand);
282 // Try to move I1 towards I2.
284 // Look at instructions I in between I1 and (excluding) I2.
285 MachineBasicBlock::iterator I(I1), End(I2);
286 // At O3 we got better results (dhrystone) by being more conservative here.
287 if (!ShouldCombineAggressively)
288 End = std::next(MachineBasicBlock::iterator(I2));
289 unsigned I1UseReg = UseReg(I1->getOperand(1));
290 // Track killed operands. If we move across an instruction that kills our
291 // operand, we need to update the kill information on the moved I1. It kills
293 MachineInstr *KillingInstr = nullptr;
294 unsigned KilledOperand = 0;
297 // If the intervening instruction I:
298 // * modifies I1's use reg
299 // * modifies I1's def reg
300 // * reads I1's def reg
301 // * or has unmodelled side effects
302 // We introduce this special case because llvm has no api to remove a
303 // kill flag for a register (a removeRegisterKilled() analogous to
304 // addRegisterKilled) that handles aliased register correctly.
305 // * or has a killed aliased register use of I1's use reg
306 // %D4<def> = TFRI64 16
307 // %R6<def> = TFR %R9
308 // %R8<def> = KILL %R8, %D4<imp-use,kill>
309 // If we want to move R6 = across the KILL instruction we would have
310 // to remove the %D4<imp-use,kill> operand. For now, we are
311 // conservative and disallow the move.
312 // we can't move I1 across it.
313 if (isUnsafeToMoveAcross(I, I1UseReg, I1DestReg, TRI) ||
314 // Check for an aliased register kill. Bail out if we see one.
315 (!I->killsRegister(I1UseReg) && I->killsRegister(I1UseReg, TRI)))
318 // Check for an exact kill (registers match).
319 if (I1UseReg && I->killsRegister(I1UseReg)) {
320 assert(!KillingInstr && "Should only see one killing instruction");
321 KilledOperand = I1UseReg;
326 removeKillInfo(KillingInstr, KilledOperand);
327 // Update I1 to set the kill flag. This flag will later be picked up by
328 // the new COMBINE instruction.
329 bool Added = I1->addRegisterKilled(KilledOperand, TRI);
330 (void)Added; // suppress compiler warning
331 assert(Added && "Must successfully update kill flag");
333 DoInsertAtI1 = false;
339 /// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
340 /// newified. (A use of a 64 bit register define can not be newified)
342 HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
343 DenseMap<unsigned, MachineInstr *> LastDef;
344 for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
345 MachineInstr *MI = I;
346 // Mark TFRs that feed a potential new value store as such.
347 if(TII->mayBeNewStore(MI)) {
348 // Look for uses of TFR instructions.
349 for (unsigned OpdIdx = 0, OpdE = MI->getNumOperands(); OpdIdx != OpdE;
351 MachineOperand &Op = MI->getOperand(OpdIdx);
353 // Skip over anything except register uses.
354 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
357 // Look for the defining instruction.
358 unsigned Reg = Op.getReg();
359 MachineInstr *DefInst = LastDef[Reg];
362 if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
365 // Only close newifiable stores should influence the decision.
366 MachineBasicBlock::iterator It(DefInst);
367 unsigned NumInstsToDef = 0;
371 if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
374 PotentiallyNewifiableTFR.insert(DefInst);
376 // Skip to next instruction.
380 // Put instructions that last defined integer or double registers into the
382 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
383 MachineOperand &Op = MI->getOperand(I);
384 if (!Op.isReg() || !Op.isDef() || !Op.getReg())
386 unsigned Reg = Op.getReg();
387 if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
388 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
389 LastDef[*SubRegs] = MI;
391 } else if (Hexagon::IntRegsRegClass.contains(Reg))
397 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
399 if (IsCombinesDisabled) return false;
401 bool HasChanged = false;
404 TRI = MF.getSubtarget().getRegisterInfo();
405 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
407 // Combine aggressively (for code size)
408 ShouldCombineAggressively =
409 MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
411 // Traverse basic blocks.
412 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
414 PotentiallyNewifiableTFR.clear();
415 findPotentialNewifiableTFRs(*BI);
417 // Traverse instructions in basic block.
418 for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
420 MachineInstr *I1 = MI++;
421 // Don't combine a TFR whose user could be newified (instructions that
422 // define double registers can not be newified - Programmer's Ref Manual
423 // 5.4.2 New-value stores).
424 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I1))
427 // Ignore instructions that are not combinable.
428 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
431 // Find a second instruction that can be merged into a combine
433 bool DoInsertAtI1 = false;
434 MachineInstr *I2 = findPairable(I1, DoInsertAtI1);
437 combine(I1, I2, MI, DoInsertAtI1);
445 /// findPairable - Returns an instruction that can be merged with \p I1 into a
446 /// COMBINE instruction or 0 if no such instruction can be found. Returns true
447 /// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
448 /// false if the combine must be inserted at the returned instruction.
449 MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
450 bool &DoInsertAtI1) {
451 MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
452 unsigned I1DestReg = I1->getOperand(0).getReg();
454 for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
456 // Bail out early if we see a second definition of I1DestReg.
457 if (I2->modifiesRegister(I1DestReg, TRI))
460 // Ignore non-combinable instructions.
461 if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
464 // Don't combine a TFR whose user could be newified.
465 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I2))
468 unsigned I2DestReg = I2->getOperand(0).getReg();
470 // Check that registers are adjacent and that the first destination register
472 bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
473 bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
474 unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
475 if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
478 // Check that the two instructions are combinable. V4 allows more
479 // instructions to be merged into a combine.
480 // The order matters because in a TFRI we might can encode a int8 as the
481 // hi reg operand but only a uint6 as the low reg operand.
482 if ((IsI2LowReg && !areCombinableOperations(TRI, I1, I2)) ||
483 (IsI1LowReg && !areCombinableOperations(TRI, I2, I1)))
486 if (isSafeToMoveTogether(I1, I2, I1DestReg, I2DestReg,
490 // Not safe. Stop searching.
496 void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
497 MachineBasicBlock::iterator &MI,
499 // We are going to delete I2. If MI points to I2 advance it to the next
501 if ((MachineInstr *)MI == I2) ++MI;
503 // Figure out whether I1 or I2 goes into the lowreg part.
504 unsigned I1DestReg = I1->getOperand(0).getReg();
505 unsigned I2DestReg = I2->getOperand(0).getReg();
506 bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
507 unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
509 // Get the double word register.
510 unsigned DoubleRegDest =
511 TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg,
512 &Hexagon::DoubleRegsRegClass);
513 assert(DoubleRegDest != 0 && "Expect a valid register");
516 // Setup source operands.
517 MachineOperand &LoOperand = IsI1Loreg ? I1->getOperand(1) :
519 MachineOperand &HiOperand = IsI1Loreg ? I2->getOperand(1) :
522 // Figure out which source is a register and which a constant.
523 bool IsHiReg = HiOperand.isReg();
524 bool IsLoReg = LoOperand.isReg();
526 MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
528 if (IsHiReg && IsLoReg)
529 emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
531 emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
533 emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
535 emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
537 I1->eraseFromParent();
538 I2->eraseFromParent();
541 void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
542 unsigned DoubleDestReg,
543 MachineOperand &HiOperand,
544 MachineOperand &LoOperand) {
545 DebugLoc DL = InsertPt->getDebugLoc();
546 MachineBasicBlock *BB = InsertPt->getParent();
549 if (HiOperand.isGlobal()) {
550 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
551 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
552 HiOperand.getTargetFlags())
553 .addImm(LoOperand.getImm());
556 if (LoOperand.isGlobal()) {
557 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
558 .addImm(HiOperand.getImm())
559 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
560 LoOperand.getTargetFlags());
564 // Handle block addresses.
565 if (HiOperand.isBlockAddress()) {
566 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
567 .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
568 HiOperand.getTargetFlags())
569 .addImm(LoOperand.getImm());
572 if (LoOperand.isBlockAddress()) {
573 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
574 .addImm(HiOperand.getImm())
575 .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
576 LoOperand.getTargetFlags());
580 // Handle jump tables.
581 if (HiOperand.isJTI()) {
582 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
583 .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
584 .addImm(LoOperand.getImm());
587 if (LoOperand.isJTI()) {
588 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
589 .addImm(HiOperand.getImm())
590 .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
594 // Handle constant pools.
595 if (HiOperand.isCPI()) {
596 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
597 .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
598 HiOperand.getTargetFlags())
599 .addImm(LoOperand.getImm());
602 if (LoOperand.isCPI()) {
603 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
604 .addImm(HiOperand.getImm())
605 .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
606 LoOperand.getTargetFlags());
610 // First preference should be given to Hexagon::A2_combineii instruction
611 // as it can include U6 (in Hexagon::A4_combineii) as well.
612 // In this instruction, HiOperand is const extended, if required.
613 if (isInt<8>(LoOperand.getImm())) {
614 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
615 .addImm(HiOperand.getImm())
616 .addImm(LoOperand.getImm());
620 // In this instruction, LoOperand is const extended, if required.
621 if (isInt<8>(HiOperand.getImm())) {
622 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
623 .addImm(HiOperand.getImm())
624 .addImm(LoOperand.getImm());
628 // Insert new combine instruction.
629 // DoubleRegDest = combine #HiImm, #LoImm
630 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
631 .addImm(HiOperand.getImm())
632 .addImm(LoOperand.getImm());
635 void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
636 unsigned DoubleDestReg,
637 MachineOperand &HiOperand,
638 MachineOperand &LoOperand) {
639 unsigned LoReg = LoOperand.getReg();
640 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
642 DebugLoc DL = InsertPt->getDebugLoc();
643 MachineBasicBlock *BB = InsertPt->getParent();
646 if (HiOperand.isGlobal()) {
647 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
648 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
649 HiOperand.getTargetFlags())
650 .addReg(LoReg, LoRegKillFlag);
653 // Handle block addresses.
654 if (HiOperand.isBlockAddress()) {
655 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
656 .addBlockAddress(HiOperand.getBlockAddress(), HiOperand.getOffset(),
657 HiOperand.getTargetFlags())
658 .addReg(LoReg, LoRegKillFlag);
661 // Handle jump tables.
662 if (HiOperand.isJTI()) {
663 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
664 .addJumpTableIndex(HiOperand.getIndex(), HiOperand.getTargetFlags())
665 .addReg(LoReg, LoRegKillFlag);
668 // Handle constant pools.
669 if (HiOperand.isCPI()) {
670 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
671 .addConstantPoolIndex(HiOperand.getIndex(), HiOperand.getOffset(),
672 HiOperand.getTargetFlags())
673 .addReg(LoReg, LoRegKillFlag);
676 // Insert new combine instruction.
677 // DoubleRegDest = combine #HiImm, LoReg
678 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
679 .addImm(HiOperand.getImm())
680 .addReg(LoReg, LoRegKillFlag);
683 void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
684 unsigned DoubleDestReg,
685 MachineOperand &HiOperand,
686 MachineOperand &LoOperand) {
687 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
688 unsigned HiReg = HiOperand.getReg();
690 DebugLoc DL = InsertPt->getDebugLoc();
691 MachineBasicBlock *BB = InsertPt->getParent();
694 if (LoOperand.isGlobal()) {
695 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
696 .addReg(HiReg, HiRegKillFlag)
697 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
698 LoOperand.getTargetFlags());
701 // Handle block addresses.
702 if (LoOperand.isBlockAddress()) {
703 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
704 .addReg(HiReg, HiRegKillFlag)
705 .addBlockAddress(LoOperand.getBlockAddress(), LoOperand.getOffset(),
706 LoOperand.getTargetFlags());
709 // Handle jump tables.
710 if (LoOperand.isJTI()) {
711 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
712 .addReg(HiOperand.getReg(), HiRegKillFlag)
713 .addJumpTableIndex(LoOperand.getIndex(), LoOperand.getTargetFlags());
716 // Handle constant pools.
717 if (LoOperand.isCPI()) {
718 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
719 .addReg(HiOperand.getReg(), HiRegKillFlag)
720 .addConstantPoolIndex(LoOperand.getIndex(), LoOperand.getOffset(),
721 LoOperand.getTargetFlags());
725 // Insert new combine instruction.
726 // DoubleRegDest = combine HiReg, #LoImm
727 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
728 .addReg(HiReg, HiRegKillFlag)
729 .addImm(LoOperand.getImm());
732 void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
733 unsigned DoubleDestReg,
734 MachineOperand &HiOperand,
735 MachineOperand &LoOperand) {
736 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
737 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
738 unsigned LoReg = LoOperand.getReg();
739 unsigned HiReg = HiOperand.getReg();
741 DebugLoc DL = InsertPt->getDebugLoc();
742 MachineBasicBlock *BB = InsertPt->getParent();
744 // Insert new combine instruction.
745 // DoubleRegDest = combine HiReg, LoReg
746 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combinew), DoubleDestReg)
747 .addReg(HiReg, HiRegKillFlag)
748 .addReg(LoReg, LoRegKillFlag);
751 FunctionPass *llvm::createHexagonCopyToCombine() {
752 return new HexagonCopyToCombine();