1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass replaces transfer instructions by combine instructions.
10 // We walk along a basic block and look for two combinable instructions and try
11 // to move them together. If we can move them next to each other we do so and
12 // replace them with a combine instruction.
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "hexagon-copy-combine"
16 #include "llvm/PassSupport.h"
18 #include "HexagonInstrInfo.h"
19 #include "HexagonMachineFunctionInfo.h"
20 #include "HexagonRegisterInfo.h"
21 #include "HexagonSubtarget.h"
22 #include "HexagonTargetMachine.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/DenseSet.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstr.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/Support/CodeGen.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
40 cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
41 cl::Hidden, cl::ZeroOrMore,
43 cl::desc("Disable merging into combines"));
46 MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
47 cl::Hidden, cl::init(4),
48 cl::desc("Maximum distance between a tfr feeding a store we "
49 "consider the store still to be newifiable"));
52 void initializeHexagonCopyToCombinePass(PassRegistry&);
58 class HexagonCopyToCombine : public MachineFunctionPass {
59 const HexagonInstrInfo *TII;
60 const TargetRegisterInfo *TRI;
61 bool ShouldCombineAggressively;
63 DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
67 HexagonCopyToCombine() : MachineFunctionPass(ID) {
68 initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
71 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
72 MachineFunctionPass::getAnalysisUsage(AU);
75 const char *getPassName() const {
76 return "Hexagon Copy-To-Combine Pass";
79 virtual bool runOnMachineFunction(MachineFunction &Fn);
82 MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);
84 void findPotentialNewifiableTFRs(MachineBasicBlock &);
86 void combine(MachineInstr *I1, MachineInstr *I2,
87 MachineBasicBlock::iterator &MI, bool DoInsertAtI1);
89 bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2,
90 unsigned I1DestReg, unsigned I2DestReg,
93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
94 MachineOperand &HiOperand, MachineOperand &LoOperand);
96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
97 MachineOperand &HiOperand, MachineOperand &LoOperand);
99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
100 MachineOperand &HiOperand, MachineOperand &LoOperand);
102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
103 MachineOperand &HiOperand, MachineOperand &LoOperand);
106 } // End anonymous namespace.
108 char HexagonCopyToCombine::ID = 0;
110 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
111 "Hexagon Copy-To-Combine Pass", false, false)
113 static bool isCombinableInstType(MachineInstr *MI,
114 const HexagonInstrInfo *TII,
115 bool ShouldCombineAggressively) {
116 switch(MI->getOpcode()) {
118 // A COPY instruction can be combined if its arguments are IntRegs (32bit).
119 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg());
121 unsigned DestReg = MI->getOperand(0).getReg();
122 unsigned SrcReg = MI->getOperand(1).getReg();
123 return Hexagon::IntRegsRegClass.contains(DestReg) &&
124 Hexagon::IntRegsRegClass.contains(SrcReg);
127 case Hexagon::TFRI: {
128 // A transfer-immediate can be combined if its argument is a signed 8bit
130 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
131 unsigned DestReg = MI->getOperand(0).getReg();
133 // Only combine constant extended TFRI if we are in aggressive mode.
134 return Hexagon::IntRegsRegClass.contains(DestReg) &&
135 (ShouldCombineAggressively || isInt<8>(MI->getOperand(1).getImm()));
138 case Hexagon::TFRI_V4: {
139 if (!ShouldCombineAggressively)
141 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal());
143 // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
144 // workaround for an ABI bug that prevents GOT relocations on combine
146 if (MI->getOperand(1).getTargetFlags() != HexagonII::MO_NO_FLAG)
149 unsigned DestReg = MI->getOperand(0).getReg();
150 return Hexagon::IntRegsRegClass.contains(DestReg);
160 static bool isGreaterThan8BitTFRI(MachineInstr *I) {
161 return I->getOpcode() == Hexagon::TFRI &&
162 !isInt<8>(I->getOperand(1).getImm());
164 static bool isGreaterThan6BitTFRI(MachineInstr *I) {
165 return I->getOpcode() == Hexagon::TFRI &&
166 !isUInt<6>(I->getOperand(1).getImm());
169 /// areCombinableOperations - Returns true if the two instruction can be merge
170 /// into a combine (ignoring register constraints).
171 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
172 MachineInstr *HighRegInst,
173 MachineInstr *LowRegInst) {
174 assert((HighRegInst->getOpcode() == Hexagon::TFR ||
175 HighRegInst->getOpcode() == Hexagon::TFRI ||
176 HighRegInst->getOpcode() == Hexagon::TFRI_V4) &&
177 (LowRegInst->getOpcode() == Hexagon::TFR ||
178 LowRegInst->getOpcode() == Hexagon::TFRI ||
179 LowRegInst->getOpcode() == Hexagon::TFRI_V4) &&
180 "Assume individual instructions are of a combinable type");
182 const HexagonRegisterInfo *QRI =
183 static_cast<const HexagonRegisterInfo *>(TRI);
185 // V4 added some combine variations (mixed immediate and register source
186 // operands), if we are on < V4 we can only combine 2 register-to-register
187 // moves and 2 immediate-to-register moves. We also don't have
188 // constant-extenders.
189 if (!QRI->Subtarget.hasV4TOps())
190 return HighRegInst->getOpcode() == LowRegInst->getOpcode() &&
191 !isGreaterThan8BitTFRI(HighRegInst) &&
192 !isGreaterThan6BitTFRI(LowRegInst);
194 // There is no combine of two constant extended values.
195 if ((HighRegInst->getOpcode() == Hexagon::TFRI_V4 ||
196 isGreaterThan8BitTFRI(HighRegInst)) &&
197 (LowRegInst->getOpcode() == Hexagon::TFRI_V4 ||
198 isGreaterThan6BitTFRI(LowRegInst)))
204 static bool isEvenReg(unsigned Reg) {
205 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
206 Hexagon::IntRegsRegClass.contains(Reg));
207 return (Reg - Hexagon::R0) % 2 == 0;
210 static void removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) {
211 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
212 MachineOperand &Op = MI->getOperand(I);
213 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
219 /// isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy
220 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
221 static bool isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg,
223 const TargetRegisterInfo *TRI) {
224 return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
225 I->modifiesRegister(DestReg, TRI) ||
226 I->readsRegister(DestReg, TRI) ||
227 I->hasUnmodeledSideEffects() ||
228 I->isInlineAsm() || I->isDebugValue();
231 /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
232 /// that the two instructions can be paired in a combine.
233 bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
237 bool &DoInsertAtI1) {
239 bool IsImmUseReg = I2->getOperand(1).isImm() || I2->getOperand(1).isGlobal();
240 unsigned I2UseReg = IsImmUseReg ? 0 : I2->getOperand(1).getReg();
242 // It is not safe to move I1 and I2 into one combine if I2 has a true
244 if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
249 // First try to move I2 towards I1.
251 // A reverse_iterator instantiated like below starts before I2, and I1
253 // Look at instructions I in between I2 and (excluding) I1.
254 MachineBasicBlock::reverse_iterator I(I2),
255 End = --(MachineBasicBlock::reverse_iterator(I1));
256 // At 03 we got better results (dhrystone!) by being more conservative.
257 if (!ShouldCombineAggressively)
258 End = MachineBasicBlock::reverse_iterator(I1);
259 // If I2 kills its operand and we move I2 over an instruction that also
260 // uses I2's use reg we need to modify that (first) instruction to now kill
262 unsigned KilledOperand = 0;
263 if (I2->killsRegister(I2UseReg))
264 KilledOperand = I2UseReg;
265 MachineInstr *KillingInstr = 0;
267 for (; I != End; ++I) {
268 // If the intervening instruction I:
269 // * modifies I2's use reg
270 // * modifies I2's def reg
271 // * reads I2's def reg
272 // * or has unmodelled side effects
273 // we can't move I2 across it.
274 if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
279 // Update first use of the killed operand.
280 if (!KillingInstr && KilledOperand &&
281 I->readsRegister(KilledOperand, TRI))
285 // Update the intermediate instruction to with the kill flag.
287 bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
288 (void)Added; // supress compiler warning
289 assert(Added && "Must successfully update kill flag");
290 removeKillInfo(I2, KilledOperand);
297 // Try to move I1 towards I2.
299 // Look at instructions I in between I1 and (excluding) I2.
300 MachineBasicBlock::iterator I(I1), End(I2);
301 // At O3 we got better results (dhrystone) by being more conservative here.
302 if (!ShouldCombineAggressively)
303 End = llvm::next(MachineBasicBlock::iterator(I2));
304 IsImmUseReg = I1->getOperand(1).isImm() || I1->getOperand(1).isGlobal();
305 unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg();
306 // Track killed operands. If we move across an instruction that kills our
307 // operand, we need to update the kill information on the moved I1. It kills
309 MachineInstr *KillingInstr = 0;
310 unsigned KilledOperand = 0;
313 // If the intervening instruction I:
314 // * modifies I1's use reg
315 // * modifies I1's def reg
316 // * reads I1's def reg
317 // * or has unmodelled side effects
318 // We introduce this special case because llvm has no api to remove a
319 // kill flag for a register (a removeRegisterKilled() analogous to
320 // addRegisterKilled) that handles aliased register correctly.
321 // * or has a killed aliased register use of I1's use reg
322 // %D4<def> = TFRI64 16
323 // %R6<def> = TFR %R9
324 // %R8<def> = KILL %R8, %D4<imp-use,kill>
325 // If we want to move R6 = across the KILL instruction we would have
326 // to remove the %D4<imp-use,kill> operand. For now, we are
327 // conservative and disallow the move.
328 // we can't move I1 across it.
329 if (isUnsafeToMoveAcross(I, I1UseReg, I1DestReg, TRI) ||
330 // Check for an aliased register kill. Bail out if we see one.
331 (!I->killsRegister(I1UseReg) && I->killsRegister(I1UseReg, TRI)))
334 // Check for an exact kill (registers match).
335 if (I1UseReg && I->killsRegister(I1UseReg)) {
336 assert(KillingInstr == 0 && "Should only see one killing instruction");
337 KilledOperand = I1UseReg;
342 removeKillInfo(KillingInstr, KilledOperand);
343 // Update I1 to set the kill flag. This flag will later be picked up by
344 // the new COMBINE instruction.
345 bool Added = I1->addRegisterKilled(KilledOperand, TRI);
346 (void)Added; // supress compiler warning
347 assert(Added && "Must successfully update kill flag");
349 DoInsertAtI1 = false;
355 /// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
356 /// newified. (A use of a 64 bit register define can not be newified)
358 HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
359 DenseMap<unsigned, MachineInstr *> LastDef;
360 for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
361 MachineInstr *MI = I;
362 // Mark TFRs that feed a potential new value store as such.
363 if(TII->mayBeNewStore(MI)) {
364 // Look for uses of TFR instructions.
365 for (unsigned OpdIdx = 0, OpdE = MI->getNumOperands(); OpdIdx != OpdE;
367 MachineOperand &Op = MI->getOperand(OpdIdx);
369 // Skip over anything except register uses.
370 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
373 // Look for the defining instruction.
374 unsigned Reg = Op.getReg();
375 MachineInstr *DefInst = LastDef[Reg];
378 if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
381 // Only close newifiable stores should influence the decision.
382 MachineBasicBlock::iterator It(DefInst);
383 unsigned NumInstsToDef = 0;
387 if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
390 PotentiallyNewifiableTFR.insert(DefInst);
392 // Skip to next instruction.
396 // Put instructions that last defined integer or double registers into the
398 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
399 MachineOperand &Op = MI->getOperand(I);
400 if (!Op.isReg() || !Op.isDef() || !Op.getReg())
402 unsigned Reg = Op.getReg();
403 if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
404 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
405 LastDef[*SubRegs] = MI;
407 } else if (Hexagon::IntRegsRegClass.contains(Reg))
413 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
415 if (IsCombinesDisabled) return false;
417 bool HasChanged = false;
420 TRI = MF.getTarget().getRegisterInfo();
421 TII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
423 // Combine aggressively (for code size)
424 ShouldCombineAggressively =
425 MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
427 // Traverse basic blocks.
428 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
430 PotentiallyNewifiableTFR.clear();
431 findPotentialNewifiableTFRs(*BI);
433 // Traverse instructions in basic block.
434 for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
436 MachineInstr *I1 = MI++;
437 // Don't combine a TFR whose user could be newified (instructions that
438 // define double registers can not be newified - Programmer's Ref Manual
439 // 5.4.2 New-value stores).
440 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I1))
443 // Ignore instructions that are not combinable.
444 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
447 // Find a second instruction that can be merged into a combine
449 bool DoInsertAtI1 = false;
450 MachineInstr *I2 = findPairable(I1, DoInsertAtI1);
453 combine(I1, I2, MI, DoInsertAtI1);
461 /// findPairable - Returns an instruction that can be merged with \p I1 into a
462 /// COMBINE instruction or 0 if no such instruction can be found. Returns true
463 /// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
464 /// false if the combine must be inserted at the returned instruction.
465 MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
466 bool &DoInsertAtI1) {
467 MachineBasicBlock::iterator I2 = llvm::next(MachineBasicBlock::iterator(I1));
468 unsigned I1DestReg = I1->getOperand(0).getReg();
470 for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
472 // Bail out early if we see a second definition of I1DestReg.
473 if (I2->modifiesRegister(I1DestReg, TRI))
476 // Ignore non-combinable instructions.
477 if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
480 // Don't combine a TFR whose user could be newified.
481 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I2))
484 unsigned I2DestReg = I2->getOperand(0).getReg();
486 // Check that registers are adjacent and that the first destination register
488 bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
489 bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
490 unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
491 if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
494 // Check that the two instructions are combinable. V4 allows more
495 // instructions to be merged into a combine.
496 // The order matters because in a TFRI we might can encode a int8 as the
497 // hi reg operand but only a uint6 as the low reg operand.
498 if ((IsI2LowReg && !areCombinableOperations(TRI, I1, I2)) ||
499 (IsI1LowReg && !areCombinableOperations(TRI, I2, I1)))
502 if (isSafeToMoveTogether(I1, I2, I1DestReg, I2DestReg,
506 // Not safe. Stop searching.
512 void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
513 MachineBasicBlock::iterator &MI,
515 // We are going to delete I2. If MI points to I2 advance it to the next
517 if ((MachineInstr *)MI == I2) ++MI;
519 // Figure out whether I1 or I2 goes into the lowreg part.
520 unsigned I1DestReg = I1->getOperand(0).getReg();
521 unsigned I2DestReg = I2->getOperand(0).getReg();
522 bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
523 unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
525 // Get the double word register.
526 unsigned DoubleRegDest =
527 TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg,
528 &Hexagon::DoubleRegsRegClass);
529 assert(DoubleRegDest != 0 && "Expect a valid register");
532 // Setup source operands.
533 MachineOperand &LoOperand = IsI1Loreg ? I1->getOperand(1) :
535 MachineOperand &HiOperand = IsI1Loreg ? I2->getOperand(1) :
538 // Figure out which source is a register and which a constant.
539 bool IsHiReg = HiOperand.isReg();
540 bool IsLoReg = LoOperand.isReg();
542 MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
544 if (IsHiReg && IsLoReg)
545 emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
547 emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
549 emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
551 emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
553 I1->eraseFromParent();
554 I2->eraseFromParent();
557 void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
558 unsigned DoubleDestReg,
559 MachineOperand &HiOperand,
560 MachineOperand &LoOperand) {
561 DebugLoc DL = InsertPt->getDebugLoc();
562 MachineBasicBlock *BB = InsertPt->getParent();
565 if (HiOperand.isGlobal()) {
566 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
567 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
568 HiOperand.getTargetFlags())
569 .addImm(LoOperand.getImm());
572 if (LoOperand.isGlobal()) {
573 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
574 .addImm(HiOperand.getImm())
575 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
576 LoOperand.getTargetFlags());
580 // Handle constant extended immediates.
581 if (!isInt<8>(HiOperand.getImm())) {
582 assert(isInt<8>(LoOperand.getImm()));
583 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
584 .addImm(HiOperand.getImm())
585 .addImm(LoOperand.getImm());
589 if (!isUInt<6>(LoOperand.getImm())) {
590 assert(isInt<8>(HiOperand.getImm()));
591 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
592 .addImm(HiOperand.getImm())
593 .addImm(LoOperand.getImm());
597 // Insert new combine instruction.
598 // DoubleRegDest = combine #HiImm, #LoImm
599 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
600 .addImm(HiOperand.getImm())
601 .addImm(LoOperand.getImm());
604 void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
605 unsigned DoubleDestReg,
606 MachineOperand &HiOperand,
607 MachineOperand &LoOperand) {
608 unsigned LoReg = LoOperand.getReg();
609 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
611 DebugLoc DL = InsertPt->getDebugLoc();
612 MachineBasicBlock *BB = InsertPt->getParent();
615 if (HiOperand.isGlobal()) {
616 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg)
617 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
618 HiOperand.getTargetFlags())
619 .addReg(LoReg, LoRegKillFlag);
622 // Insert new combine instruction.
623 // DoubleRegDest = combine #HiImm, LoReg
624 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg)
625 .addImm(HiOperand.getImm())
626 .addReg(LoReg, LoRegKillFlag);
629 void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
630 unsigned DoubleDestReg,
631 MachineOperand &HiOperand,
632 MachineOperand &LoOperand) {
633 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
634 unsigned HiReg = HiOperand.getReg();
636 DebugLoc DL = InsertPt->getDebugLoc();
637 MachineBasicBlock *BB = InsertPt->getParent();
640 if (LoOperand.isGlobal()) {
641 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg)
642 .addReg(HiReg, HiRegKillFlag)
643 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
644 LoOperand.getTargetFlags());
648 // Insert new combine instruction.
649 // DoubleRegDest = combine HiReg, #LoImm
650 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg)
651 .addReg(HiReg, HiRegKillFlag)
652 .addImm(LoOperand.getImm());
655 void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
656 unsigned DoubleDestReg,
657 MachineOperand &HiOperand,
658 MachineOperand &LoOperand) {
659 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
660 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
661 unsigned LoReg = LoOperand.getReg();
662 unsigned HiReg = HiOperand.getReg();
664 DebugLoc DL = InsertPt->getDebugLoc();
665 MachineBasicBlock *BB = InsertPt->getParent();
667 // Insert new combine instruction.
668 // DoubleRegDest = combine HiReg, LoReg
669 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rr), DoubleDestReg)
670 .addReg(HiReg, HiRegKillFlag)
671 .addReg(LoReg, LoRegKillFlag);
674 FunctionPass *llvm::createHexagonCopyToCombine() {
675 return new HexagonCopyToCombine();