1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass replaces transfer instructions by combine instructions.
10 // We walk along a basic block and look for two combinable instructions and try
11 // to move them together. If we can move them next to each other we do so and
12 // replace them with a combine instruction.
13 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "hexagon-copy-combine"
16 #include "llvm/PassSupport.h"
17 #include "llvm/ADT/DenseSet.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/Target/TargetRegisterInfo.h"
26 #include "llvm/Support/CodeGen.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/raw_ostream.h"
32 #include "HexagonInstrInfo.h"
33 #include "HexagonRegisterInfo.h"
34 #include "HexagonSubtarget.h"
35 #include "HexagonTargetMachine.h"
36 #include "HexagonMachineFunctionInfo.h"
41 cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
42 cl::Hidden, cl::ZeroOrMore,
44 cl::desc("Disable merging into combines"));
47 MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
48 cl::Hidden, cl::init(4),
49 cl::desc("Maximum distance between a tfr feeding a store we "
50 "consider the store still to be newifiable"));
53 void initializeHexagonCopyToCombinePass(PassRegistry&);
59 class HexagonCopyToCombine : public MachineFunctionPass {
60 const HexagonInstrInfo *TII;
61 const TargetRegisterInfo *TRI;
62 bool ShouldCombineAggressively;
64 DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
68 HexagonCopyToCombine() : MachineFunctionPass(ID) {
69 initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
72 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
73 MachineFunctionPass::getAnalysisUsage(AU);
76 const char *getPassName() const {
77 return "Hexagon Copy-To-Combine Pass";
80 virtual bool runOnMachineFunction(MachineFunction &Fn);
83 MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);
85 void findPotentialNewifiableTFRs(MachineBasicBlock &);
87 void combine(MachineInstr *I1, MachineInstr *I2,
88 MachineBasicBlock::iterator &MI, bool DoInsertAtI1);
90 bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2,
91 unsigned I1DestReg, unsigned I2DestReg,
94 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
95 MachineOperand &HiOperand, MachineOperand &LoOperand);
97 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
98 MachineOperand &HiOperand, MachineOperand &LoOperand);
100 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
101 MachineOperand &HiOperand, MachineOperand &LoOperand);
103 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
104 MachineOperand &HiOperand, MachineOperand &LoOperand);
107 } // End anonymous namespace.
109 char HexagonCopyToCombine::ID = 0;
111 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
112 "Hexagon Copy-To-Combine Pass", false, false)
114 static bool isCombinableInstType(MachineInstr *MI,
115 const HexagonInstrInfo *TII,
116 bool ShouldCombineAggressively) {
117 switch(MI->getOpcode()) {
119 // A COPY instruction can be combined if its arguments are IntRegs (32bit).
120 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg());
122 unsigned DestReg = MI->getOperand(0).getReg();
123 unsigned SrcReg = MI->getOperand(1).getReg();
124 return Hexagon::IntRegsRegClass.contains(DestReg) &&
125 Hexagon::IntRegsRegClass.contains(SrcReg);
128 case Hexagon::TFRI: {
129 // A transfer-immediate can be combined if its argument is a signed 8bit
131 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
132 unsigned DestReg = MI->getOperand(0).getReg();
134 // Only combine constant extended TFRI if we are in aggressive mode.
135 return Hexagon::IntRegsRegClass.contains(DestReg) &&
136 (ShouldCombineAggressively || isInt<8>(MI->getOperand(1).getImm()));
139 case Hexagon::TFRI_V4: {
140 if (!ShouldCombineAggressively)
142 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal());
144 // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
145 // workaround for an ABI bug that prevents GOT relocations on combine
147 if (MI->getOperand(1).getTargetFlags() != HexagonII::MO_NO_FLAG)
150 unsigned DestReg = MI->getOperand(0).getReg();
151 return Hexagon::IntRegsRegClass.contains(DestReg);
161 static bool isGreaterThan8BitTFRI(MachineInstr *I) {
162 return I->getOpcode() == Hexagon::TFRI &&
163 !isInt<8>(I->getOperand(1).getImm());
165 static bool isGreaterThan6BitTFRI(MachineInstr *I) {
166 return I->getOpcode() == Hexagon::TFRI &&
167 !isUInt<6>(I->getOperand(1).getImm());
170 /// areCombinableOperations - Returns true if the two instruction can be merge
171 /// into a combine (ignoring register constraints).
172 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
173 MachineInstr *HighRegInst,
174 MachineInstr *LowRegInst) {
175 assert((HighRegInst->getOpcode() == Hexagon::TFR ||
176 HighRegInst->getOpcode() == Hexagon::TFRI ||
177 HighRegInst->getOpcode() == Hexagon::TFRI_V4) &&
178 (LowRegInst->getOpcode() == Hexagon::TFR ||
179 LowRegInst->getOpcode() == Hexagon::TFRI ||
180 LowRegInst->getOpcode() == Hexagon::TFRI_V4) &&
181 "Assume individual instructions are of a combinable type");
183 const HexagonRegisterInfo *QRI =
184 static_cast<const HexagonRegisterInfo *>(TRI);
186 // V4 added some combine variations (mixed immediate and register source
187 // operands), if we are on < V4 we can only combine 2 register-to-register
188 // moves and 2 immediate-to-register moves. We also don't have
189 // constant-extenders.
190 if (!QRI->Subtarget.hasV4TOps())
191 return HighRegInst->getOpcode() == LowRegInst->getOpcode() &&
192 !isGreaterThan8BitTFRI(HighRegInst) &&
193 !isGreaterThan6BitTFRI(LowRegInst);
195 // There is no combine of two constant extended values.
196 if ((HighRegInst->getOpcode() == Hexagon::TFRI_V4 ||
197 isGreaterThan8BitTFRI(HighRegInst)) &&
198 (LowRegInst->getOpcode() == Hexagon::TFRI_V4 ||
199 isGreaterThan6BitTFRI(LowRegInst)))
205 static bool isEvenReg(unsigned Reg) {
206 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
207 Hexagon::IntRegsRegClass.contains(Reg));
208 return (Reg - Hexagon::R0) % 2 == 0;
211 static void removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) {
212 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
213 MachineOperand &Op = MI->getOperand(I);
214 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
220 /// isUnsafeToMoveAccross - Returns true if it is unsafe to move a copy
221 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
222 static bool isUnsafeToMoveAccross(MachineInstr *I, unsigned UseReg,
224 const TargetRegisterInfo *TRI) {
225 return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
226 I->modifiesRegister(DestReg, TRI) ||
227 I->readsRegister(DestReg, TRI) ||
228 I->hasUnmodeledSideEffects() ||
229 I->isInlineAsm() || I->isDebugValue();
232 /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
233 /// that the two instructions can be paired in a combine.
234 bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
238 bool &DoInsertAtI1) {
240 bool IsImmUseReg = I2->getOperand(1).isImm() || I2->getOperand(1).isGlobal();
241 unsigned I2UseReg = IsImmUseReg ? 0 : I2->getOperand(1).getReg();
243 // It is not safe to move I1 and I2 into one combine if I2 has a true
245 if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
250 // First try to move I2 towards I1.
252 // A reverse_iterator instantiated like below starts before I2, and I1
254 // Look at instructions I in between I2 and (excluding) I1.
255 MachineBasicBlock::reverse_iterator I(I2),
256 End = --(MachineBasicBlock::reverse_iterator(I1));
257 // At 03 we got better results (dhrystone!) by being more conservative.
258 if (!ShouldCombineAggressively)
259 End = MachineBasicBlock::reverse_iterator(I1);
260 // If I2 kills its operand and we move I2 over an instruction that also
261 // uses I2's use reg we need to modify that (first) instruction to now kill
263 unsigned KilledOperand = 0;
264 if (I2->killsRegister(I2UseReg))
265 KilledOperand = I2UseReg;
266 MachineInstr *KillingInstr = 0;
268 for (; I != End; ++I) {
269 // If the intervening instruction I:
270 // * modifies I2's use reg
271 // * modifies I2's def reg
272 // * reads I2's def reg
273 // * or has unmodelled side effects
274 // we can't move I2 across it.
275 if (isUnsafeToMoveAccross(&*I, I2UseReg, I2DestReg, TRI)) {
280 // Update first use of the killed operand.
281 if (!KillingInstr && KilledOperand &&
282 I->readsRegister(KilledOperand, TRI))
286 // Update the intermediate instruction to with the kill flag.
288 bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
289 (void)Added; // supress compiler warning
290 assert(Added && "Must successfully update kill flag");
291 removeKillInfo(I2, KilledOperand);
298 // Try to move I1 towards I2.
300 // Look at instructions I in between I1 and (excluding) I2.
301 MachineBasicBlock::iterator I(I1), End(I2);
302 // At O3 we got better results (dhrystone) by being more conservative here.
303 if (!ShouldCombineAggressively)
304 End = llvm::next(MachineBasicBlock::iterator(I2));
305 IsImmUseReg = I1->getOperand(1).isImm() || I1->getOperand(1).isGlobal();
306 unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg();
307 // Track killed operands. If we move accross an instruction that kills our
308 // operand, we need to update the kill information on the moved I1. It kills
310 MachineInstr *KillingInstr = 0;
311 unsigned KilledOperand = 0;
314 // If the intervening instruction I:
315 // * modifies I1's use reg
316 // * modifies I1's def reg
317 // * reads I1's def reg
318 // * or has unmodelled side effects
319 // We introduce this special case because llvm has no api to remove a
320 // kill flag for a register (a removeRegisterKilled() analogous to
321 // addRegisterKilled) that handles aliased register correctly.
322 // * or has a killed aliased register use of I1's use reg
323 // %D4<def> = TFRI64 16
324 // %R6<def> = TFR %R9
325 // %R8<def> = KILL %R8, %D4<imp-use,kill>
326 // If we want to move R6 = across the KILL instruction we would have
327 // to remove the %D4<imp-use,kill> operand. For now, we are
328 // conservative and disallow the move.
329 // we can't move I1 across it.
330 if (isUnsafeToMoveAccross(I, I1UseReg, I1DestReg, TRI) ||
331 // Check for an aliased register kill. Bail out if we see one.
332 (!I->killsRegister(I1UseReg) && I->killsRegister(I1UseReg, TRI)))
335 // Check for an exact kill (registers match).
336 if (I1UseReg && I->killsRegister(I1UseReg)) {
337 assert(KillingInstr == 0 && "Should only see one killing instruction");
338 KilledOperand = I1UseReg;
343 removeKillInfo(KillingInstr, KilledOperand);
344 // Update I1 to set the kill flag. This flag will later be picked up by
345 // the new COMBINE instruction.
346 bool Added = I1->addRegisterKilled(KilledOperand, TRI);
347 (void)Added; // supress compiler warning
348 assert(Added && "Must successfully update kill flag");
350 DoInsertAtI1 = false;
356 /// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
357 /// newified. (A use of a 64 bit register define can not be newified)
359 HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
360 DenseMap<unsigned, MachineInstr *> LastDef;
361 for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
362 MachineInstr *MI = I;
363 // Mark TFRs that feed a potential new value store as such.
364 if(TII->mayBeNewStore(MI)) {
365 // Look for uses of TFR instructions.
366 for (unsigned OpdIdx = 0, OpdE = MI->getNumOperands(); OpdIdx != OpdE;
368 MachineOperand &Op = MI->getOperand(OpdIdx);
370 // Skip over anything except register uses.
371 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
374 // Look for the defining instruction.
375 unsigned Reg = Op.getReg();
376 MachineInstr *DefInst = LastDef[Reg];
379 if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
382 // Only close newifiable stores should influence the decision.
383 MachineBasicBlock::iterator It(DefInst);
384 unsigned NumInstsToDef = 0;
388 if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
391 PotentiallyNewifiableTFR.insert(DefInst);
393 // Skip to next instruction.
397 // Put instructions that last defined integer or double registers into the
399 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
400 MachineOperand &Op = MI->getOperand(I);
401 if (!Op.isReg() || !Op.isDef() || !Op.getReg())
403 unsigned Reg = Op.getReg();
404 if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
405 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
406 LastDef[*SubRegs] = MI;
408 } else if (Hexagon::IntRegsRegClass.contains(Reg))
414 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
416 if (IsCombinesDisabled) return false;
418 bool HasChanged = false;
421 TRI = MF.getTarget().getRegisterInfo();
422 TII = static_cast<const HexagonInstrInfo *>(MF.getTarget().getInstrInfo());
424 // Combine aggressively (for code size)
425 ShouldCombineAggressively =
426 MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
428 // Traverse basic blocks.
429 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
431 PotentiallyNewifiableTFR.clear();
432 findPotentialNewifiableTFRs(*BI);
434 // Traverse instructions in basic block.
435 for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
437 MachineInstr *I1 = MI++;
438 // Don't combine a TFR whose user could be newified (instructions that
439 // define double registers can not be newified - Programmer's Ref Manual
440 // 5.4.2 New-value stores).
441 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I1))
444 // Ignore instructions that are not combinable.
445 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
448 // Find a second instruction that can be merged into a combine
450 bool DoInsertAtI1 = false;
451 MachineInstr *I2 = findPairable(I1, DoInsertAtI1);
454 combine(I1, I2, MI, DoInsertAtI1);
462 /// findPairable - Returns an instruction that can be merged with \p I1 into a
463 /// COMBINE instruction or 0 if no such instruction can be found. Returns true
464 /// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
465 /// false if the combine must be inserted at the returned instruction.
466 MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
467 bool &DoInsertAtI1) {
468 MachineBasicBlock::iterator I2 = llvm::next(MachineBasicBlock::iterator(I1));
469 unsigned I1DestReg = I1->getOperand(0).getReg();
471 for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
473 // Bail out early if we see a second definition of I1DestReg.
474 if (I2->modifiesRegister(I1DestReg, TRI))
477 // Ignore non-combinable instructions.
478 if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
481 // Don't combine a TFR whose user could be newified.
482 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I2))
485 unsigned I2DestReg = I2->getOperand(0).getReg();
487 // Check that registers are adjacent and that the first destination register
489 bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
490 bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
491 unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
492 if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
495 // Check that the two instructions are combinable. V4 allows more
496 // instructions to be merged into a combine.
497 // The order matters because in a TFRI we might can encode a int8 as the
498 // hi reg operand but only a uint6 as the low reg operand.
499 if ((IsI2LowReg && !areCombinableOperations(TRI, I1, I2)) ||
500 (IsI1LowReg && !areCombinableOperations(TRI, I2, I1)))
503 if (isSafeToMoveTogether(I1, I2, I1DestReg, I2DestReg,
507 // Not safe. Stop searching.
513 void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
514 MachineBasicBlock::iterator &MI,
516 // We are going to delete I2. If MI points to I2 advance it to the next
518 if ((MachineInstr *)MI == I2) ++MI;
520 // Figure out whether I1 or I2 goes into the lowreg part.
521 unsigned I1DestReg = I1->getOperand(0).getReg();
522 unsigned I2DestReg = I2->getOperand(0).getReg();
523 bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
524 unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
526 // Get the double word register.
527 unsigned DoubleRegDest =
528 TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg,
529 &Hexagon::DoubleRegsRegClass);
530 assert(DoubleRegDest != 0 && "Expect a valid register");
533 // Setup source operands.
534 MachineOperand &LoOperand = IsI1Loreg ? I1->getOperand(1) :
536 MachineOperand &HiOperand = IsI1Loreg ? I2->getOperand(1) :
539 // Figure out which source is a register and which a constant.
540 bool IsHiReg = HiOperand.isReg();
541 bool IsLoReg = LoOperand.isReg();
543 MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
545 if (IsHiReg && IsLoReg)
546 emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
548 emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
550 emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
552 emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
554 I1->eraseFromParent();
555 I2->eraseFromParent();
558 void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
559 unsigned DoubleDestReg,
560 MachineOperand &HiOperand,
561 MachineOperand &LoOperand) {
562 DebugLoc DL = InsertPt->getDebugLoc();
563 MachineBasicBlock *BB = InsertPt->getParent();
566 if (HiOperand.isGlobal()) {
567 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
568 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
569 HiOperand.getTargetFlags())
570 .addImm(LoOperand.getImm());
573 if (LoOperand.isGlobal()) {
574 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
575 .addImm(HiOperand.getImm())
576 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
577 LoOperand.getTargetFlags());
581 // Handle constant extended immediates.
582 if (!isInt<8>(HiOperand.getImm())) {
583 assert(isInt<8>(LoOperand.getImm()));
584 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
585 .addImm(HiOperand.getImm())
586 .addImm(LoOperand.getImm());
590 if (!isUInt<6>(LoOperand.getImm())) {
591 assert(isInt<8>(HiOperand.getImm()));
592 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_iI_V4), DoubleDestReg)
593 .addImm(HiOperand.getImm())
594 .addImm(LoOperand.getImm());
598 // Insert new combine instruction.
599 // DoubleRegDest = combine #HiImm, #LoImm
600 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ii), DoubleDestReg)
601 .addImm(HiOperand.getImm())
602 .addImm(LoOperand.getImm());
605 void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
606 unsigned DoubleDestReg,
607 MachineOperand &HiOperand,
608 MachineOperand &LoOperand) {
609 unsigned LoReg = LoOperand.getReg();
610 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
612 DebugLoc DL = InsertPt->getDebugLoc();
613 MachineBasicBlock *BB = InsertPt->getParent();
616 if (HiOperand.isGlobal()) {
617 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg)
618 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
619 HiOperand.getTargetFlags())
620 .addReg(LoReg, LoRegKillFlag);
623 // Insert new combine instruction.
624 // DoubleRegDest = combine #HiImm, LoReg
625 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_Ir_V4), DoubleDestReg)
626 .addImm(HiOperand.getImm())
627 .addReg(LoReg, LoRegKillFlag);
630 void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
631 unsigned DoubleDestReg,
632 MachineOperand &HiOperand,
633 MachineOperand &LoOperand) {
634 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
635 unsigned HiReg = HiOperand.getReg();
637 DebugLoc DL = InsertPt->getDebugLoc();
638 MachineBasicBlock *BB = InsertPt->getParent();
641 if (LoOperand.isGlobal()) {
642 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg)
643 .addReg(HiReg, HiRegKillFlag)
644 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
645 LoOperand.getTargetFlags());
649 // Insert new combine instruction.
650 // DoubleRegDest = combine HiReg, #LoImm
651 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rI_V4), DoubleDestReg)
652 .addReg(HiReg, HiRegKillFlag)
653 .addImm(LoOperand.getImm());
656 void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
657 unsigned DoubleDestReg,
658 MachineOperand &HiOperand,
659 MachineOperand &LoOperand) {
660 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
661 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
662 unsigned LoReg = LoOperand.getReg();
663 unsigned HiReg = HiOperand.getReg();
665 DebugLoc DL = InsertPt->getDebugLoc();
666 MachineBasicBlock *BB = InsertPt->getParent();
668 // Insert new combine instruction.
669 // DoubleRegDest = combine HiReg, LoReg
670 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::COMBINE_rr), DoubleDestReg)
671 .addReg(HiReg, HiRegKillFlag)
672 .addReg(LoReg, LoRegKillFlag);
675 FunctionPass *llvm::createHexagonCopyToCombine() {
676 return new HexagonCopyToCombine();