1 //===------- HexagonCopyToCombine.cpp - Hexagon Copy-To-Combine Pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This pass replaces transfer instructions by combine instructions.
10 // We walk along a basic block and look for two combinable instructions and try
11 // to move them together. If we can move them next to each other we do so and
12 // replace them with a combine instruction.
13 //===----------------------------------------------------------------------===//
14 #include "llvm/PassSupport.h"
16 #include "HexagonInstrInfo.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonRegisterInfo.h"
19 #include "HexagonSubtarget.h"
20 #include "HexagonTargetMachine.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/DenseSet.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/Support/CodeGen.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
37 #define DEBUG_TYPE "hexagon-copy-combine"
40 cl::opt<bool> IsCombinesDisabled("disable-merge-into-combines",
41 cl::Hidden, cl::ZeroOrMore,
43 cl::desc("Disable merging into combines"));
46 MaxNumOfInstsBetweenNewValueStoreAndTFR("max-num-inst-between-tfr-and-nv-store",
47 cl::Hidden, cl::init(4),
48 cl::desc("Maximum distance between a tfr feeding a store we "
49 "consider the store still to be newifiable"));
52 void initializeHexagonCopyToCombinePass(PassRegistry&);
58 class HexagonCopyToCombine : public MachineFunctionPass {
59 const HexagonInstrInfo *TII;
60 const TargetRegisterInfo *TRI;
61 bool ShouldCombineAggressively;
63 DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
67 HexagonCopyToCombine() : MachineFunctionPass(ID) {
68 initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
71 void getAnalysisUsage(AnalysisUsage &AU) const override {
72 MachineFunctionPass::getAnalysisUsage(AU);
75 const char *getPassName() const override {
76 return "Hexagon Copy-To-Combine Pass";
79 bool runOnMachineFunction(MachineFunction &Fn) override;
82 MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);
84 void findPotentialNewifiableTFRs(MachineBasicBlock &);
86 void combine(MachineInstr *I1, MachineInstr *I2,
87 MachineBasicBlock::iterator &MI, bool DoInsertAtI1);
89 bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2,
90 unsigned I1DestReg, unsigned I2DestReg,
93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
94 MachineOperand &HiOperand, MachineOperand &LoOperand);
96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
97 MachineOperand &HiOperand, MachineOperand &LoOperand);
99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
100 MachineOperand &HiOperand, MachineOperand &LoOperand);
102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
103 MachineOperand &HiOperand, MachineOperand &LoOperand);
106 } // End anonymous namespace.
108 char HexagonCopyToCombine::ID = 0;
110 INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
111 "Hexagon Copy-To-Combine Pass", false, false)
113 static bool isCombinableInstType(MachineInstr *MI,
114 const HexagonInstrInfo *TII,
115 bool ShouldCombineAggressively) {
116 switch(MI->getOpcode()) {
117 case Hexagon::A2_tfr: {
118 // A COPY instruction can be combined if its arguments are IntRegs (32bit).
119 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg());
121 unsigned DestReg = MI->getOperand(0).getReg();
122 unsigned SrcReg = MI->getOperand(1).getReg();
123 return Hexagon::IntRegsRegClass.contains(DestReg) &&
124 Hexagon::IntRegsRegClass.contains(SrcReg);
127 case Hexagon::A2_tfrsi: {
128 // A transfer-immediate can be combined if its argument is a signed 8bit
130 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
131 unsigned DestReg = MI->getOperand(0).getReg();
133 // Only combine constant extended TFRI if we are in aggressive mode.
134 return Hexagon::IntRegsRegClass.contains(DestReg) &&
135 (ShouldCombineAggressively || isInt<8>(MI->getOperand(1).getImm()));
138 case Hexagon::TFRI_V4: {
139 if (!ShouldCombineAggressively)
141 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal());
143 // Ensure that TargetFlags are MO_NO_FLAG for a global. This is a
144 // workaround for an ABI bug that prevents GOT relocations on combine
146 if (MI->getOperand(1).getTargetFlags() != HexagonII::MO_NO_FLAG)
149 unsigned DestReg = MI->getOperand(0).getReg();
150 return Hexagon::IntRegsRegClass.contains(DestReg);
160 static bool isGreaterThan8BitTFRI(MachineInstr *I) {
161 return I->getOpcode() == Hexagon::A2_tfrsi &&
162 !isInt<8>(I->getOperand(1).getImm());
164 static bool isGreaterThan6BitTFRI(MachineInstr *I) {
165 return I->getOpcode() == Hexagon::A2_tfrsi &&
166 !isUInt<6>(I->getOperand(1).getImm());
169 /// areCombinableOperations - Returns true if the two instruction can be merge
170 /// into a combine (ignoring register constraints).
171 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
172 MachineInstr *HighRegInst,
173 MachineInstr *LowRegInst) {
174 assert((HighRegInst->getOpcode() == Hexagon::A2_tfr ||
175 HighRegInst->getOpcode() == Hexagon::A2_tfrsi ||
176 HighRegInst->getOpcode() == Hexagon::TFRI_V4) &&
177 (LowRegInst->getOpcode() == Hexagon::A2_tfr ||
178 LowRegInst->getOpcode() == Hexagon::A2_tfrsi ||
179 LowRegInst->getOpcode() == Hexagon::TFRI_V4) &&
180 "Assume individual instructions are of a combinable type");
182 // There is no combine of two constant extended values.
183 if ((HighRegInst->getOpcode() == Hexagon::TFRI_V4 ||
184 isGreaterThan8BitTFRI(HighRegInst)) &&
185 (LowRegInst->getOpcode() == Hexagon::TFRI_V4 ||
186 isGreaterThan6BitTFRI(LowRegInst)))
192 static bool isEvenReg(unsigned Reg) {
193 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
194 Hexagon::IntRegsRegClass.contains(Reg));
195 return (Reg - Hexagon::R0) % 2 == 0;
198 static void removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) {
199 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
200 MachineOperand &Op = MI->getOperand(I);
201 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
207 /// isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy
208 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
209 static bool isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg,
211 const TargetRegisterInfo *TRI) {
212 return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
213 I->modifiesRegister(DestReg, TRI) ||
214 I->readsRegister(DestReg, TRI) ||
215 I->hasUnmodeledSideEffects() ||
216 I->isInlineAsm() || I->isDebugValue();
219 /// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
220 /// that the two instructions can be paired in a combine.
221 bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
225 bool &DoInsertAtI1) {
227 bool IsImmUseReg = I2->getOperand(1).isImm() || I2->getOperand(1).isGlobal();
228 unsigned I2UseReg = IsImmUseReg ? 0 : I2->getOperand(1).getReg();
230 // It is not safe to move I1 and I2 into one combine if I2 has a true
232 if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
237 // First try to move I2 towards I1.
239 // A reverse_iterator instantiated like below starts before I2, and I1
241 // Look at instructions I in between I2 and (excluding) I1.
242 MachineBasicBlock::reverse_iterator I(I2),
243 End = --(MachineBasicBlock::reverse_iterator(I1));
244 // At 03 we got better results (dhrystone!) by being more conservative.
245 if (!ShouldCombineAggressively)
246 End = MachineBasicBlock::reverse_iterator(I1);
247 // If I2 kills its operand and we move I2 over an instruction that also
248 // uses I2's use reg we need to modify that (first) instruction to now kill
250 unsigned KilledOperand = 0;
251 if (I2->killsRegister(I2UseReg))
252 KilledOperand = I2UseReg;
253 MachineInstr *KillingInstr = nullptr;
255 for (; I != End; ++I) {
256 // If the intervening instruction I:
257 // * modifies I2's use reg
258 // * modifies I2's def reg
259 // * reads I2's def reg
260 // * or has unmodelled side effects
261 // we can't move I2 across it.
262 if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
267 // Update first use of the killed operand.
268 if (!KillingInstr && KilledOperand &&
269 I->readsRegister(KilledOperand, TRI))
273 // Update the intermediate instruction to with the kill flag.
275 bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true);
276 (void)Added; // suppress compiler warning
277 assert(Added && "Must successfully update kill flag");
278 removeKillInfo(I2, KilledOperand);
285 // Try to move I1 towards I2.
287 // Look at instructions I in between I1 and (excluding) I2.
288 MachineBasicBlock::iterator I(I1), End(I2);
289 // At O3 we got better results (dhrystone) by being more conservative here.
290 if (!ShouldCombineAggressively)
291 End = std::next(MachineBasicBlock::iterator(I2));
292 IsImmUseReg = I1->getOperand(1).isImm() || I1->getOperand(1).isGlobal();
293 unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg();
294 // Track killed operands. If we move across an instruction that kills our
295 // operand, we need to update the kill information on the moved I1. It kills
297 MachineInstr *KillingInstr = nullptr;
298 unsigned KilledOperand = 0;
301 // If the intervening instruction I:
302 // * modifies I1's use reg
303 // * modifies I1's def reg
304 // * reads I1's def reg
305 // * or has unmodelled side effects
306 // We introduce this special case because llvm has no api to remove a
307 // kill flag for a register (a removeRegisterKilled() analogous to
308 // addRegisterKilled) that handles aliased register correctly.
309 // * or has a killed aliased register use of I1's use reg
310 // %D4<def> = TFRI64 16
311 // %R6<def> = TFR %R9
312 // %R8<def> = KILL %R8, %D4<imp-use,kill>
313 // If we want to move R6 = across the KILL instruction we would have
314 // to remove the %D4<imp-use,kill> operand. For now, we are
315 // conservative and disallow the move.
316 // we can't move I1 across it.
317 if (isUnsafeToMoveAcross(I, I1UseReg, I1DestReg, TRI) ||
318 // Check for an aliased register kill. Bail out if we see one.
319 (!I->killsRegister(I1UseReg) && I->killsRegister(I1UseReg, TRI)))
322 // Check for an exact kill (registers match).
323 if (I1UseReg && I->killsRegister(I1UseReg)) {
324 assert(!KillingInstr && "Should only see one killing instruction");
325 KilledOperand = I1UseReg;
330 removeKillInfo(KillingInstr, KilledOperand);
331 // Update I1 to set the kill flag. This flag will later be picked up by
332 // the new COMBINE instruction.
333 bool Added = I1->addRegisterKilled(KilledOperand, TRI);
334 (void)Added; // suppress compiler warning
335 assert(Added && "Must successfully update kill flag");
337 DoInsertAtI1 = false;
343 /// findPotentialNewifiableTFRs - Finds tranfers that feed stores that could be
344 /// newified. (A use of a 64 bit register define can not be newified)
346 HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
347 DenseMap<unsigned, MachineInstr *> LastDef;
348 for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
349 MachineInstr *MI = I;
350 // Mark TFRs that feed a potential new value store as such.
351 if(TII->mayBeNewStore(MI)) {
352 // Look for uses of TFR instructions.
353 for (unsigned OpdIdx = 0, OpdE = MI->getNumOperands(); OpdIdx != OpdE;
355 MachineOperand &Op = MI->getOperand(OpdIdx);
357 // Skip over anything except register uses.
358 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
361 // Look for the defining instruction.
362 unsigned Reg = Op.getReg();
363 MachineInstr *DefInst = LastDef[Reg];
366 if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
369 // Only close newifiable stores should influence the decision.
370 MachineBasicBlock::iterator It(DefInst);
371 unsigned NumInstsToDef = 0;
375 if (NumInstsToDef > MaxNumOfInstsBetweenNewValueStoreAndTFR)
378 PotentiallyNewifiableTFR.insert(DefInst);
380 // Skip to next instruction.
384 // Put instructions that last defined integer or double registers into the
386 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
387 MachineOperand &Op = MI->getOperand(I);
388 if (!Op.isReg() || !Op.isDef() || !Op.getReg())
390 unsigned Reg = Op.getReg();
391 if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
392 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
393 LastDef[*SubRegs] = MI;
395 } else if (Hexagon::IntRegsRegClass.contains(Reg))
401 bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
403 if (IsCombinesDisabled) return false;
405 bool HasChanged = false;
408 TRI = MF.getSubtarget().getRegisterInfo();
409 TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
411 // Combine aggressively (for code size)
412 ShouldCombineAggressively =
413 MF.getTarget().getOptLevel() <= CodeGenOpt::Default;
415 // Traverse basic blocks.
416 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); BI != BE;
418 PotentiallyNewifiableTFR.clear();
419 findPotentialNewifiableTFRs(*BI);
421 // Traverse instructions in basic block.
422 for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
424 MachineInstr *I1 = MI++;
425 // Don't combine a TFR whose user could be newified (instructions that
426 // define double registers can not be newified - Programmer's Ref Manual
427 // 5.4.2 New-value stores).
428 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I1))
431 // Ignore instructions that are not combinable.
432 if (!isCombinableInstType(I1, TII, ShouldCombineAggressively))
435 // Find a second instruction that can be merged into a combine
437 bool DoInsertAtI1 = false;
438 MachineInstr *I2 = findPairable(I1, DoInsertAtI1);
441 combine(I1, I2, MI, DoInsertAtI1);
449 /// findPairable - Returns an instruction that can be merged with \p I1 into a
450 /// COMBINE instruction or 0 if no such instruction can be found. Returns true
451 /// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
452 /// false if the combine must be inserted at the returned instruction.
453 MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
454 bool &DoInsertAtI1) {
455 MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
456 unsigned I1DestReg = I1->getOperand(0).getReg();
458 for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
460 // Bail out early if we see a second definition of I1DestReg.
461 if (I2->modifiesRegister(I1DestReg, TRI))
464 // Ignore non-combinable instructions.
465 if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
468 // Don't combine a TFR whose user could be newified.
469 if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I2))
472 unsigned I2DestReg = I2->getOperand(0).getReg();
474 // Check that registers are adjacent and that the first destination register
476 bool IsI1LowReg = (I2DestReg - I1DestReg) == 1;
477 bool IsI2LowReg = (I1DestReg - I2DestReg) == 1;
478 unsigned FirstRegIndex = IsI1LowReg ? I1DestReg : I2DestReg;
479 if ((!IsI1LowReg && !IsI2LowReg) || !isEvenReg(FirstRegIndex))
482 // Check that the two instructions are combinable. V4 allows more
483 // instructions to be merged into a combine.
484 // The order matters because in a TFRI we might can encode a int8 as the
485 // hi reg operand but only a uint6 as the low reg operand.
486 if ((IsI2LowReg && !areCombinableOperations(TRI, I1, I2)) ||
487 (IsI1LowReg && !areCombinableOperations(TRI, I2, I1)))
490 if (isSafeToMoveTogether(I1, I2, I1DestReg, I2DestReg,
494 // Not safe. Stop searching.
500 void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
501 MachineBasicBlock::iterator &MI,
503 // We are going to delete I2. If MI points to I2 advance it to the next
505 if ((MachineInstr *)MI == I2) ++MI;
507 // Figure out whether I1 or I2 goes into the lowreg part.
508 unsigned I1DestReg = I1->getOperand(0).getReg();
509 unsigned I2DestReg = I2->getOperand(0).getReg();
510 bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
511 unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
513 // Get the double word register.
514 unsigned DoubleRegDest =
515 TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg,
516 &Hexagon::DoubleRegsRegClass);
517 assert(DoubleRegDest != 0 && "Expect a valid register");
520 // Setup source operands.
521 MachineOperand &LoOperand = IsI1Loreg ? I1->getOperand(1) :
523 MachineOperand &HiOperand = IsI1Loreg ? I2->getOperand(1) :
526 // Figure out which source is a register and which a constant.
527 bool IsHiReg = HiOperand.isReg();
528 bool IsLoReg = LoOperand.isReg();
530 MachineBasicBlock::iterator InsertPt(DoInsertAtI1 ? I1 : I2);
532 if (IsHiReg && IsLoReg)
533 emitCombineRR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
535 emitCombineRI(InsertPt, DoubleRegDest, HiOperand, LoOperand);
537 emitCombineIR(InsertPt, DoubleRegDest, HiOperand, LoOperand);
539 emitCombineII(InsertPt, DoubleRegDest, HiOperand, LoOperand);
541 I1->eraseFromParent();
542 I2->eraseFromParent();
545 void HexagonCopyToCombine::emitCombineII(MachineBasicBlock::iterator &InsertPt,
546 unsigned DoubleDestReg,
547 MachineOperand &HiOperand,
548 MachineOperand &LoOperand) {
549 DebugLoc DL = InsertPt->getDebugLoc();
550 MachineBasicBlock *BB = InsertPt->getParent();
553 if (HiOperand.isGlobal()) {
554 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
555 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
556 HiOperand.getTargetFlags())
557 .addImm(LoOperand.getImm());
560 if (LoOperand.isGlobal()) {
561 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
562 .addImm(HiOperand.getImm())
563 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
564 LoOperand.getTargetFlags());
568 // Handle constant extended immediates.
569 if (!isInt<8>(HiOperand.getImm())) {
570 assert(isInt<8>(LoOperand.getImm()));
571 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
572 .addImm(HiOperand.getImm())
573 .addImm(LoOperand.getImm());
577 if (!isUInt<6>(LoOperand.getImm())) {
578 assert(isInt<8>(HiOperand.getImm()));
579 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
580 .addImm(HiOperand.getImm())
581 .addImm(LoOperand.getImm());
585 // Insert new combine instruction.
586 // DoubleRegDest = combine #HiImm, #LoImm
587 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
588 .addImm(HiOperand.getImm())
589 .addImm(LoOperand.getImm());
592 void HexagonCopyToCombine::emitCombineIR(MachineBasicBlock::iterator &InsertPt,
593 unsigned DoubleDestReg,
594 MachineOperand &HiOperand,
595 MachineOperand &LoOperand) {
596 unsigned LoReg = LoOperand.getReg();
597 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
599 DebugLoc DL = InsertPt->getDebugLoc();
600 MachineBasicBlock *BB = InsertPt->getParent();
603 if (HiOperand.isGlobal()) {
604 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
605 .addGlobalAddress(HiOperand.getGlobal(), HiOperand.getOffset(),
606 HiOperand.getTargetFlags())
607 .addReg(LoReg, LoRegKillFlag);
610 // Insert new combine instruction.
611 // DoubleRegDest = combine #HiImm, LoReg
612 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
613 .addImm(HiOperand.getImm())
614 .addReg(LoReg, LoRegKillFlag);
617 void HexagonCopyToCombine::emitCombineRI(MachineBasicBlock::iterator &InsertPt,
618 unsigned DoubleDestReg,
619 MachineOperand &HiOperand,
620 MachineOperand &LoOperand) {
621 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
622 unsigned HiReg = HiOperand.getReg();
624 DebugLoc DL = InsertPt->getDebugLoc();
625 MachineBasicBlock *BB = InsertPt->getParent();
628 if (LoOperand.isGlobal()) {
629 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
630 .addReg(HiReg, HiRegKillFlag)
631 .addGlobalAddress(LoOperand.getGlobal(), LoOperand.getOffset(),
632 LoOperand.getTargetFlags());
636 // Insert new combine instruction.
637 // DoubleRegDest = combine HiReg, #LoImm
638 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
639 .addReg(HiReg, HiRegKillFlag)
640 .addImm(LoOperand.getImm());
643 void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
644 unsigned DoubleDestReg,
645 MachineOperand &HiOperand,
646 MachineOperand &LoOperand) {
647 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
648 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
649 unsigned LoReg = LoOperand.getReg();
650 unsigned HiReg = HiOperand.getReg();
652 DebugLoc DL = InsertPt->getDebugLoc();
653 MachineBasicBlock *BB = InsertPt->getParent();
655 // Insert new combine instruction.
656 // DoubleRegDest = combine HiReg, LoReg
657 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combinew), DoubleDestReg)
658 .addReg(HiReg, HiRegKillFlag)
659 .addReg(LoReg, LoRegKillFlag);
662 FunctionPass *llvm::createHexagonCopyToCombine() {
663 return new HexagonCopyToCombine();