1 //===--- HexagonExpandCondsets.cpp ----------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Replace mux instructions with the corresponding legal instructions.
11 // It is meant to work post-SSA, but still on virtual registers. It was
12 // originally placed between register coalescing and machine instruction
14 // In this place in the optimization sequence, live interval analysis had
15 // been performed, and the live intervals should be preserved. A large part
16 // of the code deals with preserving the liveness information.
18 // Liveness tracking aside, the main functionality of this pass is divided
19 // into two steps. The first step is to replace an instruction
20 // vreg0 = C2_mux vreg0, vreg1, vreg2
21 // with a pair of conditional transfers
22 // vreg0 = A2_tfrt vreg0, vreg1
23 // vreg0 = A2_tfrf vreg0, vreg2
24 // It is the intention that the execution of this pass could be terminated
25 // after this step, and the code generated would be functionally correct.
27 // If the uses of the source values vreg1 and vreg2 are kills, and their
28 // definitions are predicable, then in the second step, the conditional
29 // transfers will then be rewritten as predicated instructions. E.g.
30 // vreg0 = A2_or vreg1, vreg2
31 // vreg3 = A2_tfrt vreg99, vreg0<kill>
32 // will be rewritten as
33 // vreg3 = A2_port vreg99, vreg1, vreg2
35 // This replacement has two variants: "up" and "down". Consider this case:
36 // vreg0 = A2_or vreg1, vreg2
37 // ... [intervening instructions] ...
38 // vreg3 = A2_tfrt vreg99, vreg0<kill>
40 // vreg3 = A2_port vreg99, vreg1, vreg2
41 // ... [intervening instructions, vreg0->vreg3] ...
45 // ... [intervening instructions] ...
46 // vreg3 = A2_port vreg99, vreg1, vreg2
48 // Both, one or none of these variants may be valid, and checks are made
49 // to rule out inapplicable variants.
51 // As an additional optimization, before either of the two steps above is
52 // executed, the pass attempts to coalesce the target register with one of
53 // the source registers, e.g. given an instruction
54 // vreg3 = C2_mux vreg0, vreg1, vreg2
55 // vreg3 will be coalesced with either vreg1 or vreg2. If this succeeds,
56 // the instruction would then be (for example)
57 // vreg3 = C2_mux vreg0, vreg3, vreg2
58 // and, under certain circumstances, this could result in only one predicated
60 // vreg3 = A2_tfrf vreg0, vreg2
63 #define DEBUG_TYPE "expand-condsets"
64 #include "HexagonTargetMachine.h"
66 #include "llvm/CodeGen/Passes.h"
67 #include "llvm/CodeGen/LiveInterval.h"
68 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
69 #include "llvm/CodeGen/MachineFunction.h"
70 #include "llvm/CodeGen/MachineInstrBuilder.h"
71 #include "llvm/CodeGen/MachineRegisterInfo.h"
72 #include "llvm/Target/TargetInstrInfo.h"
73 #include "llvm/Target/TargetMachine.h"
74 #include "llvm/Target/TargetRegisterInfo.h"
75 #include "llvm/Support/CommandLine.h"
76 #include "llvm/Support/Debug.h"
77 #include "llvm/Support/raw_ostream.h"
81 static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit",
82 cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"));
83 static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit",
84 cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"));
87 void initializeHexagonExpandCondsetsPass(PassRegistry&);
88 FunctionPass *createHexagonExpandCondsets();
92 class HexagonExpandCondsets : public MachineFunctionPass {
95 HexagonExpandCondsets() :
96 MachineFunctionPass(ID), HII(0), TRI(0), MRI(0),
97 LIS(0), CoaLimitActive(false),
98 TfrLimitActive(false), CoaCounter(0), TfrCounter(0) {
99 if (OptCoaLimit.getPosition())
100 CoaLimitActive = true, CoaLimit = OptCoaLimit;
101 if (OptTfrLimit.getPosition())
102 TfrLimitActive = true, TfrLimit = OptTfrLimit;
103 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
106 virtual const char *getPassName() const {
107 return "Hexagon Expand Condsets";
109 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
110 AU.addRequired<LiveIntervals>();
111 AU.addPreserved<LiveIntervals>();
112 AU.addPreserved<SlotIndexes>();
113 MachineFunctionPass::getAnalysisUsage(AU);
115 virtual bool runOnMachineFunction(MachineFunction &MF);
118 const HexagonInstrInfo *HII;
119 const TargetRegisterInfo *TRI;
120 MachineRegisterInfo *MRI;
123 bool CoaLimitActive, TfrLimitActive;
124 unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter;
127 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
128 Sub(Op.getSubReg()) {}
129 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
130 bool operator== (RegisterRef RR) const {
131 return Reg == RR.Reg && Sub == RR.Sub;
133 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
137 typedef DenseMap<unsigned,unsigned> ReferenceMap;
138 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
139 enum { Exec_Then = 0x10, Exec_Else = 0x20 };
140 unsigned getMaskForSub(unsigned Sub);
141 bool isCondset(const MachineInstr *MI);
143 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
144 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
146 LiveInterval::iterator nextSegment(LiveInterval &LI, SlotIndex S);
147 LiveInterval::iterator prevSegment(LiveInterval &LI, SlotIndex S);
148 void makeDefined(unsigned Reg, SlotIndex S, bool SetDef);
149 void makeUndead(unsigned Reg, SlotIndex S);
150 void shrinkToUses(unsigned Reg, LiveInterval &LI);
151 void updateKillFlags(unsigned Reg, LiveInterval &LI);
152 void terminateSegment(LiveInterval::iterator LT, SlotIndex S,
154 void addInstrToLiveness(MachineInstr *MI);
155 void removeInstrFromLiveness(MachineInstr *MI);
157 unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
158 MachineInstr *genTfrFor(MachineOperand &SrcOp, unsigned DstR,
159 unsigned DstSR, const MachineOperand &PredOp, bool Cond);
160 bool split(MachineInstr *MI);
161 bool splitInBlock(MachineBasicBlock &B);
163 bool isPredicable(MachineInstr *MI);
164 MachineInstr *getReachingDefForPred(RegisterRef RD,
165 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
166 bool canMoveOver(MachineInstr *MI, ReferenceMap &Defs, ReferenceMap &Uses);
167 bool canMoveMemTo(MachineInstr *MI, MachineInstr *ToI, bool IsDown);
168 void predicateAt(RegisterRef RD, MachineInstr *MI,
169 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond);
170 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
171 bool Cond, MachineBasicBlock::iterator First,
172 MachineBasicBlock::iterator Last);
173 bool predicate(MachineInstr *TfrI, bool Cond);
174 bool predicateInBlock(MachineBasicBlock &B);
176 void postprocessUndefImplicitUses(MachineBasicBlock &B);
177 void removeImplicitUses(MachineInstr *MI);
178 void removeImplicitUses(MachineBasicBlock &B);
180 bool isIntReg(RegisterRef RR, unsigned &BW);
181 bool isIntraBlocks(LiveInterval &LI);
182 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
183 bool coalesceSegments(MachineFunction &MF);
187 char HexagonExpandCondsets::ID = 0;
190 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
192 case Hexagon::subreg_loreg:
194 case Hexagon::subreg_hireg:
196 case Hexagon::NoSubRegister:
199 llvm_unreachable("Invalid subregister");
203 bool HexagonExpandCondsets::isCondset(const MachineInstr *MI) {
204 unsigned Opc = MI->getOpcode();
206 case Hexagon::C2_mux:
207 case Hexagon::C2_muxii:
208 case Hexagon::C2_muxir:
209 case Hexagon::C2_muxri:
210 case Hexagon::MUX64_rr:
218 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
220 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
221 ReferenceMap::iterator F = Map.find(RR.Reg);
223 Map.insert(std::make_pair(RR.Reg, Mask));
229 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
231 ReferenceMap::iterator F = Map.find(RR.Reg);
234 unsigned Mask = getMaskForSub(RR.Sub) | Exec;
235 if (Mask & F->second)
241 LiveInterval::iterator HexagonExpandCondsets::nextSegment(LiveInterval &LI,
243 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
251 LiveInterval::iterator HexagonExpandCondsets::prevSegment(LiveInterval &LI,
253 LiveInterval::iterator P = LI.end();
254 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
263 /// Find the implicit use of register Reg in slot index S, and make sure
264 /// that the "defined" flag is set to SetDef. While the mux expansion is
265 /// going on, predicated instructions will have implicit uses of the
266 /// registers that are being defined. This is to keep any preceding
267 /// definitions live. If there is no preceding definition, the implicit
268 /// use will be marked as "undef", otherwise it will be "defined". This
269 /// function is used to update the flag.
270 void HexagonExpandCondsets::makeDefined(unsigned Reg, SlotIndex S,
274 MachineInstr *MI = LIS->getInstructionFromIndex(S);
275 assert(MI && "Expecting instruction");
276 for (auto &Op : MI->operands()) {
277 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
279 bool IsDef = !Op.isUndef();
280 if (Op.isImplicit() && IsDef != SetDef)
281 Op.setIsUndef(!SetDef);
286 void HexagonExpandCondsets::makeUndead(unsigned Reg, SlotIndex S) {
287 // If S is a block boundary, then there can still be a dead def reaching
288 // this point. Instead of traversing the CFG, queue start points of all
289 // live segments that begin with a register, and end at a block boundary.
290 // This may "resurrect" some truly dead definitions, but doing so is
292 SmallVector<MachineInstr*,8> Defs;
294 LiveInterval &LI = LIS->getInterval(Reg);
295 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
296 if (!I->start.isRegister() || !I->end.isBlock())
298 MachineInstr *MI = LIS->getInstructionFromIndex(I->start);
301 } else if (S.isRegister()) {
302 MachineInstr *MI = LIS->getInstructionFromIndex(S);
306 for (unsigned i = 0, n = Defs.size(); i < n; ++i) {
307 MachineInstr *MI = Defs[i];
308 for (auto &Op : MI->operands()) {
309 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
317 /// Shrink the segments in the live interval for a given register to the last
318 /// use before each subsequent def. Unlike LiveIntervals::shrinkToUses, this
319 /// function will not mark any definitions of Reg as dead. The reason for this
320 /// is that this function is used while a MUX instruction is being expanded,
321 /// or while a conditional copy is undergoing predication. During these
322 /// processes, there may be defs present in the instruction sequence that have
323 /// not yet been removed, or there may be missing uses that have not yet been
324 /// added. We want to utilize LiveIntervals::shrinkToUses as much as possible,
325 /// but since it does not extend any intervals that are too short, we need to
326 /// pre-emptively extend them here in anticipation of further changes.
327 void HexagonExpandCondsets::shrinkToUses(unsigned Reg, LiveInterval &LI) {
328 SmallVector<MachineInstr*,4> Deads;
329 LIS->shrinkToUses(&LI, &Deads);
330 // Need to undo the deadification made by "shrinkToUses". It's easier to
331 // do it here, since we have a list of all instructions that were just
333 for (unsigned i = 0, n = Deads.size(); i < n; ++i) {
334 MachineInstr *MI = Deads[i];
335 // Clear the "dead" flag.
336 for (auto &Op : MI->operands()) {
337 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
341 // Extend the live segment to the beginning of the next one.
342 LiveInterval::iterator End = LI.end();
343 SlotIndex S = LIS->getInstructionIndex(MI).getRegSlot();
344 LiveInterval::iterator T = LI.FindSegmentContaining(S);
346 LiveInterval::iterator N = std::next(T);
350 T->end = LIS->getMBBEndIdx(MI->getParent());
352 updateKillFlags(Reg, LI);
356 /// Given an updated live interval LI for register Reg, update the kill flags
357 /// in instructions using Reg to reflect the liveness changes.
358 void HexagonExpandCondsets::updateKillFlags(unsigned Reg, LiveInterval &LI) {
359 MRI->clearKillFlags(Reg);
360 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
361 SlotIndex EX = I->end;
362 if (!EX.isRegister())
364 MachineInstr *MI = LIS->getInstructionFromIndex(EX);
365 for (auto &Op : MI->operands()) {
366 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
368 // Only set the kill flag on the first encountered use of Reg in this
377 /// When adding a new instruction to liveness, the newly added definition
378 /// will start a new live segment. This may happen at a position that falls
379 /// within an existing live segment. In such case that live segment needs to
380 /// be truncated to make room for the new segment. Ultimately, the truncation
381 /// will occur at the last use, but for now the segment can be terminated
382 /// right at the place where the new segment will start. The segments will be
383 /// shrunk-to-uses later.
384 void HexagonExpandCondsets::terminateSegment(LiveInterval::iterator LT,
385 SlotIndex S, LiveInterval &LI) {
386 // Terminate the live segment pointed to by LT within a live interval LI.
390 VNInfo *OldVN = LT->valno;
391 SlotIndex EX = LT->end;
393 // If LT does not end at a block boundary, the termination is done.
397 // If LT ended at a block boundary, it's possible that its value number
398 // is picked up at the beginning other blocks. Create a new value number
399 // and change such blocks to use it instead.
401 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
402 if (!I->start.isBlock() || I->valno != OldVN)
404 // Generate on-demand a new value number that is defined by the
405 // block beginning (i.e. -phi).
407 NewVN = LI.getNextValue(I->start, LIS->getVNInfoAllocator());
413 /// Add the specified instruction to live intervals. This function is used
414 /// to update the live intervals while the program code is being changed.
415 /// Neither the expansion of a MUX, nor the predication are atomic, and this
416 /// function is used to update the live intervals while these transformations
418 void HexagonExpandCondsets::addInstrToLiveness(MachineInstr *MI) {
419 SlotIndex MX = LIS->isNotInMIMap(MI) ? LIS->InsertMachineInstrInMaps(MI)
420 : LIS->getInstructionIndex(MI);
421 DEBUG(dbgs() << "adding liveness info for instr\n " << MX << " " << *MI);
423 MX = MX.getRegSlot();
424 bool Predicated = HII->isPredicated(MI);
425 MachineBasicBlock *MB = MI->getParent();
427 // Strip all implicit uses from predicated instructions. They will be
428 // added again, according to the updated information.
430 removeImplicitUses(MI);
432 // For each def in MI we need to insert a new live segment starting at MX
433 // into the interval. If there already exists a live segment in the interval
434 // that contains MX, we need to terminate it at MX.
435 SmallVector<RegisterRef,2> Defs;
436 for (auto &Op : MI->operands())
437 if (Op.isReg() && Op.isDef())
438 Defs.push_back(RegisterRef(Op));
440 for (unsigned i = 0, n = Defs.size(); i < n; ++i) {
441 unsigned DefR = Defs[i].Reg;
442 LiveInterval &LID = LIS->getInterval(DefR);
443 DEBUG(dbgs() << "adding def " << PrintReg(DefR, TRI)
444 << " with interval\n " << LID << "\n");
445 // If MX falls inside of an existing live segment, terminate it.
446 LiveInterval::iterator LT = LID.FindSegmentContaining(MX);
448 terminateSegment(LT, MX, LID);
449 DEBUG(dbgs() << "after terminating segment\n " << LID << "\n");
451 // Create a new segment starting from MX.
452 LiveInterval::iterator P = prevSegment(LID, MX), N = nextSegment(LID, MX);
454 VNInfo *VN = LID.getNextValue(MX, LIS->getVNInfoAllocator());
455 if (N == LID.end()) {
456 // There is no live segment after MX. End this segment at the end of
458 EX = LIS->getMBBEndIdx(MB);
460 // If the next segment starts at the block boundary, end the new segment
461 // at the boundary of the preceding block (i.e. the previous index).
462 // Otherwise, end the segment at the beginning of the next segment. In
463 // either case it will be "shrunk-to-uses" later.
464 EX = N->start.isBlock() ? N->start.getPrevIndex() : N->start;
467 // Predicated instruction will have an implicit use of the defined
468 // register. This is necessary so that this definition will not make
469 // any previous definitions dead. If there are no previous live
470 // segments, still add the implicit use, but make it "undef".
471 // Because of the implicit use, the preceding definition is not
472 // dead. Mark is as such (if necessary).
473 MachineOperand ImpUse = MachineOperand::CreateReg(DefR, false, true);
474 ImpUse.setSubReg(Defs[i].Sub);
479 // If the previous segment extends to the end of the previous block,
480 // the end index may actually be the beginning of this block. If
481 // the previous segment ends at a block boundary, move it back by one,
482 // to get the proper block for it.
483 SlotIndex PE = P->end.isBlock() ? P->end.getPrevIndex() : P->end;
484 MachineBasicBlock *PB = LIS->getMBBFromIndex(PE);
485 if (PB != MB && !LIS->isLiveInToMBB(LID, MB))
489 makeUndead(DefR, P->valno->def);
490 // We are adding a live use, so extend the previous segment to
494 ImpUse.setIsUndef(true);
497 if (!MI->readsRegister(DefR))
498 MI->addOperand(ImpUse);
500 makeDefined(DefR, N->start, true);
502 LiveRange::Segment NR = LiveRange::Segment(MX, EX, VN);
504 DEBUG(dbgs() << "added a new segment " << NR << "\n " << LID << "\n");
505 shrinkToUses(DefR, LID);
506 DEBUG(dbgs() << "updated imp-uses: " << *MI);
510 // For each use in MI:
511 // - If there is no live segment that contains MX for the used register,
512 // extend the previous one. Ignore implicit uses.
513 for (auto &Op : MI->operands()) {
514 if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef())
516 unsigned UseR = Op.getReg();
517 LiveInterval &LIU = LIS->getInterval(UseR);
518 // Find the last segment P that starts before MX.
519 LiveInterval::iterator P = LIU.FindSegmentContaining(MX);
521 P = prevSegment(LIU, MX);
523 assert(P != LIU.end() && "MI uses undefined register?");
524 SlotIndex EX = P->end;
525 // If P contains MX, there is not much to do.
530 // Otherwise, extend P to "next(MX)".
531 P->end = MX.getNextIndex();
533 // Get the old "kill" instruction, and remove the kill flag.
534 if (MachineInstr *KI = LIS->getInstructionFromIndex(MX))
535 KI->clearRegisterKills(UseR, nullptr);
536 shrinkToUses(UseR, LIU);
542 /// Update the live interval information to reflect the removal of the given
543 /// instruction from the program. As with "addInstrToLiveness", this function
544 /// is called while the program code is being changed.
545 void HexagonExpandCondsets::removeInstrFromLiveness(MachineInstr *MI) {
546 SlotIndex MX = LIS->getInstructionIndex(MI).getRegSlot();
547 DEBUG(dbgs() << "removing instr\n " << MX << " " << *MI);
549 // For each def in MI:
550 // If MI starts a live segment, merge this segment with the previous segment.
552 for (auto &Op : MI->operands()) {
553 if (!Op.isReg() || !Op.isDef())
555 unsigned DefR = Op.getReg();
556 LiveInterval &LID = LIS->getInterval(DefR);
557 LiveInterval::iterator LT = LID.FindSegmentContaining(MX);
558 assert(LT != LID.end() && "Expecting live segments");
559 DEBUG(dbgs() << "removing def at " << MX << " of " << PrintReg(DefR, TRI)
560 << " with interval\n " << LID << "\n");
564 VNInfo *MVN = LT->valno;
565 if (LT != LID.begin()) {
566 // If the current live segment is not the first, the task is easy. If
567 // the previous segment continues into the current block, extend it to
568 // the end of the current one, and merge the value numbers.
569 // Otherwise, remove the current segment, and make the end of it "undef".
570 LiveInterval::iterator P = std::prev(LT);
571 SlotIndex PE = P->end.isBlock() ? P->end.getPrevIndex() : P->end;
572 MachineBasicBlock *MB = MI->getParent();
573 MachineBasicBlock *PB = LIS->getMBBFromIndex(PE);
574 if (PB != MB && !LIS->isLiveInToMBB(LID, MB)) {
575 makeDefined(DefR, LT->end, false);
576 LID.removeSegment(*LT);
578 // Make the segments adjacent, so that merge-vn can also merge the
581 makeUndead(DefR, P->valno->def);
582 LID.MergeValueNumberInto(MVN, P->valno);
585 LiveInterval::iterator N = std::next(LT);
586 LiveInterval::iterator RmB = LT, RmE = N;
587 while (N != LID.end()) {
588 // Iterate until the first register-based definition is found
589 // (i.e. skip all block-boundary entries).
590 LiveInterval::iterator Next = std::next(N);
591 if (N->start.isRegister()) {
592 makeDefined(DefR, N->start, false);
595 if (N->end.isRegister()) {
596 makeDefined(DefR, N->end, false);
603 // Erase the segments in one shot to avoid invalidating iterators.
604 LID.segments.erase(RmB, RmE);
608 for (LiveInterval::iterator I = LID.begin(), E = LID.end(); I != E; ++I) {
617 DEBUG(dbgs() << "new interval: ");
619 DEBUG(dbgs() << LID << "\n");
622 DEBUG(dbgs() << "<empty>\n");
623 LIS->removeInterval(DefR);
627 // For uses there is nothing to do. The intervals will be updated via
629 SmallVector<unsigned,4> Uses;
630 for (auto &Op : MI->operands()) {
631 if (!Op.isReg() || !Op.isUse())
633 unsigned R = Op.getReg();
634 if (!TargetRegisterInfo::isVirtualRegister(R))
638 LIS->RemoveMachineInstrFromMaps(MI);
639 MI->eraseFromParent();
640 for (unsigned i = 0, n = Uses.size(); i < n; ++i) {
641 LiveInterval &LI = LIS->getInterval(Uses[i]);
642 shrinkToUses(Uses[i], LI);
647 /// Get the opcode for a conditional transfer of the value in SO (source
648 /// operand). The condition (true/false) is given in Cond.
649 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
651 using namespace Hexagon;
655 if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
656 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
657 assert(VC->begin() != VC->end() && "Empty register class");
658 PhysR = *VC->begin();
660 assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
663 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
664 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
665 switch (RC->getSize()) {
667 return Cond ? A2_tfrt : A2_tfrf;
669 return Cond ? A2_tfrpt : A2_tfrpf;
671 llvm_unreachable("Invalid register operand");
673 if (SO.isImm() || SO.isFPImm())
674 return Cond ? C2_cmoveit : C2_cmoveif;
675 llvm_unreachable("Unexpected source operand");
679 /// Generate a conditional transfer, copying the value SrcOp to the
680 /// destination register DstR:DstSR, and using the predicate register from
681 /// PredOp. The Cond argument specifies whether the predicate is to be
682 /// if(PredOp), or if(!PredOp).
683 MachineInstr *HexagonExpandCondsets::genTfrFor(MachineOperand &SrcOp,
684 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, bool Cond) {
685 MachineInstr *MI = SrcOp.getParent();
686 MachineBasicBlock &B = *MI->getParent();
687 MachineBasicBlock::iterator At = MI;
688 DebugLoc DL = MI->getDebugLoc();
690 // Don't avoid identity copies here (i.e. if the source and the destination
691 // are the same registers). It is actually better to generate them here,
692 // since this would cause the copy to potentially be predicated in the next
693 // step. The predication will remove such a copy if it is unable to
696 unsigned Opc = getCondTfrOpcode(SrcOp, Cond);
697 MachineInstr *TfrI = BuildMI(B, At, DL, HII->get(Opc))
698 .addReg(DstR, RegState::Define, DstSR)
701 // We don't want any kills yet.
702 TfrI->clearKillInfo();
703 DEBUG(dbgs() << "created an initial copy: " << *TfrI);
708 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
709 /// performs all necessary changes to complete the replacement.
710 bool HexagonExpandCondsets::split(MachineInstr *MI) {
711 if (TfrLimitActive) {
712 if (TfrCounter >= TfrLimit)
716 DEBUG(dbgs() << "\nsplitting BB#" << MI->getParent()->getNumber()
718 MachineOperand &MD = MI->getOperand(0); // Definition
719 MachineOperand &MP = MI->getOperand(1); // Predicate register
721 unsigned DR = MD.getReg(), DSR = MD.getSubReg();
723 // First, create the two invididual conditional transfers, and add each
724 // of them to the live intervals information. Do that first and then remove
725 // the old instruction from live intervals.
726 if (MachineInstr *TfrT = genTfrFor(MI->getOperand(2), DR, DSR, MP, true))
727 addInstrToLiveness(TfrT);
728 if (MachineInstr *TfrF = genTfrFor(MI->getOperand(3), DR, DSR, MP, false))
729 addInstrToLiveness(TfrF);
730 removeInstrFromLiveness(MI);
736 /// Split all MUX instructions in the given block into pairs of contitional
738 bool HexagonExpandCondsets::splitInBlock(MachineBasicBlock &B) {
739 bool Changed = false;
740 MachineBasicBlock::iterator I, E, NextI;
741 for (I = B.begin(), E = B.end(); I != E; I = NextI) {
742 NextI = std::next(I);
750 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
751 if (HII->isPredicated(MI) || !HII->isPredicable(MI))
753 if (MI->hasUnmodeledSideEffects() || MI->mayStore())
755 // Reject instructions with multiple defs (e.g. post-increment loads).
757 for (auto &Op : MI->operands()) {
758 if (!Op.isReg() || !Op.isDef())
764 for (auto &Mo : MI->memoperands())
765 if (Mo->isVolatile())
771 /// Find the reaching definition for a predicated use of RD. The RD is used
772 /// under the conditions given by PredR and Cond, and this function will ignore
773 /// definitions that set RD under the opposite conditions.
774 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
775 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
776 MachineBasicBlock &B = *UseIt->getParent();
777 MachineBasicBlock::iterator I = UseIt, S = B.begin();
781 bool PredValid = true;
784 MachineInstr *MI = &*I;
785 // Check if this instruction can be ignored, i.e. if it is predicated
786 // on the complementary condition.
787 if (PredValid && HII->isPredicated(MI)) {
788 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(MI)))
792 // Check the defs. If the PredR is defined, invalidate it. If RD is
793 // defined, return the instruction or 0, depending on the circumstances.
794 for (auto &Op : MI->operands()) {
795 if (!Op.isReg() || !Op.isDef())
798 if (RR.Reg == PredR) {
802 if (RR.Reg != RD.Reg)
804 // If the "Reg" part agrees, there is still the subregister to check.
805 // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but
806 // not vreg1 (w/o subregisters).
807 if (RR.Sub == RD.Sub)
809 if (RR.Sub == 0 || RD.Sub == 0)
811 // We have different subregisters, so we can continue looking.
819 /// Check if the instruction MI can be safely moved over a set of instructions
820 /// whose side-effects (in terms of register defs and uses) are expressed in
821 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
822 /// that depend on the same predicate register to allow moving instructions
823 /// over instructions predicated on the opposite condition.
824 bool HexagonExpandCondsets::canMoveOver(MachineInstr *MI, ReferenceMap &Defs,
825 ReferenceMap &Uses) {
826 // In order to be able to safely move MI over instructions that define
827 // "Defs" and use "Uses", no def operand from MI can be defined or used
828 // and no use operand can be defined.
829 for (auto &Op : MI->operands()) {
833 // For physical register we would need to check register aliases, etc.
834 // and we don't want to bother with that. It would be of little value
835 // before the actual register rewriting (from virtual to physical).
836 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
838 // No redefs for any operand.
839 if (isRefInMap(RR, Defs, Exec_Then))
841 // For defs, there cannot be uses.
842 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
849 /// Check if the instruction accessing memory (TheI) can be moved to the
851 bool HexagonExpandCondsets::canMoveMemTo(MachineInstr *TheI, MachineInstr *ToI,
853 bool IsLoad = TheI->mayLoad(), IsStore = TheI->mayStore();
854 if (!IsLoad && !IsStore)
856 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
858 if (TheI->hasUnmodeledSideEffects())
861 MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI;
862 MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI;
863 bool Ordered = TheI->hasOrderedMemoryRef();
865 // Search for aliased memory reference in (StartI, EndI).
866 for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) {
867 MachineInstr *MI = &*I;
868 if (MI->hasUnmodeledSideEffects())
870 bool L = MI->mayLoad(), S = MI->mayStore();
873 if (Ordered && MI->hasOrderedMemoryRef())
876 bool Conflict = (L && IsStore) || S;
884 /// Generate a predicated version of MI (where the condition is given via
885 /// PredR and Cond) at the point indicated by Where.
886 void HexagonExpandCondsets::predicateAt(RegisterRef RD, MachineInstr *MI,
887 MachineBasicBlock::iterator Where, unsigned PredR, bool Cond) {
888 // The problem with updating live intervals is that we can move one def
889 // past another def. In particular, this can happen when moving an A2_tfrt
890 // over an A2_tfrf defining the same register. From the point of view of
891 // live intervals, these two instructions are two separate definitions,
892 // and each one starts another live segment. LiveIntervals's "handleMove"
893 // does not allow such moves, so we need to handle it ourselves. To avoid
894 // invalidating liveness data while we are using it, the move will be
895 // implemented in 4 steps: (1) add a clone of the instruction MI at the
896 // target location, (2) update liveness, (3) delete the old instruction,
897 // and (4) update liveness again.
899 MachineBasicBlock &B = *MI->getParent();
900 DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction.
901 unsigned Opc = MI->getOpcode();
902 unsigned PredOpc = HII->getCondOpcode(Opc, !Cond);
903 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
904 unsigned Ox = 0, NP = MI->getNumOperands();
905 // Skip all defs from MI first.
907 MachineOperand &MO = MI->getOperand(Ox);
908 if (!MO.isReg() || !MO.isDef())
912 // Add the new def, then the predicate register, then the rest of the
914 MB.addReg(RD.Reg, RegState::Define, RD.Sub);
917 MachineOperand &MO = MI->getOperand(Ox);
918 if (!MO.isReg() || !MO.isImplicit())
923 MachineFunction &MF = *B.getParent();
924 MachineInstr::mmo_iterator I = MI->memoperands_begin();
925 unsigned NR = std::distance(I, MI->memoperands_end());
926 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(NR);
927 for (unsigned i = 0; i < NR; ++i)
929 MB.setMemRefs(MemRefs, MemRefs+NR);
931 MachineInstr *NewI = MB;
932 NewI->clearKillInfo();
933 addInstrToLiveness(NewI);
937 /// In the range [First, Last], rename all references to the "old" register RO
938 /// to the "new" register RN, but only in instructions predicated on the given
940 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
941 unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
942 MachineBasicBlock::iterator Last) {
943 MachineBasicBlock::iterator End = std::next(Last);
944 for (MachineBasicBlock::iterator I = First; I != End; ++I) {
945 MachineInstr *MI = &*I;
946 // Do not touch instructions that are not predicated, or are predicated
947 // on the opposite condition.
948 if (!HII->isPredicated(MI))
950 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI)))
953 for (auto &Op : MI->operands()) {
954 if (!Op.isReg() || RO != RegisterRef(Op))
957 Op.setSubReg(RN.Sub);
958 // In practice, this isn't supposed to see any defs.
959 assert(!Op.isDef() && "Not expecting a def");
965 /// For a given conditional copy, predicate the definition of the source of
966 /// the copy under the given condition (using the same predicate register as
968 bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond) {
969 // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
970 unsigned Opc = TfrI->getOpcode();
972 assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
973 DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
976 MachineOperand &MD = TfrI->getOperand(0);
977 MachineOperand &MP = TfrI->getOperand(1);
978 MachineOperand &MS = TfrI->getOperand(2);
979 // The source operand should be a <kill>. This is not strictly necessary,
980 // but it makes things a lot simpler. Otherwise, we would need to rename
981 // some registers, which would complicate the transformation considerably.
986 unsigned PredR = MP.getReg();
987 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond);
988 if (!DefI || !isPredicable(DefI))
991 DEBUG(dbgs() << "Source def: " << *DefI);
993 // Collect the information about registers defined and used between the
994 // DefI and the TfrI.
995 // Map: reg -> bitmask of subregs
996 ReferenceMap Uses, Defs;
997 MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI;
999 // Check if the predicate register is valid between DefI and TfrI.
1000 // If it is, we can then ignore instructions predicated on the negated
1001 // conditions when collecting def and use information.
1002 bool PredValid = true;
1003 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
1004 if (!I->modifiesRegister(PredR, 0))
1010 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
1011 MachineInstr *MI = &*I;
1012 // If this instruction is predicated on the same register, it could
1013 // potentially be ignored.
1014 // By default assume that the instruction executes on the same condition
1015 // as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
1016 unsigned Exec = Exec_Then | Exec_Else;
1017 if (PredValid && HII->isPredicated(MI) && MI->readsRegister(PredR))
1018 Exec = (Cond == HII->isPredicatedTrue(MI)) ? Exec_Then : Exec_Else;
1020 for (auto &Op : MI->operands()) {
1023 // We don't want to deal with physical registers. The reason is that
1024 // they can be aliased with other physical registers. Aliased virtual
1025 // registers must share the same register number, and can only differ
1026 // in the subregisters, which we are keeping track of. Physical
1027 // registers ters no longer have subregisters---their super- and
1028 // subregisters are other physical registers, and we are not checking
1030 RegisterRef RR = Op;
1031 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
1034 ReferenceMap &Map = Op.isDef() ? Defs : Uses;
1035 addRefToMap(RR, Map, Exec);
1042 // RD = TfrI ..., RT
1044 // If the register-in-the-middle (RT) is used or redefined between
1045 // DefI and TfrI, we may not be able proceed with this transformation.
1046 // We can ignore a def that will not execute together with TfrI, and a
1047 // use that will. If there is such a use (that does execute together with
1048 // TfrI), we will not be able to move DefI down. If there is a use that
1049 // executed if TfrI's condition is false, then RT must be available
1050 // unconditionally (cannot be predicated).
1051 // Essentially, we need to be able to rename RT to RD in this segment.
1052 if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else))
1054 RegisterRef RD = MD;
1055 // If the predicate register is defined between DefI and TfrI, the only
1056 // potential thing to do would be to move the DefI down to TfrI, and then
1057 // predicate. The reaching def (DefI) must be movable down to the location
1059 // If the target register of the TfrI (RD) is not used or defined between
1060 // DefI and TfrI, consider moving TfrI up to DefI.
1061 bool CanUp = canMoveOver(TfrI, Defs, Uses);
1062 bool CanDown = canMoveOver(DefI, Defs, Uses);
1063 // The TfrI does not access memory, but DefI could. Check if it's safe
1064 // to move DefI down to TfrI.
1065 if (DefI->mayLoad() || DefI->mayStore())
1066 if (!canMoveMemTo(DefI, TfrI, true))
1069 DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
1070 << ", can move down: " << (CanDown ? "yes\n" : "no\n"));
1071 MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
1073 predicateAt(RD, DefI, PastDefIt, PredR, Cond);
1075 predicateAt(RD, DefI, TfrIt, PredR, Cond);
1080 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt);
1082 // Delete the user of RT first (it should work either way, but this order
1083 // of deleting is more natural).
1084 removeInstrFromLiveness(TfrI);
1085 removeInstrFromLiveness(DefI);
1090 /// Predicate all cases of conditional copies in the specified block.
1091 bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B) {
1092 bool Changed = false;
1093 MachineBasicBlock::iterator I, E, NextI;
1094 for (I = B.begin(), E = B.end(); I != E; I = NextI) {
1095 NextI = std::next(I);
1096 unsigned Opc = I->getOpcode();
1097 if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
1098 bool Done = predicate(I, (Opc == Hexagon::A2_tfrt));
1100 // If we didn't predicate I, we may need to remove it in case it is
1101 // an "identity" copy, e.g. vreg1 = A2_tfrt vreg2, vreg1.
1102 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2)))
1103 removeInstrFromLiveness(I);
1112 void HexagonExpandCondsets::removeImplicitUses(MachineInstr *MI) {
1113 for (unsigned i = MI->getNumOperands(); i > 0; --i) {
1114 MachineOperand &MO = MI->getOperand(i-1);
1115 if (MO.isReg() && MO.isUse() && MO.isImplicit())
1116 MI->RemoveOperand(i-1);
1121 void HexagonExpandCondsets::removeImplicitUses(MachineBasicBlock &B) {
1122 for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
1123 MachineInstr *MI = &*I;
1124 if (HII->isPredicated(MI))
1125 removeImplicitUses(MI);
1130 void HexagonExpandCondsets::postprocessUndefImplicitUses(MachineBasicBlock &B) {
1131 // Implicit uses that are "undef" are only meaningful (outside of the
1132 // internals of this pass) when the instruction defines a subregister,
1133 // and the implicit-undef use applies to the defined register. In such
1134 // cases, the proper way to record the information in the IR is to mark
1135 // the definition as "undef", which will be interpreted as "read-undef".
1136 typedef SmallSet<unsigned,2> RegisterSet;
1137 for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
1138 MachineInstr *MI = &*I;
1140 for (unsigned i = MI->getNumOperands(); i > 0; --i) {
1141 MachineOperand &MO = MI->getOperand(i-1);
1142 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.isUndef()) {
1143 MI->RemoveOperand(i-1);
1144 Undefs.insert(MO.getReg());
1147 for (auto &Op : MI->operands()) {
1148 if (!Op.isReg() || !Op.isDef() || !Op.getSubReg())
1150 if (Undefs.count(Op.getReg()))
1151 Op.setIsUndef(true);
1157 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
1158 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
1160 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
1161 if (RC == &Hexagon::IntRegsRegClass) {
1165 if (RC == &Hexagon::DoubleRegsRegClass) {
1166 BW = (RR.Sub != 0) ? 32 : 64;
1173 bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) {
1174 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
1175 LiveRange::Segment &LR = *I;
1176 // Range must start at a register...
1177 if (!LR.start.isRegister())
1179 // ...and end in a register or in a dead slot.
1180 if (!LR.end.isRegister() && !LR.end.isDead())
1187 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
1188 if (CoaLimitActive) {
1189 if (CoaCounter >= CoaLimit)
1194 if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2)
1196 if (MRI->isLiveIn(R1.Reg))
1198 if (MRI->isLiveIn(R2.Reg))
1201 LiveInterval &L1 = LIS->getInterval(R1.Reg);
1202 LiveInterval &L2 = LIS->getInterval(R2.Reg);
1203 bool Overlap = L1.overlaps(L2);
1205 DEBUG(dbgs() << "compatible registers: ("
1206 << (Overlap ? "overlap" : "disjoint") << ")\n "
1207 << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
1208 << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
1209 if (R1.Sub || R2.Sub)
1214 // Coalescing could have a negative impact on scheduling, so try to limit
1215 // to some reasonable extent. Only consider coalescing segments, when one
1216 // of them does not cross basic block boundaries.
1217 if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
1220 MRI->replaceRegWith(R2.Reg, R1.Reg);
1222 // Move all live segments from L2 to L1.
1223 typedef DenseMap<VNInfo*,VNInfo*> ValueInfoMap;
1225 for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
1226 VNInfo *NewVN, *OldVN = I->valno;
1227 ValueInfoMap::iterator F = VM.find(OldVN);
1228 if (F == VM.end()) {
1229 NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator());
1230 VM.insert(std::make_pair(OldVN, NewVN));
1234 L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
1236 while (L2.begin() != L2.end())
1237 L2.removeSegment(*L2.begin());
1239 updateKillFlags(R1.Reg, L1);
1240 DEBUG(dbgs() << "coalesced: " << L1 << "\n");
1247 /// Attempt to coalesce one of the source registers to a MUX intruction with
1248 /// the destination register. This could lead to having only one predicated
1249 /// instruction in the end instead of two.
1250 bool HexagonExpandCondsets::coalesceSegments(MachineFunction &MF) {
1251 SmallVector<MachineInstr*,16> Condsets;
1252 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
1253 MachineBasicBlock &B = *I;
1254 for (MachineBasicBlock::iterator J = B.begin(), F = B.end(); J != F; ++J) {
1255 MachineInstr *MI = &*J;
1258 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
1259 if (!S1.isReg() && !S2.isReg())
1261 Condsets.push_back(MI);
1265 bool Changed = false;
1266 for (unsigned i = 0, n = Condsets.size(); i < n; ++i) {
1267 MachineInstr *CI = Condsets[i];
1268 RegisterRef RD = CI->getOperand(0);
1269 RegisterRef RP = CI->getOperand(1);
1270 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
1272 // Consider this case:
1273 // vreg1 = instr1 ...
1274 // vreg2 = instr2 ...
1275 // vreg0 = C2_mux ..., vreg1, vreg2
1276 // If vreg0 was coalesced with vreg1, we could end up with the following
1278 // vreg0 = instr1 ...
1279 // vreg2 = instr2 ...
1280 // vreg0 = A2_tfrf ..., vreg2
1281 // which will later become:
1282 // vreg0 = instr1 ...
1283 // vreg0 = instr2_cNotPt ...
1284 // i.e. there will be an unconditional definition (instr1) of vreg0
1285 // followed by a conditional one. The output dependency was there before
1286 // and it unavoidable, but if instr1 is predicable, we will no longer be
1287 // able to predicate it here.
1288 // To avoid this scenario, don't coalesce the destination register with
1289 // a source register that is defined by a predicable instruction.
1291 RegisterRef RS = S1;
1292 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
1293 if (!RDef || !HII->isPredicable(RDef))
1294 Done = coalesceRegisters(RD, RegisterRef(S1));
1296 if (!Done && S2.isReg()) {
1297 RegisterRef RS = S2;
1298 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
1299 if (!RDef || !HII->isPredicable(RDef))
1300 Done = coalesceRegisters(RD, RegisterRef(S2));
1308 bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
1309 HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
1310 TRI = MF.getSubtarget().getRegisterInfo();
1311 LIS = &getAnalysis<LiveIntervals>();
1312 MRI = &MF.getRegInfo();
1314 bool Changed = false;
1316 // Try to coalesce the target of a mux with one of its sources.
1317 // This could eliminate a register copy in some circumstances.
1318 Changed |= coalesceSegments(MF);
1320 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
1321 // First, simply split all muxes into a pair of conditional transfers
1322 // and update the live intervals to reflect the new arrangement.
1323 // This is done mainly to make the live interval update simpler, than it
1324 // would be while trying to predicate instructions at the same time.
1325 Changed |= splitInBlock(*I);
1326 // Traverse all blocks and collapse predicable instructions feeding
1327 // conditional transfers into predicated instructions.
1328 // Walk over all the instructions again, so we may catch pre-existing
1329 // cases that were not created in the previous step.
1330 Changed |= predicateInBlock(*I);
1333 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
1334 postprocessUndefImplicitUses(*I);
1339 //===----------------------------------------------------------------------===//
1340 // Public Constructor Functions
1341 //===----------------------------------------------------------------------===//
1343 static void initializePassOnce(PassRegistry &Registry) {
1344 const char *Name = "Hexagon Expand Condsets";
1345 PassInfo *PI = new PassInfo(Name, "expand-condsets",
1346 &HexagonExpandCondsets::ID, 0, false, false);
1347 Registry.registerPass(*PI, true);
1350 void llvm::initializeHexagonExpandCondsetsPass(PassRegistry &Registry) {
1351 CALL_ONCE_INITIALIZATION(initializePassOnce)
1355 FunctionPass *llvm::createHexagonExpandCondsets() {
1356 return new HexagonExpandCondsets();